JP3440764B2 - Liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a liquid crystal display device, and more particularly to a semiconductor device suitable for use as a thin film semiconductor device and an active matrix type liquid crystal display device using the thin film semiconductor device.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device using thin film transistors (hereinafter referred to as TFTs) is known as a display device for image information and character information in office automation equipment and the like. In the conventional liquid crystal display device of this type, high definition and high image quality are important issues along with cost reduction. In order to solve these problems, it is essential to improve the performance of the TFT, which is a key device. In forming a high-performance TFT on an inexpensive glass substrate, for example, 198
5th Conference Record of International Display Research Conference (Confere
nce Record of International Display Research Confe
rence) As described on page 9, it has been attempted to reduce the cost by configuring the peripheral drive circuit for driving the TFT active matrix also with the TFT and integrating them on the same substrate. If higher-performance peripheral drive circuits can be integrated on the glass substrate, the circuit configuration and the mounting process to be mounted on the outside can be simplified, and a significant reduction in mounting cost can be expected. Higher performance TF for constructing high-performance circuits
T is required. In particular, in a TFT formed on a polycrystalline silicon (hereinafter referred to as poly-Si) film, which is currently most expected as a TFT for a peripheral drive circuit integrated type display device, the carrier mobility is improved and the threshold voltage (V
The reduction of th) is an important technical issue.

As a method of lowering Vth in a transistor formed on an insulator to realize operation at a lower voltage, 1994 Technical Digest of
International Electron Device Meeting (Technical Digest of International Electron D
evice Meeting). On page 809 thereof, what is called a dynamic threshold voltage MOSFET (Dynamic Threshold Voltage MOSFET) is provided in which a semiconductor film to be an active layer is provided with a fourth contact in addition to a source and a drain and is connected to a gate electrode to perform a bipolar operation.
Silicon on Insulator (SOI) devices with submicron T: DTMOS are described.

[0004]

In the above-mentioned prior art, since the threshold voltage of the transistor is lowered to operate at a low voltage, the power supply voltage can be lowered to reduce the power consumption of the circuit. Is desirable as a driving element for a liquid crystal display device. However, this technique is obviously intended for a logic element or a memory element that operates at a high speed with a low voltage, and cannot be used as it is as a driving element for a liquid crystal display device.

That is, as described on page 809 of the above document, the semiconductor device obtained by the above-mentioned prior art is designed to operate effectively only in the region where the gate voltage is less than 0.6V. The semiconductor element obtained by the above-mentioned conventional technique cannot be directly applied to a liquid crystal display device in which the lower limit of the gate drive voltage is limited by the liquid crystal drive voltage. Specifically, in order to drive a general liquid crystal material, at least a peak amplitude of about ± 3 V is required, and the amplitude of the gate voltage of the pixel driving transistor must be at least the peak voltage for driving the liquid crystal. is necessary.
Therefore, the output voltage of the peripheral drive circuit is required to have an amplitude of at least about ± 3V. Therefore, it is difficult to directly apply the above-mentioned conventional element that operates effectively only when the gate voltage is less than 1 V to the liquid crystal display device.

An object of the present invention is to provide an active matrix type liquid crystal display device of low power consumption.

[0007]

According to the present invention, a semiconductor element as a switching element formed in a display area of a liquid crystal display device or a semiconductor element formed in a drive circuit area for driving the display area, First, second, third and fourth electrodes, a pair of one conductivity type semiconductor layers connected to the second and third electrodes and separated from each other, and connected to the pair of one conductivity type semiconductor layers And a second conductivity type semiconductor layer formed on the intrinsic semiconductor layer, the first electrode is formed on the intrinsic semiconductor layer via an insulating film, and the fourth electrode is It is formed on the other conductivity type semiconductor layer formed on the intrinsic semiconductor layer.

The pair of one conductivity type semiconductor layer and the other conductivity type semiconductor layer are preferably separated from each other by the intrinsic semiconductor layer. Furthermore, according to another embodiment, the region of the intrinsic semiconductor layer viewed from the direction perpendicular to the substrate extends from the region of the insulating layer in the direction of at least the pair of one-conductivity-type semiconductor layers.

It is preferable for the wiring of the liquid crystal display device to connect the first electrode and the fourth electrode via a resistor.

The true semiconductor layer, the one-conductivity-type semiconductor layer, and the other-conductivity-type semiconductor layer may be composed of a semiconductor thin film made of any one of silicon, silicon germanium, and silicon carbide.

Further, the intrinsic semiconductor layer, the one conductivity type semiconductor layer and the other conductivity type semiconductor layer may be composed of a polycrystalline silicon film. In particular, it is desirable to use a polycrystalline silicon film in a liquid crystal display device with a built-in drive circuit.

The semiconductor element can be constructed by any one of a planar type, an inverted stagger type and a normal stagger type. In the case of the inverted stagger type, a first electrode is formed on one substrate, an insulating layer is formed on the first electrode, an intrinsic semiconductor layer is formed on this insulating film, and a pair of intrinsic semiconductor layers is formed on the intrinsic semiconductor layer. On the other hand, a conductive semiconductor layer is formed. In the case of the planar type, the second electrode, the third electrode and the fourth electrode are formed on one substrate.

In the case of the positive stagger and the reverse stagger, the semiconductor layer of one of the one conductivity type and the semiconductor layer of the other conductivity type is used as a mask pattern to form the other semiconductor layer in a self-aligned manner. It is also possible to do so.

The semiconductor element of the present invention can be used as the n-type and p-type semiconductor elements of a complementary semiconductor device in the drive circuit region of a liquid crystal display device. Specifically, the driver circuit area has a vertical scanning circuit and a video signal driver circuit, and the complementary semiconductor device is applied to a shift register in these circuits. In particular, when the semiconductor element of the present invention is used in the drive circuit region of a liquid crystal display device with a built-in peripheral circuit, low power consumption is effective.

According to the present invention, an intrinsic semiconductor layer (i layer) is formed as a semiconductor layer formed between the first electrode, the second electrode and the third electrode, and the second electrode and the second electrode are formed. Current carriers having different polarities from the current carriers of the impurity semiconductor layer (one-side conductivity type semiconductor layer) connected to the third electrode are injected into the intrinsic semiconductor layer. With this configuration, when the impurity semiconductor layer connected to the second electrode and the third electrode is formed of an n-type semiconductor layer, p− is formed between the current carrier injection layer or the fourth electrode and the second electrode. An in junction is formed.

When the voltage between the current carrier injection layer or the fourth electrode and the second electrode is Vb, the voltage Vb is p-i.
It is possible to prevent an excessive current (base current) from flowing by being divided into the i-n junction and the i-layer of the -n junction. Therefore, it is possible to operate with low power up to a larger gate voltage (voltage applied to the first electrode). That is, when a p-type or n-type semiconductor layer is used instead of the intrinsic semiconductor,
All of Vb is added to the source junction, and when Vb exceeds the built-in voltage (about 0.6 V) of the source junction, an excessive base current flows and power consumption sharply increases. On the other hand, when the semiconductor layer is made of an intrinsic semiconductor, an excessive base current does not flow up to a higher Vb, and a low gate operation can be performed up to a higher gate voltage. In this case p-i
By adopting the -n junction, the degree of decrease in the threshold voltage is slightly reduced, but the threshold voltage can be made lower than that of the conventional element. This lowering of the threshold voltage makes it possible to lower the voltage of the liquid crystal driving element and the peripheral circuits, and it is possible to reduce the power consumption of the active matrix type display device.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, the semiconductor element has a gate electrode 10 made of chromium formed on a glass substrate 1 as a first electrode. The gate electrode 10 is covered with a gate insulating film 20 made of a silicon nitride film (SiN film). An intrinsic a-Si layer 30 is formed on the gate insulating film 20. Genuine a-S
An n-type a-Si layer 3 doped with phosphorus is formed on the i layer 30.
1, 32 are formed, and a p-type a-Si layer 33 doped with boron is formed.

The p-type a-Si layer 33 is the n-type a-Si layer 3
The n-type a is self-aligned using the patterns of 1, 32 as a mask.
It is formed between the -Si layers 31 and 32. n type a-S
When the n-type a-Si layer 32 is formed using the patterns of the i-layers 31 and 32 as a mask, the n-type a-Si layers 31 and 32 and the p-type a-Si layer 33 are formed by one photolithography process.
Since both can be formed, the manufacturing process can be simplified and the manufacturing cost can be reduced. As the second and third electrodes connected to the n-type a-Si layers 31 and 32, a source electrode 11 and a drain electrode 12 made of titanium are formed.
Further, a base electrode 14 that contacts the p-type a-Si layer 33 is formed as a hole injection electrode. Then, the protective insulating film 2 in which the entire element is made of a silicon nitride film (SiN film)
2 to cover an n-type field effect transistor.

That is, in the above embodiment, the majority carriers are electrons and the minority carriers are holes. Where p-type a-Si
By applying a positive voltage with respect to the source electrode 11 to the base electrode 14 in contact with the layer 33, holes that are minority carriers are injected into the intrinsic a-Si layer 30.

Next, the specific operation of the semiconductor device shown in FIG. 1 will be described with reference to FIGS.

In the n-type transistor, when the source electrode is set to the ground potential as shown in FIG. 2, positive voltages Vg and Vd are applied to the gate electrode 10 and the drain electrode 12, respectively, to bring them into a conductive state (on state). To realize.
At this time, in the transistor of the present invention, p
A positive voltage Vb is applied to the fourth electrode 14 (hereinafter referred to as the base electrode) that is in contact with the mold a-Si layer 33. By the positive potential Vb, the n-i-p junction composed of the n-type a-Si layer 31-intrinsic a-Si layer 30-p-type a-Si layer 33 in contact with the source electrode 11 is forward biased, p-type a-S
Holes are injected from the i layer 33. Φh represents the flow of injected holes. The injected holes drift toward the source electrode 11 and the n-type a-Si layer 31 and the intrinsic a-Si layer 3
It is blocked by the potential barrier of the n ⁺ / i junction formed with 0 and accumulates near the n ⁺ / i junction. The accumulated holes lower the potential barrier of the n ⁺ / i junction, and a large amount of electrons are injected from the n ⁺ layer to the channel ch formed at the interface between the intrinsic semiconductor layer and the gate insulating film 20. Φe represents the flow of injected electrons. As a result, a large increase in majority carrier (electron) current is realized by injecting a small amount of minority carriers (holes).

FIG. 3 is an energy band diagram of the source junction indicated by XX 'in FIG. Holes injected from the base electrode is blocked by the potential barrier of n ⁺ / i junction, to accumulate near n ⁺ / i junction. As a result, the potential energy of the intrinsic a-Si layer 30 changes from the dotted line showing the state before the hole accumulation to the solid line, and the potential barrier against a large amount of electrons existing in the n-type a-Si layer 31 decreases, which is indicated by φe. Thus, a large amount of electrons are injected toward the channel ch. On the other hand, in the cut-off state (off state), a negative voltage is applied to the gate electrode and a negative voltage is also applied to the base electrode, so that n−
By reverse biasing the ip junction, current injection can be interrupted by stopping injection of holes from the base.
Since the effect of the current multiplication is more remarkable in the subthreshold region where the electron current is limited by the injection from the source, the transfer characteristic shows that the current rise in the subthreshold region is increased as the base current ib increases as shown in FIG. The threshold voltage Vth changes so that the threshold voltage Vth decreases.

Further, in this embodiment, since the intrinsic a-Si layer 30 is used as the semiconductor layer, the base-source voltage Vb becomes the i-n junction and the i-layer of the p-i-n junction. It is possible to prevent an excessive current (base current) from flowing due to voltage division. Therefore, it is possible to operate at a low power up to a larger gate voltage, for example, a voltage exceeding ± 5V. Therefore, if a semiconductor element capable of lowering the threshold voltage is used as a liquid crystal driving element or an element of a peripheral circuit,
The power supply voltage can be lowered, and the power consumption of the active matrix display device can be reduced.

(Second Embodiment) FIG. 5 is a sectional view of a semiconductor device according to a second embodiment of the present invention. The semiconductor element in the present embodiment is configured as a positive stagger type TFT, and is formed on a glass substrate 1 in a state where a source electrode 11, a drain electrode 12 and a base electrode 14 made of chromium are separated from each other. . The source electrode 1
1 and the n-type a-Si on the drain electrode 12, respectively.
Layers 31 and 32 are formed, and a p-type a-Si layer 33 is formed on the base electrode 14. The n-type a
An intrinsic a-Si layer 30 formed on the -Si layer 31 and the p-type a-Si layer 33, a gate insulating film 20 formed of a silicon nitride film (SiN film) formed on the intrinsic a-Si layer 30, Through the gate insulating film 20, the intrinsic aS
The gate electrode 10 made of aluminum formed on the i layer 30 and the silicon nitride film (S
The protective insulating film 22 is made of an iN film).

In the semiconductor device of the present embodiment, the majority carriers are electrons and the minority carriers are holes, as in the above embodiments. Here, by applying a positive voltage to the source electrode 11 to the base electrode 14 in contact with the p-type a-Si layer 33, holes which are minority carriers are injected into the intrinsic a-Si layer 30. Thereby, the first
Similar to the principle of the above embodiment, the threshold voltage is reduced and the current driving capability is improved.

In the present embodiment, the intrinsic a-Si layer 30 is used as an active layer as in the above-mentioned embodiments, but this is made of another semiconductor material such as polycrystalline silicon (poly-Si). The same effect can be obtained by using an amorphous or polycrystalline silicon germanium thin film (SiGe).

(Third Embodiment) FIG. 6 is a sectional view of a semiconductor device according to a third embodiment of the present invention. The semiconductor element in the present embodiment is configured as a planar type TFT, and includes a base electrode 14 made of chromium on the glass substrate 1, and ap ⁺ layer 33 formed on the base electrode 14.
1, intrinsic semiconductor layer 30 formed on the p ⁺ layer 331
1, a gate insulating film 201 made of silicon dioxide (SiO ₂ ) formed on a part of the intrinsic semiconductor layer 301,
The gate electrode 10 made of aluminum formed on the gate insulating film 201, the n ⁺ layers 311, 321 and the n ⁺ layer 31 formed on a part of the intrinsic semiconductor layer 301.
1, a source electrode 11 and a drain electrode 12 made of chromium formed so as to be in contact with the first and the _second electrodes 321, a _second protective insulating film 21 made of SiO ₂ , and a protective insulating film 22 covering the entire element. Also in the present embodiment, as in the first embodiment, the majority carriers are electrons and the minority carriers are holes.

By applying a positive voltage with respect to the source electrode 11 to the base electrode 14 in contact with the p ⁺ layer 331, holes, which are minority carriers, are transferred to the intrinsic semiconductor layer 301.
Is injected into. As a result, the threshold voltage is lowered by the same principle of the semiconductor device shown in FIG. 1 and the current driving capability is improved.

Further, in the present embodiment, the n ⁺ layer 31
1, 321 are formed in self-alignment with the patterns of the gate insulating film 201 and the gate electrode 10.
That is, the n ⁺ layers 311 and 321 are formed by using the patterns of the gate insulating film 201 and the gate electrode 10 as a mask.
Are formed. As a result, both the patterns of the n ⁺ layers 311 and 321 and the gate electrode 10 can be formed by one photolithography process, which simplifies the manufacturing process and reduces the manufacturing cost. In addition, the gate electrode 10 and the n ⁺ layer 311 can be formed. Since the overlap width of 321 can be minimized and the parasitic capacitance between the gate electrode 10 and the source electrode 11 or the gate electrode 10 and the drain electrode 12 can be minimized, high-speed operation of the device becomes possible.

(Embodiment 4) Each of the semiconductor elements of the above-described embodiments is a four-terminal element including a gate, a source, a drain and a base. On the other hand, the transistor used in the conventional liquid crystal display device and its driving circuit is a three-terminal element. Therefore, in order to apply the element of the present invention to the conventional circuit system, a new wiring must be separately provided in order to supply the base current, the circuit layout becomes complicated, and the area occupied by the circuit increases.

Therefore, in this embodiment, as shown in FIG. 7, the gate electrode 10 and the base electrode 14 are connected by a resistor rb having an appropriate value in order to supply an appropriate current to the base.
Base current is supplied from the gate wiring. By doing this, it is not necessary to provide a new wiring exclusively for the base, so the wiring is simplified and the degree of circuit integration is improved.
Miniaturization becomes easy.

(Fifth Embodiment) FIG. 8 is a plan view of a planar type TFT according to the present invention. FIG. 9 is a sectional view taken along the line XX 'in FIG.

In this embodiment, the poly-Si intrinsic semiconductor layer 301 is used as a convex plane pattern, the pattern of the gate electrode 10 is arranged at the center thereof, and the source and drain n ⁺ layers 311 and 321 are arranged on the left and right sides thereof. Was formed. The n ⁺ layers 311 and 321 are formed on the glass substrate, similarly to the planar type transistor shown in FIG. On the upper protrusion of the convex intrinsic semiconductor layer 301, p serving as a base is formed.
^{The +} layer 331 is formed. The source electrode 11 and the drain electrode 12 are the source and drain n ⁺ layers 3 respectively.
11 and 321, and the base electrode 14 is p ⁺ of the base.
It is formed to be in contact with the layer 331. From the intrinsic semiconductor layer 301 (channel) below the gate electrode to the p ⁺ layer 33
1 is not doped with either p-type or n-type impurities to form a high resistance layer rb. The source / drain n ⁺ layers 311 and 321 and the base p ⁺ layer 331 are intrinsic semiconductor layers. It has a structure separated by 301.

Also in the present embodiment, as in the first embodiment, the majority carriers are electrons and the minority carriers are holes. By applying a positive voltage to the source electrode 11 to the base electrode 14 in contact with the n ⁺ layer 321, holes that are minority carriers are transferred to the intrinsic semiconductor layer 30.
Injected into 1. As a result, the threshold voltage is lowered by the same principle of the semiconductor device shown in FIG. 1 and the current driving capability is improved.

Further, in the present embodiment, by connecting the base electrode 14 and the gate electrode 10, the operation with the three-terminal structure as shown in FIG. 7 becomes possible. At this time,
Since the high resistance layer rb functions to limit the base current, excessive base current injection is prevented, and operation at low power is possible up to a larger gate voltage, for example, a voltage exceeding ± 5V.

The drain current-gate voltage characteristics and the drain current-drain voltage of the TFT of this embodiment are shown in FIGS. 25 (a) and 25 (b) in comparison with the TFT having the conventional structure, respectively. It is clear that the TFT of the present invention has a larger current driving capability than the conventional TFT.

(Embodiment 6) FIG. 10 is a plan view of a planar type TFT according to the present invention. FIG. 11 shows X- in FIG.
It is sectional drawing which follows the line shown by A.

In the embodiment, similarly to the fifth embodiment, the intrinsic semiconductor layer 301 is formed as a convex plane pattern, the pattern of the gate electrode 10 is arranged in the center thereof, and the source and drain of the source and drain are formed on both sides thereof. The n ⁺ layers 311 and 321 are formed, and the p ⁺ layer 331 serving as a base is formed on the upper protrusion of the convex intrinsic semiconductor layer 301. In addition, from the intrinsic semiconductor layer 301 (channel) below the gate electrode, p
^The high resistance layer rb, which is not doped with either p-type or n-type impurities, is formed in the portion reaching the ⁺ layer 331.
This is the same as the fifth embodiment. This embodiment is characterized in that an offset layer composed of the intrinsic semiconductor layer 301, roff, is formed between the n ⁺ layers 311 and 321 of the source and drain and the intrinsic semiconductor layer 301 (channel) directly below the gate electrode 10. There is. That is, the source / drain n ⁺ layers 311 and 321 and the base p ⁺ layer 331 have a structure separated by the intrinsic semiconductor layer 301. In order to realize such a structure, in the present embodiment, the pattern of the gate insulating film 20 is made slightly larger than the gate electrode 10, and the pattern of the gate insulating film 20 is used as a mask for the source and drain. n ⁺ layers 311 and 3
21 or a p ⁺ layer 331 serving as a base is formed.

Also in the present embodiment, the majority carriers are electrons and the minority carriers are holes, as in the first embodiment. Here, by applying a positive voltage to the source electrode 11 to the base electrode 14 in contact with the p ⁺ layer 331, holes that are minority carriers are transferred to the intrinsic semiconductor layer 3.
Injected at 01. As a result, the threshold voltage is lowered by the same principle of the semiconductor device shown in FIG. 1 and the current driving capability is improved. In addition, in the present embodiment, by connecting the base electrode 14 and the gate electrode 10, as shown in FIG.
It becomes possible to operate with a three-terminal configuration as shown in FIG. At this time, not only the high resistance layer rb but also the offset layer roff works so as to limit the base current, so that excessive base current injection can be further prevented and operation at low power up to a larger gate voltage becomes possible. Further, since the offset layer acts so as to relax the electric field between the source electrode 11 and the drain electrode 12, the generation of hot carriers is suppressed and the reliability of the device is improved.

(Embodiment 7) FIG. 12 is a circuit diagram when a complementary (CMOS) inverter circuit is constructed using the semiconductor elements shown in FIGS. 8 and 9, and FIG. 13 is shown in FIG. The pattern layout drawing of the shown inverter circuit is shown.
Such an inverter is used especially in a drive circuit of a liquid crystal display device. The complementary inverter according to the present embodiment includes a p-type transistor PMOS and an n-type transistor NM.
The gate and base of each transistor are connected via a base resistance rb.
TF in which the first wiring electrode 105 integrated with the gate electrode 10 of the TFT and the input terminal Vin has a convex pattern
The second wiring electrode 106 is extended to the vicinity of the protruding portion of T.
Is connected to the base electrode formed on the protruding portion via.

The electrodes for supplying the reference voltage Vss and the power supply voltage Vdd to the circuit and the output terminal Vout are also formed by the second wiring electrode 106. In order to realize high-speed circuit operation, the intrinsic semiconductor layer 30 having high carrier mobility is used.
1 is used for the active layer. Further, in order to prevent characteristic deterioration during operation due to hot carriers, the n-type transistor in which hot carriers are easily generated has a configuration having an offset layer roff as shown in FIG.

The transistor forming the present inverter circuit operates at a low threshold voltage due to the above-mentioned operation. It is possible to operate with a low power supply voltage and reduce the power consumption of the circuit. In addition, the input terminal and the base electrode 14 of the TFT
A high resistance rb is inserted between them to suppress the input current from the input terminal through the base electrode 14 to the source electrode, so that the power consumption can be reduced.

(Embodiment 8) FIG. 14 is a sectional view when a complementary (CMOS) inverter circuit is constructed using the inverted stagger type TFT shown in FIG. 1, and FIG. 15 is a pattern layout of the inverter circuit. The figure is shown. N shown on the left side of the figure
The structure of the type transistor is similar to that shown in FIG. However, in order to realize high-speed circuit operation, the intrinsic semiconductor layer 301 having high carrier mobility is used as the active layer. The p-type transistor shown on the right side of the figure has a structure complementary to the n-type transistor. That is, the n ⁺ layers 311 and 321 formed on the intrinsic semiconductor layer 301,
^The p ⁺ layer 331 is formed on the surface of the intrinsic semiconductor layer 301 in the region where the ⁺ layers 311 and 321 are not formed. In the p-type transistor, electrons, which are minority carriers, are injected from the base electrode 14 through the n ⁺ layer 311, and the threshold voltage is lowered by the same action as in the n-type transistor. Therefore, the inverter configured by the element of the present invention can switch at a low input voltage Vin, and the power consumption of the circuit can be reduced. Further, the bases of the p-type transistor and the n-type transistor are connected to the gate electrode via the base resistance rb, as in the embodiment shown in FIG. Thereby, the input current from the input terminal to the source electrode via the base electrode 14 is suppressed, so that the power consumption can be reduced.

(Embodiment 9) FIG. 16 is a plan view of a unit pixel of a TFT active matrix formed by using the element of FIG. The sectional structure taken along the dotted line indicated by XX 'in FIG. 16 is similar to that shown in FIG. The active matrix is a scanning electrode 100 formed on a glass substrate.
And the signal electrode 120 formed so as to intersect with the
And the intrinsic aS formed near the intersection of these electrodes
A TFT composed of the i layer 30, the source electrode 11 and the base electrode 14 formed on the intrinsic a-Si layer 30.
And an intrinsic a-Si layer 30 and an n-type a-Si formed separately from the intrinsic a-Si layer 30 forming the TFT.
It is composed of the pattern of the layer 31 and the pixel electrode 13 connected to the source electrode 11 of the TFT.

As can be seen from FIGS. 1 and 17, the base electrode 14 includes a p-type a-Si layer 33 formed on the surface of the intrinsic a-Si layer 30 constituting the TFT, and an intrinsic type formed separately from the p-type a-Si layer 33. The pattern of the n-type a-Si layer 31 on the a-Si layer 30 is connected. N on the intrinsic a-Si layer 30
In the pattern of the mold a-Si layer 31, the base electrode 14 is formed.
One end of the connection electrode 15 which is formed separately from is connected and the other end is a through hole T formed in the gate insulating film 20.
It is connected to the scan electrode 100 via H.

Here, the n-type a-S on the intrinsic a-Si layer 30 in contact with the base electrode 14 and the connection electrode 15 is formed.
The pattern of the i layer 31 constitutes the base resistance rb in the equivalent circuit of FIG. The resistance value rb can be controlled by adjusting the gap between the base electrode 14 and the connection electrode 15. By thus connecting the base electrode 14 to the scan electrode 100 via a resistor, the scan electrode 100 can also serve as a base current feed, and it is not necessary to provide a new feed line, so that the pixel aperture ratio is reduced. Absent. In addition, since the base resistance is formed by using the semiconductor film that forms the TFT, a new step for forming the resistance is unnecessary and the manufacturing process can be simplified.

FIG. 18 shows an equivalent circuit of the whole display device constituted by using the unit pixel of FIG. XiG, Xi + 1
G, ... Are video signal electrodes connected to the pixels in which the green filters G are formed. Similarly, XiB, Xi + 1B, ...
Is a video signal electrode connected to a pixel in which a blue filter B is formed, XiR, Xi + 1R, ... Is a red filter R, and Yi, Yi + 1 ... is a pixel column X shown in FIG.
, X2, ..., Which are the scanning electrodes 100, and these scanning electrodes 100 are connected to the vertical scanning circuit V.
The video signal electrode is connected to the video signal starting circuit H.
The SUP is a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source and a circuit for converting the information for the cathode ray tube from the host (upper processing unit) into the information for the liquid crystal display panel. It is a circuit including. A plurality of display areas surrounded by a plurality of scanning electrodes and a plurality of video signal electrodes in the area on the insulating substrate are connected to the switching elements connected to the scanning electrodes and the video signal electrodes, and to the switching elements. A pixel electrode, a counter electrode arranged to face the pixel electrode, and a liquid crystal layer sandwiched between the pixel electrode and the counter electrode are provided.

The semiconductor element according to the present invention is used as the switching element in each display area. in this way,
By using the element of the present invention as the switching element in each display area, the output voltage of the vertical scanning circuit V can be reduced and the power consumption can be reduced.

(Embodiment 10) FIG. 19 is a plan view of a planar type TFT according to the present invention. 19A and 19B show an n-type TFT and a p-type TFT, respectively. Also,
19C is a sectional view taken along the line YY 'in FIG. 19A, and FIG. 19D is a sectional view taken along the line XX' in FIG. 19A. Is. 19 (a) and (b)
The cross-sectional views indicated by AA ', BB', and ZZ 'in FIG.

In this embodiment, as in the fifth embodiment, the intrinsic semiconductor layer 301 is formed as a convex plane pattern, and the pattern of the gate electrode 10 is arranged in the center thereof, and the source and drain are provided on both left and right sides thereof. N ⁺ layers 311 and 321
And a p ⁺ layer 331 serving as a base is formed on the upper protrusion of the convex intrinsic semiconductor layer 301. Also,
The high resistance layer rb, which is not doped with either p-type or n-type impurities, is formed in the portion from the intrinsic semiconductor layer 301 (channel) below the gate electrode to the p ⁺ layer 331. It is similar to the embodiment. In the present embodiment, an offset layer composed of the intrinsic semiconductor layer 301, roff, is formed between the n ⁺ layers 311 and 321 of the source and drain and the intrinsic semiconductor layer 301 (channel) immediately below the gate electrode 10. That is, the source and drain n ⁺ layers 31
1, 321 and the base p ⁺ layer 331 are the intrinsic semiconductor layer 30.
It has a structure separated by 1. In order to realize such a structure, in the present embodiment, the pattern of the gate insulating film 20 is made slightly larger than the gate electrode 10, and the pattern of the gate insulating film 20 is used as a mask for the source and drain. The n ⁺ layers 311 and 321 or the p ⁺ layer 331 serving as a base are formed.

Further, as a feature of this embodiment, FIG.
As shown in (c) and (d), the gate electrode 10 is extended to above the upper protrusion of the convex intrinsic semiconductor layer 301, but the p ⁺ layer 331 and the high resistance layer rb to be the base are formed. The area is a flat pattern in which the gate electrode 10 does not exist only in the region. Further, the p ⁺ layer 331 serving as a base and the gate electrode 10 extending to above the upper protrusion are connected by the base electrode 14. With this structure, the p ⁺ layer 331 and the gate electrode 10 are connected to each other.
Used as a terminal element. By adopting such a plane pattern, it is possible to connect the gate electrode 10 and the base electrode 14 while minimizing the increase in the area occupied by the element. Further, by removing the gate electrode 10 above the high resistance layer rb, the resistance value of the high resistance layer rb does not change due to the gate voltage, so that a stable base current limiting mechanism can be obtained. Further, not only the high resistance layer rb but also the offset layer roff functions to limit the base current, so that excessive base current injection can be further prevented and operation at low power up to a larger gate voltage becomes possible. Also,
Since the offset layer acts so as to relax the electric field between the source electrode 11 and the drain electrode 12, the generation of hot carriers is suppressed and the reliability of the device is improved. Figure 20
FIG. 19A is a plan view of a unit pixel of a TFT active matrix formed by using the semiconductor element shown in FIG. 20B is a sectional view taken along the line indicated by XX 'in FIG.

The active matrix is composed of the scanning electrode 100 formed on the glass substrate, the signal electrode 120 formed so as to intersect with the scanning electrode 100, the intrinsic semiconductor layer 301 formed near the intersection of these electrodes, and the intrinsic semiconductor. Layer 30
1 is composed of a TFT composed of a source electrode 11 and a base electrode 14 connected to each other through a through hole, and a pixel electrode 13 connected to the source electrode 11 of the TFT. As can be seen from FIG. 20B, the base electrode 14 connects the p ⁺ layer 331 shown in FIG. 19 and the gate electrode 10. Thus, the base electrode 14 and the scan electrode 10
By connecting 0, the scanning electrode 100 can also serve as the power supply of the base current, and it is not necessary to provide a new power supply line, so that the pixel aperture ratio does not decrease. In addition, since the base resistance is formed by using the semiconductor film that forms the TFT, a new step for forming the resistance is unnecessary and the manufacturing process can be simplified.

FIG. 21 shows C shown in FIGS. 12 and 13.
A drive circuit configured by using a MOS inverter is shown in FIG.
An equivalent circuit of the whole display device integrated on the same substrate with the TFT active matrix shown in FIG. An active matrix 50 comprising TFTs according to the present invention,
A vertical scanning circuit 51 for driving this, each horizontal scanning circuit 53 for dividing a video signal for one scanning line into a plurality of blocks and supplying them in a time division manner, data signal lines Vdr1, Vdg1 for supplying a video signal Data. , Vdb1, ..., A switch matrix circuit 52 for supplying a video signal to the active matrix side for each divided block. Here, the vertical scanning circuit 51 and the horizontal scanning circuit 53 are composed of shift registers and buffers as shown in FIG. 22, and are driven by clock signals CL1, Cl2 and CKV. FIG. 22
Is a scanning circuit corresponding to one scanning line. 7 in the figure
Reference numeral 0 represents a p-type transistor, and 71 represents an n-type transistor. Each transistor has a structure in which a base and a gate are connected by a resistor rb as shown in FIG. The shift register takes timing with a two-phase clock (Vcp1, Vcp2) and respective inversion clocks (Vcp1, Vcp2), inverts and shifts the input voltage, and transfers it to the buffer. at the same time,
This becomes the input voltage of the shift register corresponding to the next scanning line. The buffer outputs a pulse voltage of the maximum voltage Vdd2, which becomes the scanning voltage of the active matrix display section.

Complementary TF constructed using the device of the present invention
The T shift register operated at about half the power consumption of the conventional shift register composed of TFTs. Further, since the element of the present invention is used for the TFTs forming the active matrix, the output level of the scanning circuit, that is, Vdd2, can be reduced to 1/2 of the conventional level. As a result, the power consumption of the entire active matrix substrate is reduced to 1/3 that of the conventional one.
I was able to lower it to.

Further, in the above-mentioned example, the entire structure is formed by using the planar type TFT, but the TFT may be an inverted tag type or stagger type as shown in FIG. 1 or 2.
Particularly, in the planar type device, since the parasitic capacitance between the gate and the source or the drain can be reduced, higher speed operation is possible.

(Embodiment 11) FIGS. 23A to 23D.
FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the present invention shown in FIG. 1. A Cr film having a thickness of 100 nm is deposited on the glass substrate 1 by a sputtering method, and patterned into a predetermined plane shape by a well-known photolithography method to form a gate electrode 10. Then, a silicon nitride film (SiN film) 20 and an intrinsic a-S are formed on the entire surface of the substrate including the gate electrode 10.
Plasma CVD of the i layer 30 and the n-type a-Si layer 31
It is formed continuously by the method. Each film has 3 SiN films
50 nm, intrinsic a-Si film 200 nm, n-type a-Si
The film is 40 nm (see FIG. 23 (a)).

After patterning the intrinsic a-Si film and the n-type a-Si film into a predetermined plane shape, a photoresist PR having a predetermined plane shape is further formed on the n-type a-Si layer 31.
The n-type a-Si layer 31 is patterned into a predetermined shape by a plasma etching method using the photoresist as a mask (the n-type a-Si layer 31 is divided into two layers: the n-type a-Si layer 31 and the n-type a-Si layer 32). (Separate into parts) (Fig. 23
(See (b)).

Then, with the photoresist PR remaining, the entire surface of the substrate is irradiated with an ion beam IB containing boron to remove the intrinsic a- in the region where the n-type a-Si layer 31 is removed.
A p-type a-Si layer 33 is formed on the surface of the Si layer 30 (see FIG. 2).
3 (c)).

After removing the photoresist PR, Cr is formed to a thickness of 40 nm and Al is formed to a thickness of 400 nm by a sputtering method, and patterned into a predetermined shape to obtain a source electrode 11, a drain electrode 12 and a base electrode 14. Finally,
A SiN film to be the protective insulating film 22 is formed to a thickness of 400 nm by the plasma CVD method to complete the device (see FIG. 23D).

In this embodiment, the p-type a-Si layer 33 is formed in self-alignment with the pattern of the n-type a-Si layers 31 and 32. That is, the n-type a-Si layers 31, 32
Pattern is used as a mask to form the p-type a-Si layer 33.
Are formed. As a result, the n-type a-Si layers 31 and 32 and the p-type a-Si layer 33 are formed in one photolithography process.
Since both can be formed, the manufacturing process can be simplified and the manufacturing cost can be reduced.

(Embodiment 12) FIGS. 24 (a) to 24 (f).
FIG. 20 is a cross-sectional view showing a manufacturing process of the complementary (CMOS) semiconductor device according to the present invention shown in FIG. 19. In FIG. 24, A
The portions indicated by -A ', YY', BB 'and ZZ' are respectively AA ', YY' and B- in FIG.
It is a cross-sectional structure taken along each line B ', ZZ'.

An intrinsic a-Si layer 30 having a thickness of 50 nm is formed on the glass substrate 1 by the LPCVD method, and a high-brightness XeCl excimer laser beam LASER is emitted at an energy density of 330 m.
Irradiation with J / cm ² is performed to melt and recrystallize the intrinsic a-Si layer 30 to obtain an intrinsic semiconductor layer 301 (see FIG. 24A).

After patterning the n ⁺ layer 311 into a predetermined plane shape, a silicon dioxide (SiO ₂ ) film having a thickness of 100 nm is formed by a plasma CVD method, and Al having a thickness of 100 nm is formed by a sputtering method, and patterned into a predetermined plane shape. Gate insulating film 20 and gate electrode 10
(See FIG. 24B).

Next, a photoresist pattern P having a predetermined shape
After forming R1, the ion beam IP containing phosphorus is irradiated using the photoresist pattern PR1 and the pattern of the gate electrode 10 as a mask, and the n-type poly-Si layer 311 is formed.
Are formed (see FIG. 24C).

After removing the photoresist pattern PR1, another photoresist pattern PR2 is formed, and the ion beam I containing boron is formed using the photoresist pattern PR2 and the pattern of the gate electrode 10 as a mask.
B is irradiated to form the p ⁺ layer 331. After removing the photoresist pattern PR2, XeCl excimer laser light is irradiated again at an energy density of 200 mJ / cm ² ,
Activates the implanted phosphorus and boron, n-type poly-Si
The resistance of the layer 311 and the n ⁺ layer 321 is reduced (see FIG. 24).
(See (d)).

Next, plasma CV is used as the protective insulating film 22.
A SiO ₂ film having a thickness of 300 nm is formed by the D method and patterned into a predetermined shape (see FIG. 24E).

Finally, 40% of Cr was formed by the sputtering method.
nm and Al having a thickness of 400 nm and patterned into a predetermined shape to complete the element as the source electrode 11, the drain electrode 12 and the base electrode 14 (see FIG. 24F).

(Embodiment 13) FIG. 26 is a schematic sectional view of a liquid crystal display device according to the present invention. The scanning signal electrodes 10 and the video signal electrodes 120 are formed in a matrix on the lower glass substrate 1 with respect to the liquid crystal layer 506, and the pixel electrodes 13 made of ITO are formed through the TFTs formed in the vicinity of their intersections. To drive. The counter electrode 5 made of ITO is formed on the counter glass substrate 508 that faces the liquid crystal layer 506.
10, a color filter 507, a color filter protective film 511, and a light blocking film 512 forming a black matrix pattern for light blocking are formed. The central portion of FIG. 26 is a cross section of one pixel portion, and the left is a pair of glass substrates 1,
The left side edge portion of 508 shows a cross section of a portion where the external lead terminal exists, and the right side shows a cross section of a right edge portion of the pair of glass substrates 1 and 508 where there is no external lead terminal.

The sealing material SL shown on each of the left side and the right side of FIG. 26 is configured to seal the liquid crystal layer 506, and the edges of the glass substrates 1 and 508 excluding the liquid crystal sealing port (not shown). It is formed along the whole. The sealing agent is made of, for example, an epoxy resin. The counter electrode 510 on the counter glass substrate 508 side is connected to the external extraction wiring formed on the glass substrate 1 by the silver paste material SIL at at least one location. The external connection wiring is formed in the same manufacturing process as the scanning signal wiring 10, the source electrode 11, the video signal wiring 120, and the base electrode 14. Alignment film ORI1, ORI2, pixel electrode 1
3, the respective layers of the protective film 22 and the gate SiN film 20 are formed inside the sealing material SL. The polarizing plates 505 are formed on the outer surfaces of the pair of glass substrates 1 and 508, respectively.

The liquid crystal layer 506 is enclosed between the lower alignment film ORI1 and the upper alignment film ORI2 that set the orientation of the liquid crystal molecules, and is sealed by the seal material SL. The lower alignment film ORI1 is formed on the protective film 22 on the glass substrate 1 side. On the inner surface of the counter glass substrate 508,
Light-shielding film 512, color filter 507, color filter protective film 511, counter electrode 510 and upper alignment film O
RI2 is sequentially stacked. This liquid crystal display device is assembled by separately forming layers on the glass substrate 1 side and the counter glass substrate 508 side, then stacking the upper and lower glass substrates 1 and 508 and enclosing the liquid crystal 506 between them. A TFT driving type color liquid crystal display device is configured by adjusting the transmission of light from the backlight BL at the pixel electrode 13 portion.

By using the above-described semiconductor element of the present invention as a TFT for driving the pixel electrode 13, it becomes possible to operate the TFT at a low voltage, so that a liquid crystal display device with low power consumption can be realized. .

(Embodiment 14) FIG. 27 is a schematic sectional view of a reflective liquid crystal display device according to the present invention. Only a cross-sectional view of the pixel portion is shown. The scanning signal electrodes 10 and the video signal electrodes 120 are formed in a matrix on the lower glass substrate 1 based on the liquid crystal layer 506, and the pixel electrodes 130 are driven through the TFTs formed near the intersections thereof. In the present embodiment, the pixel electrode 130 is made of Al. A counter electrode 51 made of ITO is formed on a counter glass substrate 508 that faces the liquid crystal layer 506.
0, a color filter 507, a color filter protective film 511, and a light shielding film 512 forming a black matrix pattern for light shielding. Further, a phase plate 530 for changing the phase of light and a polarizing plate 505 are formed on the outer surfaces of the opposing glass substrates 1 and 508. The respective layers of the alignment films ORI1, ORI2, the pixel electrode 13, the protective film 22, and the gate SiN film 20 are formed inside a sealing material (not shown), and the liquid crystal layer 506 is a lower part for setting the orientation of liquid crystal molecules. Alignment film ORI1 and upper alignment film ORI2
It is sealed in between and is sealed by the sealing material. The lower alignment film ORI1 is formed on the protective film 22 on the glass substrate 1 side. On the inner surface of the counter glass substrate 508,
Light-shielding film 512, color filter 507, color filter protective film 511, counter electrode 510 and upper alignment film O
RI2 is sequentially stacked. This liquid crystal display device is assembled by separately forming layers on the glass substrate 1 side and the counter glass substrate 508 side, then stacking the upper and lower glass substrates 1 and 508 and enclosing the liquid crystal 506 between them.

Since this embodiment is a reflection type display device, the light source is light incident from the outside of the counter glass substrate 508, and this incident light is reflected by the pixel electrode 1 whose surface is a mirror surface.
Reflect at 30. By adjusting the intensity of the reflected light in the liquid crystal layer 506 portion, a TFT driving type reflective color liquid crystal display device is constructed. Since such a reflective display device does not require a backlight that consumes a lot of power, a liquid crystal display device with low power consumption can be realized, but a TFT that drives the pixel electrode 130 or a peripheral drive circuit is configured. By using the above-described semiconductor element of the present invention as the TFT, the power consumed by the active matrix substrate can be reduced, and thus a liquid crystal display device with extremely low power consumption can be realized. Such a display device
It is most desirable as an image display device for a portable information terminal device driven by a battery.

[0075]

As described above, according to the present invention, the threshold voltage of the field effect semiconductor device can be reduced. As a result, the operating voltage of the circuit or the active matrix can be reduced, and the power consumption of the display device can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device showing a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view for explaining the operation principle of the semiconductor device shown in FIG.

FIG. 3 is an energy band diagram for explaining the operation principle of the semiconductor device shown in FIG.

FIG. 4 is a transfer characteristic of the semiconductor device shown in FIG.

FIG. 5 is a sectional view of a semiconductor device showing a second embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor device showing a third embodiment of the present invention.

FIG. 7 is a semiconductor element equivalent circuit diagram showing a fourth embodiment of the present invention.

FIG. 8 is a plan view of a semiconductor device showing a fifth embodiment of the present invention.

9 is a cross-sectional view taken along the line XX 'of the TFT shown in FIG.

FIG. 10 is a plan view of a semiconductor device showing a sixth embodiment of the present invention.

11 is a cross-sectional view taken along the line XA of the TFT shown in FIG.

FIG. 12 is a circuit diagram of a complementary inverter showing a seventh embodiment of the present invention.

13 is a plan view of the complementary inverter shown in FIG.

FIG. 14 is a cross-sectional view of a complementary inverter showing an eighth embodiment of the present invention.

15 is a plan view of the complementary inverter shown in FIG.

FIG. 16 is a plan view of a unit pixel of a liquid crystal display device showing a ninth embodiment of the present invention.

17 is a cross-sectional view taken along line YY ′ of the liquid crystal display device shown in FIG.

FIG. 18 is an equivalent configuration diagram showing an overall configuration of a liquid crystal display device to which the present invention is applied.

FIG. 19 is a plan view and a sectional view of a semiconductor device showing a tenth embodiment of the present invention.

20A and 20B are a plan view and a cross-sectional view of a unit pixel of a liquid crystal display device configured by using the semiconductor element shown in FIG.

21 is an equivalent configuration diagram of an entire liquid crystal display device with a built-in drive circuit, which is configured by using the semiconductor element shown in FIG.

22 is a circuit configuration diagram of a shift register and a buffer used in the liquid crystal display device with a built-in drive circuit shown in FIG. 21.

FIG. 23 is a cross-sectional view showing the manufacturing process of the semiconductor element according to the eleventh embodiment of the present invention.

FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device of the twelfth embodiment of the invention.

25 is a current-voltage characteristic of the semiconductor device shown in FIG.

FIG. 26 is a sectional view of a liquid crystal cell of a liquid crystal display device according to a thirteenth embodiment of the present invention.

FIG. 27 is a sectional view of a liquid crystal cell of a liquid crystal display device according to a fourteenth embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Glass substrate, 10 ... Gate electrode, 11 ... Source electrode, 12 ... Drain electrode, 13 ... Pixel electrode, 14 ... Base electrode, 15 ... Connection electrode, 20 Gate insulating film, 21 ... Second protective insulating film, 22 ... Protective insulating film, 30 ... Intrinsic aS
i layer, 31, 32 ... n-type a-Si layer, 33 ... p-type a-S
i layer, 50 ... TFT active matrix, 51 ... Vertical scanning circuit, 53 ... Horizontal scanning circuit, 70 ... P-type TFT,
71 ... N-type TFT, 100 ... Scan electrode, 201 ... Gate insulating film, 301 ... Intrinsic semiconductor layer, 311, 321 ... N ⁺
Layers, 331 ... P ⁺ layers, rb ... Base resistance, TH ... Through holes, V ... Vertical scanning circuit, H ... Video signal starting circuit, S
UP ... Power supply circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-7-106581 (JP, A) JP-A-63-208896 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G02F 1/1368 H01L 29/786

Claims (23)

(57) [Claims] 1. A pair of substrates of at least one of which is transparent, the
A liquid crystal display device having a liquid crystal layer between a pair of substrates, said one of the pair of substrates a plurality of semiconductor elements arranged in a matrix are formed, the plurality of semiconductor elements, the 1. First, second, third and fourth electrodes, a pair of one conductive type semiconductor layers connected to the second and third electrodes and separated from each other, and connected to the pair of one conductive type semiconductor layers an intrinsic semiconductor layer, wherein
Is separated from a pair of one conductivity type semiconductor layers, and
Conductive semiconductor layer connected to the other conductive semiconductor layer.
However, the first electrode is close to the intrinsic semiconductor layer via an insulating film.
The fourth electrode is formed so as to be in contact with the other conductive type semiconductor layer.
And the first electrode and the fourth electrode are formed by wiring or a resistor element.
Liquid crystal display device characterized by being connected through a child
Place 2. The liquid crystal display device according to claim 1, wherein the pair of one conductivity type semiconductor layer and the other conductivity type semiconductor layer are separated from each other by the intrinsic semiconductor layer. 3. The region of the intrinsic semiconductor layer as viewed from the vertical direction of the substrate according to claim 2, extending at least in the direction of the pair of one-conductivity-type semiconductor layers from the region of the insulating layer. Liquid crystal display device characterized by. 4. The liquid crystal display device according to claim 1, wherein the first electrode and the fourth electrode are connected via a resistor. 5. The intrinsic semiconductor layer, the one-conductivity-type semiconductor layer, and the other-conductivity-type semiconductor layer are formed of a semiconductor thin film made of any one of silicon, silicon germanium, and silicon carbide. A liquid crystal display device characterized by the above. 6. The liquid crystal display device according to claim 1, wherein the intrinsic semiconductor layer, the semiconductor layer of one conductivity type and the semiconductor layer of the other conductivity type are composed of a polycrystalline silicon film. 7. The liquid crystal display device according to claim 1, wherein the semiconductor layers of one conductivity type and the other conductivity type are an n-type semiconductor layer and a p-type semiconductor layer, respectively. 8. The liquid crystal display device according to claim 1, wherein a current carrier is injected into the intrinsic semiconductor layer from the fourth electrode through the semiconductor layer of the other conductivity type. 9. The first, second, and third elements according to claim 1,
And the fourth electrode is a gate, source, drain and base electrode, respectively, in a liquid crystal display device. 10. The liquid crystal display device according to claim 1, wherein the first and second semiconductor elements are any one of a planar type, an inverted stagger type, and a positive stagger type. 11. The method according to claim 10, wherein the first electrode is formed on the one substrate, the insulating layer is formed on the first electrode, and the intrinsic semiconductor layer is formed on the insulating film. And a pair of one-conductivity-type semiconductor layers are formed on the intrinsic semiconductor layer. 12. The liquid crystal display device according to claim 10, wherein the second electrode, the third electrode, and the fourth electrode are formed on the one substrate. 13. A pair of substrates, at least one of which is transparent,
A liquid crystal display device having a liquid crystal layer sandwiched between the substrates, wherein one of the pair of substrates has a display region and a drive circuit region for driving the display region, A plurality of semiconductor elements arranged in a matrix are formed in the drive circuit area, a plurality of complementary n-type and p-type semiconductor elements forming a shift register are formed in the drive circuit area, and are formed in the drive circuit area. And a pair of n-type conductive semiconductor layers connected to the second and third electrodes and separated from each other, The semiconductor device has an intrinsic semiconductor layer connected to the pair of n-type conductive semiconductor layers and a p-type conductive semiconductor layer formed on the intrinsic semiconductor layer, and the first electrode is the intrinsic semiconductor layer. The fourth electrode formed on the insulating film via an insulating film. Is formed on the p-type conductive semiconductor layer formed on the intrinsic semiconductor layer, and the first electrode and the fourth electrode are formed .
The electrodes are connected via wiring or resistance elements, and the p-type semiconductor element formed in the drive circuit region includes the first, second, third and fourth electrodes and the second and third electrodes. A pair of p-type conductive semiconductor layers that are connected to the electrodes and are separated from each other, an intrinsic semiconductor layer connected to the pair of p-type conductive semiconductor layers, and an n-type formed on the intrinsic semiconductor layer. A conductive semiconductor layer, the first electrode is formed on the intrinsic semiconductor layer via an insulating film, and the fourth electrode is an n-type conductive layer formed on the intrinsic semiconductor layer. A first electrode and a fourth electrode formed on the semiconductor layer;
A liquid crystal display device in which electrodes are connected via wiring or a resistance element . 14. The liquid crystal display device according to claim 13, wherein the semiconductor element formed in the display region is an n-type semiconductor element. 15. The n-type semiconductor element formed in the display region according to claim 14, being connected to the first, second, third and fourth electrodes and the second and third electrodes. A pair of n-type conductive semiconductor layers separated from each other, an intrinsic semiconductor layer connected to the pair of n-type conductive semiconductor layers,
A p-type conductive semiconductor layer formed on the intrinsic semiconductor layer, the first electrode is formed on the intrinsic semiconductor layer via an insulating film, and the fourth electrode is the intrinsic semiconductor. A liquid crystal display device, which is formed on a p-type conductive semiconductor layer formed on the layer. 16. The liquid crystal display device according to claim 13, wherein the semiconductor element formed in the display region and the drive circuit region is any one of a planar type, an inverted stagger type, and a positive stagger type. 17. The intrinsic semiconductor layer of a semiconductor device according to claim 13, which is formed in the display region and the drive circuit region,
A liquid crystal display device, wherein the n-type conductive semiconductor layer and the n-type conductive semiconductor layer are composed of a polycrystalline silicon film. 18. The liquid crystal display device according to claim 13, wherein the pair of n-type conductive semiconductor layers and the p-type conductive semiconductor layers are separated from each other by the intrinsic semiconductor layer. 19. The region of the intrinsic semiconductor layer as viewed in the vertical direction of the substrate extends from the region of the insulating layer in at least the direction of the pair of n-type conductive semiconductor layers. A liquid crystal display device characterized by the above. 20. The liquid crystal display device according to claim 13, wherein the first electrode and the fourth electrode are connected through a resistor. 21. A pair of substrates, at least one of which is transparent,
A liquid crystal display device having a liquid crystal layer sandwiched between the substrates, wherein one of the pair of substrates has a display region and a drive circuit region for driving the display region, A plurality of scanning signal electrodes, a plurality of video signal electrodes intersecting these in a matrix, and a plurality of n-type semiconductor elements formed corresponding to the intersections of the plurality of scanning signal electrodes and the video signal electrodes, A plurality of pixel electrodes connected to each semiconductor element are formed, and a plurality of complementary n-type and p-type semiconductor elements forming a vertical scanning circuit and a video signal driving circuit are formed in the driving circuit region. The n-type semiconductor element formed in the display region or the drive circuit region has first, second, third and fourth electrodes, and n-type conductivity connected to the second and third electrodes. Semiconductor layers and these n-type conductivity An intrinsic semiconductor layer connected to the semiconductor layer and a p-type conductive semiconductor layer formed on the intrinsic semiconductor layer, wherein the first electrode is provided on the intrinsic semiconductor layer via an insulating film. The fourth electrode is formed, is connected to the p-type semiconductor layer formed on the intrinsic semiconductor layer, and the p-type semiconductor element formed in the drive circuit region is the first, second, third And a fourth electrode, a p-type conductive semiconductor layer connected to the second and third electrodes, an intrinsic semiconductor layer connected to these p-type conductive semiconductor layers, and on this intrinsic semiconductor layer And an n-type semiconductor layer formed on the intrinsic semiconductor layer, the first electrode is formed on the intrinsic semiconductor layer via an insulating film, and the fourth electrode is formed on the intrinsic semiconductor layer. A first conductive electrode connected to the scanning signal electrode, The liquid crystal display device and the second electrode is connected to the video signal electrode, the fourth electrode, characterized in that connected to the first electrode through a resistor. 22. The liquid crystal display device according to claim 21, wherein the pair of n-type conductive semiconductor layers and the p-type conductive semiconductor layers are separated from each other by the intrinsic semiconductor layer. 23. The region of the intrinsic semiconductor layer as viewed in the vertical direction of the substrate extends from the region of the insulating layer in at least the direction of the pair of n-type conductive semiconductor layers. A liquid crystal display device characterized by the above.