JP2002299633A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce in size of an element by decreasing a forming space of a threshold voltage control contact for connecting a gate electrode of a DT- MOSFET to a channel forming region. SOLUTION: A field effect transistor comprises a gate electrode extended part 116A formed at one end of a gate electrode 116 in a channel width direction. The transistor further comprises a channel region extended part 112A largely extended from the extended part 116A to one end of a channel forming region 112 in a channel width direction. The transistor also comprises contact holes 117A formed at positions corresponding to the extended part 116A and the extended part 112A on an interlayer insulating layer 117, and a contact hole 117 for controlling a threshold voltage in the hole 117A. Accordingly, the electrode 116 is electrically connected to the region 112 via one contact 118 for controlling the threshold voltage. Thus, a space for forming for the hole 117A or the contact 118 can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is configured as a DT-MOSFET in which a gate electrode and a channel forming region are connected via a threshold voltage control contact and a threshold voltage control wiring so that the threshold voltage can be controlled. Field-effect transistor.

[0002]

2. Description of the Related Art Field effect transistors (FETs) conventionally mounted on various semiconductor circuit devices.
ransistor), which electrically connects the gate electrode and the channel forming region to enable dynamic control of the threshold voltage.
T-MOSFET (Dynamic Threshold Voltage Metal
Oxide Semiconductor FET) has been proposed. This DT-MOSFET can lower the threshold voltage during the operation in which the drain current flows, and can increase the threshold voltage in the non-operation when the drain current does not flow. Therefore, the DT-MOSFET operates at a high speed during the operation, and the leakage current during the non-operation. Can be suppressed. Therefore, lower power consumption and higher speed of the semiconductor circuit device can be achieved. Note that this D
For the T-MOSFET, see, for example, IEDM94, pp. 809 to 812, "A Dynamic Threshold Voltag".
e MOSFET (DTMOS) for Ultra-LowVoltage Operation ''
It is described in.

FIG. 3 is a plan view showing the structure of a conventional DT-MOSFET, and FIG. 4 is a sectional view taken along line BB of FIG. This DT-MOSFET is based on SOI (Silicon On
Insulator) structure of the main surface of the semiconductor substrate 10, ie,
A source region 13 and a drain region 14 are provided on a semiconductor layer 10A made of single-crystal silicon provided on the insulating layer 11 with a channel forming region (body) 12 interposed therebetween to form an active region (element forming region). A gate electrode 16 is formed on a channel forming region 12 with a gate insulating film 15 interposed therebetween. Also, such a DT-MOSF
An interlayer insulating film 17 is provided on the upper layer of the ET, and various wirings are provided on the interlayer insulating film 17.

The gate electrode 16 has a gate electrode extension 16A extending from the active region to the non-active region at one end in the channel width direction.
A contact hole 17A is formed in a region corresponding to the gate electrode extension 16A.
Is provided with a threshold voltage control contact 18A. On the other hand, the channel formation region 12 is a channel region extension 12A in which one end in the channel width direction extends from the active region to the inactive region side. The channel region extending portion 12A extends outward more greatly than the gate electrode extending portion 16A, and a contact hole 17B is formed in the interlayer insulating film 17 in a region corresponding to the channel region extending portion 12A. The contact hole 17A is provided with a threshold voltage control contact 18B. And
The threshold voltage control contacts 18A and 18B of the gate electrode 16 and the channel formation region 12 are connected to a common threshold voltage control wiring 19 on the interlayer insulating film 17.

[0005]

However, in the above-mentioned conventional DT-MOSFET, threshold voltage control contacts 18A and 18B for electrically connecting the gate electrode 16 and the channel forming region 12 are separately provided, and these are provided. Since the connection is made by the common threshold voltage control wiring 19 on the interlayer insulating film 17, the space for forming the contact holes 17A and 17B and the threshold voltage control contacts 18A and 18B is increased, and one space on the semiconductor substrate is formed. There is a problem that the area occupied by the FET increases and the degree of integration of the semiconductor device decreases.

The present invention has been made in view of the above circumstances, and has as its object to provide a contact hole and a threshold voltage control necessary for electrically connecting a gate electrode and a channel formation region. It is an object of the present invention to provide a field effect transistor capable of reducing a space for forming a contact for use, reducing an area occupied by each element on a semiconductor substrate, and improving the degree of integration of a semiconductor device.

[0007]

According to the present invention, an active region is formed by providing a source region and a drain region on a semiconductor substrate with a channel forming region interposed therebetween, and a gate insulating film is formed on the channel forming region of the semiconductor substrate. A field effect transistor having a gate electrode formed therethrough, a gate electrode extending portion formed by extending one end of the gate electrode in the channel width direction toward the inactive region side; A channel region extending portion formed by extending one end in the channel width direction to the inactive region side larger than the gate extending portion; and an interlayer insulating film formed on an upper layer of the semiconductor substrate. A contact hole opened to expose an upper surface of the channel region extension portion and an edge of the gate electrode extension portion, and the channel provided in the contact hole; A threshold voltage control contact commonly connected to the region extension portion and the gate electrode extension portion; and a threshold voltage control wiring formed on the interlayer insulating film and connected to the common contact. Features.

According to the field effect transistor of the present invention, since the gate electrode and the channel forming region are electrically connected by one threshold voltage controlling contact, separate threshold voltage controlling devices are provided for the gate electrode and the channel forming region. Compared with the case where the contact is provided, the space for forming the contact hole and the contact for controlling the threshold voltage can be reduced. Therefore, the area occupied by each element on the semiconductor substrate can be reduced, and the degree of integration of the semiconductor device can be improved.
In particular, in the present invention, since a contact hole can be formed by drilling one kind of interlayer insulating film by etching or the like, the drilling work is easier than in the case of drilling a plurality of layers of different film types, There is an advantage that a highly reliable contact can be formed and can be realized without complicating the manufacturing operation.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings. The embodiments described below are preferred specific examples of the present invention, and various technically preferable limitations are added. However, the scope of the present invention is not limited to the embodiments described below. The embodiments are not limited to these embodiments unless otherwise specified.

FIG. 1 is a plan view showing a structure of a DT-MOSFET which is a field-effect transistor according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA of FIG. The DT-MOSFET of this example has a source region with a channel formation region (body) 112 interposed between a main surface of a semiconductor substrate 110 having an SOI structure, that is, a semiconductor layer 110A made of single crystal silicon provided over an insulating layer 111. 11
3 and a drain region 114 to form an active region (element forming region), a gate electrode 116 is formed on the channel forming region 112 via a gate insulating film 115, and a silicon oxide film (SiO2) is further formed thereon. And the like are provided. Gate electrode 116
Is formed with sidewalls 116B at both ends in the channel width direction, and one end in the channel width direction is
A gate electrode extension 116A extends from the active region to the non-active region. This gate electrode extension 116
A is formed wider in the channel length direction than other portions of the gate electrode 116, and the gate electrode 116 is formed in a T-shaped pattern as a whole.

On the other hand, one end of the channel formation region 112 in the channel width direction extends from the active region to the inactive region side, and the gate electrode extension portion 116A of the gate electrode 116 is formed.
The channel region extension portion 112A is extended to a larger extent. The amount of extension of the channel region extending portion 112A is set to such an extent that an electrically sufficient connection state with a contact 118 described later can be obtained. The channel region extending portion 112A is formed wider in the channel length direction than other portions of the channel forming region 112, and the channel forming region 112 is formed in a T-shaped pattern as a whole. Further, the other end of the channel formation region 112 in the channel width direction is located inside the other end of the gate electrode 116. Further, the channel forming region 112 is surrounded by a silicon oxide film (SiO2) 120.

In the interlayer insulating layer 117, a contact hole 117A is formed at a position corresponding to the gate electrode extension 116A of the gate electrode 116 and the channel region extension 112A of the channel formation region 112. Is provided with a threshold voltage control contact 118. That is, the contact hole 117A is a square hole formed by forming a hole in the interlayer insulating layer 117 by etching. This contact hole 11
7A is formed in such a manner that the upper surface of the channel region extension portion 112A and the portion including the sidewall 116B of the gate electrode extension portion 116A are exposed, and the threshold voltage control contact 118, the gate electrode extension portion 116A and the channel region are formed. The extension portion 112A is formed in such a size that an electrically sufficient connection state can be obtained.

The contact hole 117A has:
For example, a threshold voltage control contact 118 made of tungsten or the like is provided. Therefore, the threshold voltage control contact 118 is in contact with the upper surface of the channel region extension portion 112A and also in contact with the portion including the sidewall 116B of the gate electrode extension portion 116A, and both are in a conductive state. On the upper surface of the interlayer insulating layer 117, a threshold voltage control wiring 119 made of aluminum wiring or the like is provided, and is connected to the threshold voltage control contact 118. Therefore, this threshold voltage control wiring 1
The threshold voltage is dynamically controlled by controlling the applied voltage to the gate electrode 116 and the channel formation region 112 via the contact 19 and the threshold voltage control contact 118. Although not shown in the figure, contact holes are respectively formed in the interlayer insulating layer 117 corresponding to the gate electrode 116, the source region 113, and the drain region 114, and a contact is provided in each contact hole. It is assumed that the wiring connected to the contact is provided on the interlayer insulating layer 117.

As described above, in this embodiment, since the gate electrode 116 and the channel formation region 112 are electrically connected by one threshold voltage control contact 118, the gate electrode 116 and the channel formation region 112 are separated from each other. As compared with the case where the threshold voltage control contact is provided, the space for forming the contact hole 117A and the threshold voltage control contact 118 can be reduced. Therefore, the area occupied by each element on the semiconductor substrate can be reduced, and the degree of integration of the semiconductor device can be improved.

[0015] In a configuration in which the gate electrode and the channel forming region are connected by one threshold voltage control contact, the contact is formed in such a manner that the contact reaches the channel forming region through the interlayer insulating film, the gate electrode, and the gate insulating film. It is also possible to open a hole and provide a contact in this contact hole. However, in such a method, when a contact hole is formed by etching, it is necessary to form a hole through an interlayer insulating film, a gate electrode, and a gate insulating film of different film types. In the formation, it is complicated to set etching conditions and the like. In this regard, in this embodiment, since a contact hole can be formed by drilling one kind of interlayer insulating film by etching, setting of etching conditions is simple, drilling work is easy, and high reliability is achieved. There is an advantage that the contact can be formed and the contact can be realized without complicating the manufacturing operation.

[0016]

As described above, according to the field-effect transistor of the present invention, the gate electrode and the channel formation region are electrically connected by one threshold voltage control contact. In comparison with the case where separate threshold voltage control contacts are provided, the space for forming contact holes and threshold voltage control contacts can be reduced, the area occupied by each element on a semiconductor substrate can be reduced, and the integration degree of a semiconductor device can be reduced. Can be improved. In particular, in the present invention, since a contact hole can be formed by drilling one kind of interlayer insulating film by etching or the like, the drilling work is easier than in the case of drilling a plurality of layers of different film types, There is an advantage that a highly reliable contact can be formed and can be realized without complicating the manufacturing operation.

[Brief description of the drawings]

FIG. 1 is a plan view showing a structure of a DT-MOSFET which is a field-effect transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a plan view showing a structure of a conventional DT-MOSFET.

FIG. 4 is a sectional view taken along line BB of FIG. 3;

[Explanation of symbols]

110 ... Semiconductor substrate, 110A ... Semiconductor layer, 111
... insulating layer, 112 ... channel formation region, 112A ...
... channel region extending portion, 113 ... source region, 114
...... drain region 115 gate insulating film 116
... Gate electrode, 116A ... Gate electrode extension, 116
B: sidewall 117, interlayer insulating layer 117
A: contact hole, 118: contact for controlling the threshold voltage, 119: wiring for controlling the threshold voltage.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/90 B F term (Reference) 5F033 HH08 JJ19 KK01 KK04 NN12 NN39 TT08 5F110 AA04 AA08 AA15 AA16 BB20 CC10 DD05 DD22 DD24 EE24 EE31 EE38 GG02 GG12 GG23 GG60 HL03 HL04 HL11 HM17 NN02 NN23 NN62

Claims (5)

[Claims] An electric field in which a source region and a drain region are provided on a semiconductor substrate with a channel formation region interposed therebetween to form an active region, and a gate electrode is formed on the channel formation region of the semiconductor substrate via a gate insulating film. In the effect-type transistor, a gate electrode extension portion formed by extending one end of the gate electrode in the channel width direction toward the inactive region side; and one end of the channel formation region in the channel width direction. A channel region extension portion formed by extending to the inactive region side larger than the gate extension portion; and an interlayer insulating film formed on an upper layer of the semiconductor substrate; A contact hole opened so as to expose an upper surface and an edge of the gate electrode extending portion; and a contact hole provided in the contact hole, the channel region extending portion and the gate. A threshold voltage control contact commonly connected to the gate electrode extension portion; and a threshold voltage control wiring formed on the interlayer insulating film and connected to the common contact. Type transistor. 2. The method according to claim 2, wherein the interlayer insulating film includes a gate electrode,
A contact hole is formed corresponding to each of a source region and a drain region, a contact is provided in each contact hole, and a wiring connected to each contact is provided on an interlayer insulating film. 2. The field effect transistor according to 1. 3. The field effect transistor according to claim 1, wherein the gate electrode has a gate electrode extending portion formed to be wider in a channel length direction than other portions. 4. The field effect transistor according to claim 1, wherein the channel forming region has a channel region extending portion formed wider in a channel length direction than other portions. 5. The gate electrode extension portion has a sidewall, and the contact hole is formed in a state where the sidewall is exposed.
The field-effect transistor according to the above.