JPH0385529A - Thin film semiconductor display device - Google Patents
Thin film semiconductor display deviceInfo
- Publication number
- JPH0385529A JPH0385529A JP1221495A JP22149589A JPH0385529A JP H0385529 A JPH0385529 A JP H0385529A JP 1221495 A JP1221495 A JP 1221495A JP 22149589 A JP22149589 A JP 22149589A JP H0385529 A JPH0385529 A JP H0385529A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- display device
- peripheral circuit
- tpt
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 239000010408 film Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 8
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 230000014759 maintenance of location Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は薄膜半導体装置に係り、特に液晶などを用いた
薄膜半導体表示装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film semiconductor device, and particularly to a thin film semiconductor display device using liquid crystal or the like.
液晶を用いた平面デイスプレィは、近年、画面サイズの
大型化と、画素駆動用回路のデイスプレィ基板への内蔵
という2つの流れで進んでいる。In recent years, flat displays using liquid crystals have been progressing in two ways: increasing screen size and incorporating pixel drive circuits into display substrates.
画面サイズの大型化に関しては、アモルファスシリコン
(a−8i)による逆スタガー構造のTPTを用いて、
対角14インチのデイスプレィが実現している、この構
造のTPTはリーク電流が小さいために、液晶に電界を
印加するための電荷の保持特性がよく、画面サイズの大
型化が達威しやすい。しかしキャリア移動度が約0 、
34 / V s と小さいため、電流駆動能力が小
さく、このTPTで回路を組立てることは難しい、上記
技術に関連するものとして特開昭55−83025号が
ある。一方。In order to increase the screen size, we use TPT with an inverted staggered structure made of amorphous silicon (a-8i).
The TPT with this structure, which is used to realize a 14-inch diagonal display, has a small leakage current and has good charge retention characteristics for applying an electric field to the liquid crystal, making it easy to increase the screen size. However, the carrier mobility is about 0,
34/Vs, the current drive capability is small, and it is difficult to assemble a circuit using this TPT. Japanese Patent Application Laid-Open No. 83025/1983 is related to the above technology. on the other hand.
周辺駆動回路の内蔵に関しては、多結晶シリコン(p−
8i)によるコープレーナ型のTPTが用いられる。こ
の構造のTPTはキャリア移動度が約30ci/V8以
上あり、電流駆動能力が大きく、回路を構成して画素廓
動用の周辺回路をデイスプレィ基板上に内蔵することが
可能である。このため、デイスプレィからの端子取出し
数を低減できると共に、外付けLSI分のコストを低減
できる。Regarding the built-in peripheral drive circuit, polycrystalline silicon (p-
8i) is used. A TPT with this structure has a carrier mobility of about 30 ci/V8 or more, a large current driving ability, and can form a circuit to incorporate a peripheral circuit for pixel movement on the display substrate. Therefore, the number of terminals taken out from the display can be reduced, and the cost for the external LSI can be reduced.
しかしながら、p−8iを用いたコープレーナ構造のT
PTはリーク電流が大であるために、電荷の保持能力が
十分でなく1画面が大型化しにくいという欠点がある。However, T of the coplanar structure using p-8i
Since PT has a large leakage current, it does not have sufficient charge retention ability and has the disadvantage that it is difficult to increase the size of one screen.
上記従来技術は、プロセスを複雑にしないという観点か
ら、TPT構造は同一種類のものを用いるものであり、
デイスプレィの大画面化と周辺回路の内蔵という2つの
流れに対応することが難しく、大画面デイスプレィには
周辺回路が内蔵できないという問題があった。The above conventional technology uses the same type of TPT structure from the viewpoint of not complicating the process,
It is difficult to keep up with the two trends of larger displays and built-in peripheral circuits, and there has been a problem in that large-screen displays cannot incorporate peripheral circuits.
本発明の目的は、液晶デイスプレィの大画面化と周辺回
路のデイスプレィ基板への内蔵を同時に可能にする構造
を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a structure that allows a liquid crystal display to have a larger screen and to incorporate peripheral circuits into the display substrate at the same time.
上記目的を達成するために、本発明はデイスプレィの画
素部分はスタガー構造のTFTか金属−絶縁物−金属(
MIM)構造のスイッチング素子で構成し、周辺回路部
分はコープレーナ構造のTPTで構成するようにしたも
のである。In order to achieve the above object, the present invention provides that the pixel portion of the display is made of staggered TFT or metal-insulator-metal (metal-insulator-metal).
The device is constructed of switching elements having an MIM) structure, and the peripheral circuit portion is constructed of TPTs having a coplanar structure.
本発明は以下のように作用する。第1図(b)に示すよ
うに、スタガー構造のTPTは、一般に。The invention works as follows. As shown in FIG. 1(b), the TPT has a staggered structure.
チャネル領域とソース及びドレイン領域が高抵抗の膜自
身で膜の厚さ方向に隔てられているため、一般に、電流
値が小さく、このTPTを第1図(a)に示すデイスプ
レィの画素部分に用いれば、約3 X 10”A以下と
いうリーク電流の仕様を十分溝たすため電荷の保持能力
が大きく、デイスプレィの大型化が可能である。逆スタ
ガー構造のTPTは約0,3cm2/Vs という小
さなキャリア移動度しか有しないが画素部分のTPTの
キャリア移動度の仕様的0 、2 cm2 / V s
以上を満たしている。デイスプレィの大型化にはリ
ーク電流(it流像保持能力が重要であるため、このキ
ャリア移動度の小さい点は問題とはならない、一方、第
1図(c)に示すように、コープレーナ構造のTPTは
チャネルとソース及びドレインが一平面上に接している
構造のために、キャリア移動度が約40d/Vsと大き
く、約30cm2/Vs以上というキャリア移動度の仕
様を満たすため電流駆動能力も大きくとれ、第1図(a
)に示す画素駆動用回路をこのTPTで構成してデイス
プレィ基板上に内蔵することが可能である。コープレー
ナ構造のTPTは約10−”A という大きなリーク
電流を有するが、周辺回路のTPTのリーク電流の仕様
約2X10−11A以下を満たしている0画素駆動用の
回路を構成するには大きな電流駆動能力が重要であるた
めに、このリーク電流が大きい点は問題とはならない。Since the channel region and the source and drain regions are separated in the thickness direction of the film by the high-resistance film itself, the current value is generally small, and this TPT is used in the pixel part of the display shown in Figure 1(a). For example, it has a large charge retention capacity that satisfies the leakage current specification of approximately 3 x 10" A or less, allowing for larger displays. TPT with an inverted stagger structure has a small current of approximately 0.3 cm2/Vs. Although it only has carrier mobility, the carrier mobility of TPT in the pixel part is 0.2 cm2/V s
The above requirements are met. This low carrier mobility is not a problem because the leakage current image retention ability is important for increasing the size of the display.On the other hand, as shown in Figure 1(c), TPT with a coplanar structure Because of the structure in which the channel, source, and drain are in contact with each other on one plane, the carrier mobility is as high as approximately 40 d/Vs, and the current drive capability is also large in order to meet the carrier mobility specification of approximately 30 cm2/Vs or more. , Figure 1 (a
) It is possible to configure the pixel driving circuit shown in FIG. A TPT with a coplanar structure has a large leakage current of about 10-"A, but the current drive is too large to configure a zero pixel drive circuit that satisfies the TPT leakage current specification of about 2X10-11A or less in the peripheral circuit. Since performance is important, this large leakage current is not a problem.
第2図に示すように、金属−絶縁物−金属(MIM)構
造のスイッチング素子は金属−金属間に高電界が印加さ
れたときのみ電流が流れるものであり、オフ電流は小さ
い、従って、スタガー構造TPTと同様に、大画面デイ
スプレィの画素部を構成することが可能であり、周辺回
路部を第3図に示すようなコープレーナ構造のTPTで
構成すれば、周辺回路内蔵の大型デイスプレィが実現で
きる。As shown in Figure 2, a switching element with a metal-insulator-metal (MIM) structure allows current to flow only when a high electric field is applied between metals, and the off-state current is small. Similar to structural TPT, it is possible to configure the pixel section of a large screen display, and if the peripheral circuit section is configured with a TPT with a coplanar structure as shown in Figure 3, a large display with built-in peripheral circuits can be realized. .
以下、本発明の一実施例を第1図を用いて説明する。対
角300−のガラス基板1上にCr2を蒸着して、ホト
工程により画素部逆スタガー構造TPTの電極及び配線
用パターニングを行う。その後、プラズマCVD法によ
り窒化膜3とa −Si膜(i層)4を形成する。a
−s isをホト工程により島切りした後、周辺回路部
分のみ波長3.8mmのエキシマレーザを用いてアニー
ルし、多結晶化する。その後、プラズマCVD法により
a −S i膜(n中層)5,6を形成する。ホト工程
により、ソース及びドレイン領域を形成後、酸化膜7を
常圧CVD法により形成する。ホト工程により周辺回路
部コープレーナ構造TPTのゲート絶縁膜用パターニン
グを行う。次に、信号配線用Cr8を蒸着した後、ホト
工程でパターニングする。次に、主として周辺回路部T
PT配線用のAg3を蒸着した後、ホト工程でパターニ
ングする0次に、透明電極であるITOIOを蒸着しホ
ト工程でパターニングする。最後に、カラーフィルタと
偏光板を備えた他のガラス基板との間に液晶を封入して
デイスプレィが完成する0本デイスプレィは表示部の対
角が10インチであり、走査線、信号線数共に1200
本である。また、周辺回路部はマルチプレクサ、インバ
ータ、レベルシック、マトリクススイッチが構成されて
いる。第1図(a)はこのようにして得られたデイスプ
レィ基板を示す、ここでは1画素部分16の他に周辺回
路である走査回路17と信号回路18がlっの基板上に
構成されている様子がわかる。An embodiment of the present invention will be described below with reference to FIG. Cr2 is vapor-deposited on the glass substrate 1 on the diagonal 300-, and patterned for electrodes and wiring of the inverted staggered pixel structure TPT by a photo process. Thereafter, a nitride film 3 and an a-Si film (i-layer) 4 are formed by plasma CVD. a
-s is is cut into islands by a photo process, and then only the peripheral circuit portion is annealed using an excimer laser with a wavelength of 3.8 mm to polycrystallize it. Thereafter, a-Si films (n middle layer) 5 and 6 are formed by plasma CVD. After forming source and drain regions by a photo process, an oxide film 7 is formed by atmospheric pressure CVD. Patterning for the gate insulating film of the peripheral circuit section coplanar structure TPT is performed by a photo process. Next, after depositing Cr8 for signal wiring, patterning is performed in a photo process. Next, mainly the peripheral circuit section T
After depositing Ag3 for PT wiring, patterning is performed in a photo process. Next, ITOIO, which is a transparent electrode, is deposited and patterned in a photo process. Finally, the display is completed by sealing liquid crystal between the color filter and another glass substrate equipped with a polarizing plate.The 0-line display has a diagonal of 10 inches, and both the number of scanning lines and signal lines. 1200
It's a book. The peripheral circuit section includes multiplexers, inverters, level switches, and matrix switches. FIG. 1(a) shows the display substrate obtained in this manner. Here, in addition to the one pixel portion 16, peripheral circuits such as a scanning circuit 17 and a signal circuit 18 are constructed on one substrate. I can see what's going on.
以上によって、画素部分に用いられるTPTの移動度0
、2 (cd/ V s )以上、好マシくは0.3
(d/Vs)、l、、きい電圧8(V)以下、リーク電
流3X10−1!(A)以下、オン電流lXl0’(A
)以上とし、周辺回路として用いられるTPTの移動度
30 (cm2/ V s )以上、しきい電圧8(v
)以下、リーク電流2 X 10−1’(A)以下、好
ましくは1×10−11(A )以下、オン電流I X
10’(A)以上とし、高性能の表示装置が構成でき
る。As a result of the above, the mobility of TPT used in the pixel portion is 0.
, 2 (cd/Vs) or more, preferably 0.3
(d/Vs), l,, threshold voltage 8 (V) or less, leakage current 3X10-1! (A) Below, on-current lXl0'(A
) or more, the mobility of TPT used as a peripheral circuit is 30 (cm2/V s ) or more, and the threshold voltage is 8 (v
) or less, leakage current 2 x 10-1' (A) or less, preferably 1 x 10-11 (A) or less, on-current I
10'(A) or more, a high performance display device can be constructed.
本発明によれば、液晶デイスプレィの大画面化と画素駆
動用周辺回路のデイスプレィ基板への内蔵化が可能とな
る効果がある。According to the present invention, it is possible to increase the screen size of a liquid crystal display and to incorporate a pixel driving peripheral circuit into a display substrate.
第1図は本発明の一実施例の液晶デイスプレィの平面図
、及びTPT構造を示す断面図で、第1図(a)はデイ
スプレィ基板上の画素部、及び、周辺回路部を示す平面
図、第1図(b)は画素部の逆スタガー構造TPT、第
1図(Q)は周辺回路部のコープレーナ構造TPT、第
2図は本発明の別の実施例の画素部のMIMの断面構造
、第3図は従来のコープレーナ構造TPTの断面構造を
示す。
1・・・基板、2・・・Cr電極、3・・・絶縁膜、4
・・・チャネル領域、5・・・ソース、6・・・ドレイ
ン、7・・・ゲート絶縁膜、8・・・Cr配線、9・・
・Afl配線、10・・・透明電極(ITO)、11=
4’a、12−Tazoa、13・・・絶縁膜、14・
・・Cr、15・・・パシベーション膜、16・・・画
素部、17・・・走査側回路、18・・・第1図
(a)
第1図
(b)
第
図
第
図FIG. 1 is a plan view of a liquid crystal display according to an embodiment of the present invention, and a cross-sectional view showing a TPT structure, and FIG. FIG. 1(b) shows an inverted staggered structure TPT in the pixel section, FIG. 1(Q) shows a coplanar structure TPT in the peripheral circuit section, and FIG. 2 shows a cross-sectional structure of an MIM in the pixel section according to another embodiment of the present invention. FIG. 3 shows a cross-sectional structure of a conventional coplanar structure TPT. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Cr electrode, 3... Insulating film, 4
... Channel region, 5... Source, 6... Drain, 7... Gate insulating film, 8... Cr wiring, 9...
・Afl wiring, 10...transparent electrode (ITO), 11=
4'a, 12-Tazoa, 13...insulating film, 14-
...Cr, 15...passivation film, 16...pixel section, 17...scanning side circuit, 18...Fig. 1(a) Fig. 1(b) Fig. fig.
Claims (1)
する表示装置において、画素部をスタガー構造の薄膜ト
ランジスタまたは金属−絶縁物−金属(MIM)構造の
スイッチング素子で、周辺回路部をコープレーナ構造の
薄膜トランジスタで構成することを特徴とした薄膜半導
体表示装置。 2、画素部をアモルファスシリコンによるスタガー構造
の薄膜トランジスタで、周辺回路部を多結晶シリコンに
よるコープレーナ構造の薄膜トランジスタで構成するこ
とを特徴とした薄膜半導体表示装置。 3、絶縁性基板と該基板上に形成された半導体層とを有
する表示装置において、画素部の薄膜トランジスタのリ
ーク電流を周辺回路の薄膜トランジスタのリーク電流よ
り小さくし、かつ後者のキャリア移動度を前者のキャリ
ア移動度より大きくしたことを特徴とした薄膜半導体表
示装置。 4、画素部および周辺回路部が設けられた絶縁基板を具
備し、画素部に用いる薄膜トランジスタのリーク電流を
3×10^−^1^2A以下とし、周辺回路部に用いる
薄膜トランジスタの移動度を30cm^2/Vs以上と
したことを特徴とした薄膜半導体表示装置。[Claims] 1. In a display device having an insulating substrate and a semiconductor layer formed on the substrate, a pixel portion is formed of a thin film transistor with a staggered structure or a switching element with a metal-insulator-metal (MIM) structure. , a thin film semiconductor display device characterized in that a peripheral circuit section is composed of thin film transistors having a coplanar structure. 2. A thin film semiconductor display device characterized in that the pixel portion is composed of staggered thin film transistors made of amorphous silicon, and the peripheral circuit portion is composed of coplanar thin film transistors made of polycrystalline silicon. 3. In a display device having an insulating substrate and a semiconductor layer formed on the substrate, the leakage current of the thin film transistor in the pixel portion is made smaller than the leakage current of the thin film transistor in the peripheral circuit, and the carrier mobility of the latter is made smaller than that of the former. A thin film semiconductor display device characterized by having a carrier mobility greater than that of a carrier. 4. An insulating substrate provided with a pixel part and a peripheral circuit part is provided, the leakage current of the thin film transistor used in the pixel part is 3×10^-^1^2 A or less, and the mobility of the thin film transistor used in the peripheral circuit part is 30 cm. A thin film semiconductor display device characterized by having a voltage of ^2/Vs or more.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1221495A JPH0385529A (en) | 1989-08-30 | 1989-08-30 | Thin film semiconductor display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1221495A JPH0385529A (en) | 1989-08-30 | 1989-08-30 | Thin film semiconductor display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0385529A true JPH0385529A (en) | 1991-04-10 |
Family
ID=16767607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1221495A Pending JPH0385529A (en) | 1989-08-30 | 1989-08-30 | Thin film semiconductor display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0385529A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0611738A (en) * | 1992-03-20 | 1994-01-21 | Philips Gloeilampenfab:Nv | Electronic device manufacturing method |
JPH0695071A (en) * | 1992-09-09 | 1994-04-08 | Toshiba Corp | Liquid crystal display device |
JPH0792500A (en) * | 1993-06-29 | 1995-04-07 | Toshiba Corp | Semiconductor device |
KR100262402B1 (en) * | 1997-04-18 | 2000-08-01 | 김영환 | Tft lcd and its fabrication method |
KR100265751B1 (en) * | 1992-09-07 | 2000-09-15 | 윤종용 | Lcd and its fabrication method |
-
1989
- 1989-08-30 JP JP1221495A patent/JPH0385529A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0611738A (en) * | 1992-03-20 | 1994-01-21 | Philips Gloeilampenfab:Nv | Electronic device manufacturing method |
KR100265751B1 (en) * | 1992-09-07 | 2000-09-15 | 윤종용 | Lcd and its fabrication method |
JPH0695071A (en) * | 1992-09-09 | 1994-04-08 | Toshiba Corp | Liquid crystal display device |
JPH0792500A (en) * | 1993-06-29 | 1995-04-07 | Toshiba Corp | Semiconductor device |
KR100262402B1 (en) * | 1997-04-18 | 2000-08-01 | 김영환 | Tft lcd and its fabrication method |
US6191835B1 (en) | 1997-04-18 | 2001-02-20 | Hyundai Electronics Industries Co., Ltd. | Thin film transistor liquid crystal display and method for manufacturing the same |
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