JPH0470773B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) The present invention relates to a method for manufacturing a thin film transistor using an amorphous semiconductor.

(2) Background of the technology A field-effect thin film transistor is a device in which a gate electrode, a gate insulating film, an amorphous silicon layer which is an amorphous semiconductor, and source and drain electrodes are provided on a suitable substrate such as a glass plate. It is attracting attention as a driving element for large, segmented liquid crystal displays.

Figure 1 shows one example, where S is the source electrode, G
is the gate electrode. These constitute the vertical and horizontal lines of the matrix. D is the drain electrode, which is a rectangle with a large area, and the counter electrode ITO as shown in figure b.
Together, they constitute a pair of electrodes of a liquid crystal panel, and liquid crystal is sealed between these electrodes. The electrode spacing L is
It is about 10μm. When the source electrode S and the gate electrode G are selected, that is, when a voltage is applied, the source voltage is applied to the drain D that constitutes the FET together with the selected source and gate electrode, and the arrangement of the liquid crystal between the drain and the counter electrode ITO changes. , that part becomes transparent and appears white (or non-transparent and appears black). In order to express delicate images, a large number of micropixels are required, and the screen needs to be a certain size, so even if it is an A4 size screen, it cannot be seen with an IC using a chip of several mm square. In this case, it becomes extremely large, and thin film transistors are suitable for such applications.

(3) Conventional technology and problems Conventionally used thin film transistors that do not use self-alignment have the disadvantage of slow pulse response speed due to parasitic capacitance due to large overlap between the gate, source, and drain. . Also, when looking at this from the perspective of a manufacturing process that uses high-resistance semiconductors such as amorphous silicon, if these overlaps are eliminated, a large series resistance will be inserted in the source or drain region, so a precise mask is required. There was a drawback that even higher alignment accuracy was required. Therefore, self-aligned thin film transistors have been developed in which source and drain electrodes are formed using the gate electrode as a mask.

FIG. 2 is a diagram showing a self-aligned thin film transistor, in which 1 is a glass substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is a source electrode, 5 is a drain electrode, and 6 is an amorphous silicon layer which is a semiconductor layer. are shown respectively.

In this self-aligned thin film transistor, the interface between the gate insulating film 3 and the amorphous silicon layer 6 must be kept clean during the manufacturing process for stable operation. Since it is necessary to form a pattern by breaking the pattern, there is a drawback that contamination of the interface is unavoidable. For this reason, a self-aligned thin film transistor as shown in FIG. 3 has been proposed. In the same figure,
10 is a glass substrate, 11 is a gate electrode, 12 is a gate insulating film, 13 is a source electrode, 14 is a drain electrode, 15 is a first amorphous semiconductor layer, 16
indicate the second amorphous semiconductor layer, respectively. This thin film transistor has a gate insulating film 12
A first amorphous semiconductor layer 15 is formed on the surface of the source and drain electrodes 13 and 1.
This thin film transistor differs from the thin film transistor shown in FIG. 2 in that the second amorphous semiconductor layer 4 and the second amorphous semiconductor layer 16 are stacked. This gate insulating film 12 and the first
To form the amorphous semiconductor layer 15, first, a silicon dioxide gate insulating film 12 is formed by a plasma CVD method using a mixed atmosphere of silane gas (SiH ₄ ) and nitrous oxide (N ₂ O), and then the vacuum state is broken. The first amorphous semiconductor layer 15 of amorphous silicon can be continuously formed in a silane gas atmosphere by changing the gas without any process. Therefore, the gate insulating film 1 forming the channel
The interface between the amorphous semiconductor layer 2 and the first amorphous semiconductor layer 15 is not contaminated.

However, in this self-aligned thin film transistor, the only electrode material that can form an ohmic connection with amorphous silicon is aluminum, and when aluminum is used as an electrode material, heating of approximately 300°C is required during the formation of alignment films in the liquid crystal manufacturing process. This heating causes aluminum to diffuse into the amorphous silicon layer, making it impossible to maintain the initial characteristics and making it difficult to use as a liquid crystal drive circuit.
The drawback was that the ON/OFF current ratio could not be wide enough and the contrast of the liquid crystal deteriorated.

(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the object of the present invention is to provide a self-aligned thin film transistor that can maintain initial characteristics and improve contrast when used in a liquid crystal drive circuit. That is.

(5) Structure of the Invention According to the present invention, this object includes a step of sequentially stacking a gate electrode 21, a gate insulating film 22, and a first amorphous semiconductor layer 23 on a glass substrate 20; A positive resist is applied on the layer 23 and exposed from the glass substrate 20 side to form a resist film 2 above the gate electrode 21.
4, and on the first amorphous semiconductor layer 23 and resist film 24, an n ⁺ or p ⁺ amorphous semiconductor layer 25 doped with phosphorus, boron, etc. is formed by a glow discharge decomposition method, and then The resist film 24 and the n ⁺ or p ⁺ amorphous semiconductor layer 2 thereon are formed by depositing the source/drain electrode material 26 and using a lift-off method.
5 and removing the electrode material 26 to form a source electrode 27 and a drain electrode 28 whose edges are aligned with the gate electrode 21;
The second amorphous semiconductor layer 29 is formed by plasma CVD at a temperature of 350°C, and the n ⁺ or p ⁺ amorphous semiconductor layer 2 is formed at a temperature of 350°C.
This is achieved by providing a method for manufacturing a self-aligned thin film transistor, which is characterized by comprising a step of activating a self-aligned thin film transistor.

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a diagram for explaining the method of manufacturing a self-aligned thin film transistor according to the present invention, and shows a to
f indicates the manufacturing process. In the figure, 20 is a glass substrate, 21 is a gate electrode, 22 is a gate insulating film, 23 is a hydrogenated amorphous silicon layer as a first amorphous semiconductor layer, 24 is a photoresist, and 25 is an amorphous film doped with phosphorus or boron. 26 is a source and drain electrode material, 27 is a source electrode, 28 is a drain electrode, 29 is a second amorphous semiconductor layer, and 30 is a protective film.

To explain the method of the present invention with reference to figures, first, as shown in figure a, a gate electrode 21 is formed on a glass substrate 20, and then a gate insulating film 22 of SiO ₂ , Si ₃ N ₄ , etc. is formed by plasma CVD method. 50 Å as the first amorphous semiconductor layer 23 on top without breaking the vacuum.
~1000 Å non-doped a-Si:H film in plasma
Formed by CVD method.

Next, as shown in figure b, a positive type resist is spin-coated, and after baking, it is exposed from the back side of the substrate, and the gate 21
A self-aligned pattern 24 is formed.

Next, as shown in figure c, it contained 200ppm to 1% of PH ₃ .
n ⁺ a-Si:H film 25 by _SiH4 plasma CVD method
After depositing an electrode material 26 such as NiCr or Al on top of the electrode material 26, lift-off removes unnecessary portions of the electrode, n ⁺ a-Si:H layer and non-doped a-Si:
The H layer is etched to obtain a device as shown in figure d.

Next, as shown in figure e, a non-doped a-Si:H
A film is formed by plasma CVD, and then SiO ₂ or Si ₃ N ₄ is formed as a protective film 30 by plasma CVD without breaking the vacuum.

Finally, unnecessary portions of the second amorphous semiconductor layer 29 and the protective film 30 are removed to complete the process, as shown in FIG.

Among the above steps, in the step shown in figure e, the second
The amorphous semiconductor layer 29 and protective film 30 of
Since it is formed at a temperature of 250 to 350°C, the P-doped n ⁺ a-Si:H layer 25 formed earlier at a low temperature is activated and becomes a blocking layer against holes, resulting in good ON/OFF.
This results in a stable TFT with an OFF current ratio.

FIG. 5 is a diagram showing the relationship between drain current _ID and gate voltage V _G of a self-aligned thin film transistor formed by the method of the present invention in comparison with a conventional example. In the figure, curve A shows the case of the present invention, and curve B shows the case of the conventional example. The figure shows that in the conventional example, when the gate voltage is below OV, the current flowing due to hole accumulation due to diffusion of the electrode material increases, but in the case of the present invention, normal initial characteristics are maintained. I understand.

FIG. 6 is a diagram showing an embodiment of the present invention. In the figure, 20 is a glass substrate, 21 is a gate electrode, 22 is a gate insulating film, 23 is an a-Si:H layer which is the first amorphous semiconductor layer, 25, 25'
is an n ⁺ a−Si:H layer doped with phosphorus or boron,
27 and 28 are source and drain electrodes, 29 is a second
a-Si:H layer, which is an amorphous semiconductor layer, 3
0 indicates a protective layer.

The difference between this example and the previous example is that the source
Drain electrode, n ⁺ a-Si:H layer 25/source,
Drain electrodes 27, 28/n ⁺ a-Si:H layer 25'
This is a three-layer structure with the expectation that it will form an ohmic connection from both sides with the upper and lower non-doped a-Si:H layers.

Furthermore, an example of an ohmic electrode using an a-Si:H film doped with phosphorus P has been shown so far, but in this case blocking is performed for holes. When forming an ohmic electrode for blocking electrons, an a-Si:H film doped with boron B may be used in exactly the same process.

(7) Effects of the Invention As explained above in detail, the method for manufacturing a self-aligned thin film transistor of the present invention uses amorphous silicon doped with phosphorus or boron as an ohmic electrode, and heats it to 250 to 350°C. By activating the thin film transistor, it is possible to obtain a thin film transistor that maintains its initial characteristics, and it has a great effect in that it can be used in the drive circuit of a liquid crystal display to improve its contrast. It is.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a liquid crystal display, FIGS. 2 and 3 are diagrams for explaining a conventional self-aligned thin film transistor, and FIG. 4 is a diagram for explaining a method for manufacturing a self-aligned thin film transistor according to the present invention. FIG. 5 is a characteristic diagram of a self-aligned thin film transistor formed by the method of the present invention.
FIG. 6 is a diagram showing another embodiment. In the drawing, 20 is a glass substrate, 21 is a gate electrode, 22 is a gate insulating film, 23 is a first amorphous semiconductor layer, 24 is a photoresist, 25 is an amorphous silicon layer doped with phosphorus or boron, and 26 is a source and a drain. 27 is a source electrode, 28 is a drain electrode, 29 is a second amorphous semiconductor layer, and 30 is a protective film.

Claims (1)

[Claims] 1. A step of sequentially laminating a gate electrode 21, a gate insulating film 22, and a first amorphous semiconductor layer 23 on a glass substrate 20, and applying a positive resist on the first amorphous semiconductor layer 23. Then, a step of forming a resist film 24 above the gate electrode 21 by exposing from the glass substrate 20 side, and n ⁺ doping with phosphorus, boron, etc. on the first amorphous semiconductor layer 23 and the resist film 24.
Alternatively, a step of forming a P ⁺ amorphous semiconductor layer 25 by a glow discharge decomposition method, depositing a source/drain electrode material 26 thereon, and a lift-off method is performed to form a P ⁺ amorphous semiconductor layer 25 along with the resist film 24 on the n ⁺ amorphous semiconductor layer 25 . The semiconductor layer 25 and the electrode material 26 are removed so that the edge becomes the gate electrode 21.
source electrode 27 and drain electrode 28 matched to
and plasma at a temperature of 250 to 350°C on the source electrode 27, drain electrode 28 and the gap therebetween.
The second amorphous semiconductor layer 29 is formed by the CVD method.
At the same time, depending on the temperature, the n ⁺ or
A method for manufacturing a self-aligned thin film transistor, comprising: activating a P ⁺ amorphous semiconductor layer 25.