JP3406491B2 - Electro-optic sampling oscilloscope - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses an optical pulse generated based on a signal from a delay circuit that delays a trigger signal according to a waveform observation position of a signal under measurement to measure the signal under measurement. The present invention relates to an electro-optical sampling oscilloscope which is characterized by a delay circuit for delaying a trigger signal.

[0002]

2. Description of the Related Art It is possible to observe the waveform of a signal under measurement by coupling an electric field generated by the signal under measurement with an electro-optic crystal, injecting laser light into the electro-optic crystal, and observing the polarization state of the laser light. Here, pulse the laser light,
When the signal under measurement is sampled, it can be measured with very high time resolution. An electro-optic sampling oscilloscope uses an electro-optic probe that takes advantage of this phenomenon. This electro-optical sampling oscilloscope (hereinafter abbreviated as “EOS oscilloscope”) is compared with a conventional sampling oscilloscope using an electric probe, and 1) does not require a ground line when measuring a signal, so Easy 2) Since the metal pin at the tip of the electro-optic probe is insulated from the circuit system, a high input impedance can be realized, and as a result, the state of the measured point is hardly disturbed 3) Since an optical pulse is used It has attracted attention because it has a feature that it can measure wideband up to GHz order (Shinagawa et al .: “EO
Handheld High Impedance Probe by S ", Proceedings of 15th Workshop on Lightwave Sensing Technology, Japan Society of Applied Physics, Lightwave Sensing Technology Workshop, May 1995, p.
p. 123-129).

First, the configuration of the EOS oscilloscope will be described with reference to FIG. The EOS oscilloscope is composed of a main body 1 of the EOS oscilloscope and an electro-optic probe 2. Then, in the main body 1 of the EOS oscilloscope, the trigger circuit 3 outputs a trigger signal for starting measurement of the measurement signal. Then, the delay circuit 4 delays the signal from the trigger circuit 3 by the time set by the setting unit 9. The setting unit 9 is composed of a switch or the like, and the delay time set by the setting unit 9 is set in the delay circuit 4 via the processing circuit 8. Timing generation circuit 5
Generates the optical pulse generation timing and the A / D conversion timing based on the signal from the delay circuit 4, and the optical pulse generation circuit 6 generates the optical pulse based on the timing signal from the timing generation circuit 5. To do. Then, the optical pulse from the optical pulse output circuit 6 is supplied to the electro-optical probe 2 and undergoes polarization change by the electro-optical element.
The optical pulse that has undergone this polarization change is the electro-optical probe 2
Polarization detection is performed by a polarization detection optical system (not shown) therein, and the signal is input to the main body 1 of the EOS oscilloscope. Then, this signal is amplified and A / D converted by the A / D conversion circuit 7, and processed by the processing circuit 8 for displaying the signal to be measured and the like.

Next, the reason why the delay circuit 4 delays the trigger signal from the trigger circuit 3 will be described with reference to FIG. As shown in FIGS. 5A and 5B, the trigger signal from the trigger circuit 3 is generally generated almost in synchronization with the signal under measurement. In the case of FIG. 5, the waveform from the measurement point A1 or the measurement point A2 is displayed on the display unit (not shown) of the main body 1 of the EOS oscilloscope. Here, there are cases where the user of the EOS oscilloscope desires not to display the waveform from the measurement point A1 or A2 but to display the waveform from the measurement point B1 or B2 slightly delayed from the measurement point. In this way, the delay circuit 4 is used to move the waveform display start position. For example, when the user of the EOS oscilloscope desires to display the waveform from the measurement point B1 instead of the measurement point A1, the setting unit 9 in FIG. 4 sets the display start position of the signal under measurement to be delayed. This setting information is analyzed by the processing circuit 8, the delay time T ′ of the measurement point B1 with respect to the measurement point A1 is obtained, and the delay time T ′ is set in the delay circuit 4. Then, the delay circuit 4 is shown in FIG.
As shown in (c), the trigger signal is delayed by the delay time T'and output. Then, the timing for sampling is generated using the output from the delay circuit 4.

FIG. 6 is a diagram showing an example of a conventional configuration of the delay circuit 4. As shown in FIG. 6, the delay circuit 4 includes a ramp circuit 31 having a trigger signal as an input signal, a D / A converter 32 for D / A converting a delay time setting signal from the processing circuit 8,
It comprises a ramp circuit 31 and a comparison circuit 33 for comparing the output signals from the D / A converter 32. Next, the operation of the delay circuit shown in FIG. 6 will be described with reference to FIG. Figure 7
When the trigger signal is input to the ramp circuit 31 as shown in (a), the ramp circuit 31 outputs the ramp signal as shown in FIG. 7 (c) by using this signal as a trigger. On the other hand, the D / A converter 32 outputs the output signal obtained by D / A converting the delay time setting signal from the processing circuit 7 as shown in FIG. 7B. Here, if the value set from the delay circuit 7 is the delay time T ′, the D / A converter 32
Outputs a signal higher than the reference level by an amount corresponding to this delay time T '. Ramp circuit 31 and D / A
The output from the converter 32 is compared by the comparison circuit 33, and a signal obtained by delaying the trigger signal by the time T'is output as shown in FIG. 7C.

[0006]

However, depending on the measurement signal, there are cases where a relatively long time, for example, a delay of the order of milliseconds [ms] or seconds [s] is desired. However, in the delay circuit 4 of the EOS oscilloscope described above, the delay time is set by using the ramp signal from the ramp circuit 31, but in the case of such a long delay time, fluctuations and jitters occur in the ramp signal, and the reproduction is reproduced. The sex is not good. That is, it is not possible to accurately set the delay time on the order of milliseconds [ms] or seconds [s].

The present invention has been made in view of the above circumstances, and an object thereof is to provide an electro-optical sampling oscilloscope capable of stably setting a delay time even if a relatively long delay time is set. .

[0008]

In order to achieve the above object, the invention according to claim 1 of the present invention is a signal from a delay circuit for delaying a trigger signal according to a waveform observation position of a signal under measurement. An electro-optical sampling oscilloscope that measures the signal under measurement by using an optical pulse generated based on the delay signal, wherein the delay circuit delays the reference clock from the reference clock generation circuit with respect to the trigger signal. A delay time detection circuit that detects a value corresponding to time,
A correction time determination circuit that determines a correction time based on a value detected by the delay time detection circuit so that the correction time is an integral multiple of the reference clock, and the reference clock is counted to a predetermined value by using the trigger signal as a trigger. Using a counter circuit and a signal relating to the correction time from the correction time determination circuit, with respect to the output signal from the counter circuit,
An electro-optic sampling oscilloscope, comprising: a delay correction circuit for delaying the correction time.

The invention described in claim 2 is the same as claim 1.
In the electro-optical sampling oscilloscope according to, the delay time detection circuit is a ramp circuit that outputs a ramp waveform by using the trigger signal as a trigger, and the reference clock that is input immediately after the trigger signal is a trigger from the ramp circuit. And an A / D conversion circuit that changes the output of the analog / digital converter, and the correction time determination circuit subtracts the output value from the A / D conversion circuit from a value corresponding to an integral multiple of the cycle of the reference clock. And an D / A conversion circuit for performing digital / analog conversion on the value from the arithmetic circuit.

The invention described in claim 3 is the same as claim 1
In the electro-optical sampling oscilloscope according to, the delay time detection circuit is a ramp circuit that outputs a ramp waveform by using the trigger signal as a trigger, and the reference clock that is input immediately after the trigger signal is a trigger from the ramp circuit. And a sample hold circuit for holding the output of the sample hall circuit, wherein the correction time determination circuit is a subtraction circuit for subtracting a signal corresponding to an integral multiple of the cycle of the reference clock and an output signal from the sample hall circuit. Is characterized by.

Next, the invention according to claim 4 uses the optical pulse generated based on the signal from the delay circuit for delaying the trigger signal according to the waveform observation position of the signal under measurement, An electro-optical sampling oscilloscope for measuring a signal, wherein the delay circuit outputs a ramp waveform by using the trigger signal as a trigger,
A delay time detection circuit including an A / D conversion circuit that analog-digitally changes the output from the ramp circuit with a reference clock from the reference clock generation circuit input immediately after the trigger signal as a trigger, and the reference clock An arithmetic circuit that subtracts the output value from the delay time detection circuit from a value corresponding to an integral multiple of the cycle and adds the set fine adjustment value, and D / that converts the value from the arithmetic circuit into digital / analog. An output signal from the counter circuit using a correction time determination circuit including an A conversion circuit, a counter circuit that counts the reference clock to a predetermined value by using the trigger signal as a trigger, and a signal from the correction time determination circuit. On the other hand, a delay correction circuit for delaying by a signal from the correction time determination circuit is provided. Is grayed oscilloscope.

Next, the invention according to claim 5 uses the optical pulse generated based on the signal from the delay circuit for delaying the trigger signal according to the waveform observation position of the signal under measurement, An electro-optical sampling oscilloscope for measuring a signal, wherein the delay circuit outputs a ramp waveform by using the trigger signal as a trigger,
A delay time detection circuit composed of a sample hold circuit for holding the output from the ramp circuit by using a reference clock from the reference clock generation circuit input immediately after the trigger signal as a trigger, and an integral multiple of the cycle of the reference clock. A correction time determination circuit that subtracts a corresponding signal and an output signal from the sample hall circuit and adds a signal related to a set fine adjustment value, and a counter that counts the reference clock to a predetermined value by using the trigger signal as a trigger. Circuit and the signal from the correction time determination circuit,
An electro-optical sampling oscilloscope, comprising: a delay correction circuit that delays an output signal from the counter circuit with a signal from the correction time determination circuit.

According to a sixth aspect of the present invention, in the electro-optical sampling oscilloscope according to any one of the first, fourth and fifth aspects, the delay correction circuit outputs the output signal from the counter circuit. Is used as a trigger to output a ramp waveform, and a comparison circuit that compares the output from the ramp circuit with the output from the correction time determination circuit.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An electro-optical sampling oscilloscope according to an embodiment of the present invention will be described below with reference to the drawings. First, the configuration of the EOS oscilloscope will be described with reference to FIG. As described above, the EOS oscilloscope is composed of the main body 1 of the EOS oscilloscope and the electro-optic probe 2. The main body of the EOS oscilloscope includes a trigger circuit 3, a delay circuit 4, a timing generation circuit 5, an optical pulse generation circuit 6, an A / D conversion circuit 7,
It is composed of a processing circuit 8 and a setting unit 9. In the main body 1 of this EOS oscilloscope, the trigger circuit 3 outputs a trigger signal for starting the measurement of the measurement signal. Then, the delay circuit 4 delays the signal from the trigger circuit 3 by the time set by the setting unit 9. The setting unit 9 is composed of a switch or the like, and the delay time set by the setting unit 9 is set in the delay circuit 4 via the processing circuit 8. The timing generation circuit 5 generates the optical pulse generation timing and the A / D conversion timing based on the signal from the delay circuit 4, and the optical pulse generation circuit 6 outputs the optical pulse based on the timing signal from the timing generation circuit 5. Generates a pulse.

The optical pulse from the optical pulse output circuit 6 is supplied to the electro-optical probe 2 and undergoes polarization change by the electro-optical element. A polarization detection optical system (not shown) in the electro-optic probe 2 performs polarization detection and the like on the optical pulse subjected to the polarization change, and the signal is input to the main body 1 of the EOS oscilloscope. A signal from the electro-optical probe 2 is amplified and A / D converted by the A / D conversion circuit 7.
The conversion is performed, and the processing circuit 8 performs processing for displaying the signal to be measured and the like.

Next, the circuit configuration of the delay circuit 4 in the EOS oscilloscope according to the present embodiment will be described with reference to FIG. From FIG. 1, the delay circuit 4 receives the trigger signal from the trigger circuit 3 and the processing circuit 7 as input signals.
In addition to the delay time from, the reference clock from a reference clock generation circuit (not shown) in the EOS oscilloscope is input. On the other hand, the output signal is a signal obtained by delaying the trigger signal by the set time. In the figure, in addition to the input signal, the fine adjustment value T3 set via the processing circuit 7 is input, but this signal will be described separately. The trigger signal and the reference clock are generated by different circuits and are asynchronous.
The delay circuit 4 includes a delay time detection circuit 11 that detects a value corresponding to the delay time between the asynchronous trigger signal and the reference signal,
Based on the value detected by the delay time detection circuit 11, the correction time determination circuit 12 that determines the correction time so that the correction time is an integral multiple of the cycle of the reference clock, and the delay time set by the processing circuit 7, The counter circuit 13 that counts the reference clock and the time delayed by the counter circuit 13 are further delayed by the correction time from the correction time determination circuit 12, and a signal obtained by delaying the trigger signal by an integral multiple of the reference clock is output. And a delay time correction circuit 14 for

Here, the delay time detection circuit 11 outputs a ramp waveform with a trigger signal as a trigger.
11a and an A / D conversion circuit 11b for A / D converting the ramp signal of the ramp circuit 1 / 11a at the timing of the reference clock input immediately after the input of the trigger signal. Further, the correction time determination circuit 12 obtains the delay time T1 of the reference signal with respect to the trigger signal based on the output from the delay time detection circuit 11, and subtracts the obtained delay time T1 from the period T of the known reference clock. And delay circuit 4
Calculation circuit 1 for obtaining the correction time T2 (= T-T1) so that the delay time due to
2a and a D / A conversion circuit 12b for D / A converting the output from the arithmetic circuit 12a.

The delay correction circuit 14 compares the signals from the ramp circuit 2.14a and the correction time determination circuit 12 with the ramp circuit 2.14a which outputs the ramp signal by using the signal from the counter circuit 13 as a trigger. By doing so, the signal from the counter circuit 13 is further delayed by the correction time T2, and the comparison circuit 14b outputs a signal.
In the following description, the term "EOS oscilloscope" may be provided with the electro-optic probe 2 together with the body 1 of the EOS oscilloscope shown in FIG. 4, or with the body 1 of the EOS oscilloscope alone.

Next, the operation of the delay circuit 4 shown in FIG. 1 will be described with reference to FIG.
Will be explained. Here, the delay circuit 4 is shown in FIG.
It is assumed that the trigger signal as shown in and the reference clock as shown in FIG. The frequency of the reference clock is assumed to be a relatively high frequency such as megahertz [MHz] or kilohertz [KHz]. When the trigger signal is input at time t1, the lamp circuit 1 · 11a is triggered by this signal and the lamp circuit 1 · 11a shown in FIG.
As shown in (c), the output of the ramp signal is started. Assuming that the reference clock rises for the first time at time t2 after the input of the trigger signal, the output value D1 of the ramp circuits 1 and 11a is changed to A / D by the A / D conversion circuit 11b at the timing of time t2. To be converted.
Since the reference clock has a relatively high frequency, it is A / D converted by the A / D conversion circuit 11b within a range in which the ramp signal from the ramp circuits 1 and 11a is stable.

Further, the counter circuit 13 counts the reference clocks the number of times corresponding to the set delay time by using the input of the trigger signal as a trigger. Here, the reference clock is counted with reference to the rising edge of the signal. For example, if the count number judged by the processing circuit 8 is “N” based on the delay time set by the setting unit 9 in FIG. 4, one cycle of the reference signal corrected by the delay correction circuit 14 is obtained. Count number excluding "N-
1 "is set in the counter circuit 13, and as shown in FIG. 2 (d), the counter circuit 13 sets the count number" N-
The reference clock is counted by 1 ″. At time t3 when the counting operation by the counter circuit 13 ends, the counter circuit 13 outputs a signal, and this signal is used as a trigger.
The ramp circuit 2.14a outputs a ramp signal as shown in FIG.

On the other hand, from the delay time detection circuit 11 to FIG.
Upon receiving the value D1 shown in (c), the arithmetic circuit 12a obtains the delay time T1 (t2-t1) of the reference clock with respect to the trigger signal from this value D1. Note that the delay time T1 and the value D1 are in a proportional relationship, and the proportional constant is the ramp circuit 1 ·
11a. Then, the arithmetic circuit 12a
It is assumed that a proportional constant that can be determined by the ramp circuit 1 · 11a is stored as known information. Also, the arithmetic circuit 1
In 2a, the cycle T of the reference clock is also stored in advance as a known value, and the correction time T2 is calculated by T2 = T-T1. This calculation result is converted by the D / A conversion circuit 12b according to the characteristics of the ramp circuit 2,
As shown in (e), a signal higher than the reference level by D2 is output.

The comparison circuit 14b compares the signal from the ramp circuit 2.14a shown in FIG. 2 (e) with the signal from the correction time determination circuit 12, and the ramp circuit 2.14a receives the signal from the counter circuit 13. The signal is output at the timing of time t4, which is further delayed from the time t3 by the correction time T2. The sum of the delay time T1 with respect to the trigger signal and the correction time T2 determined by the correction time determination circuit 12 matches the cycle T of the reference clock. In addition, the counter circuit 13
In, the signal is output after counting the reference clock (N-1) times. Therefore, the time t1 when the trigger signal is input and the time t1 when the signal is output from the delay circuit 4
The difference from 4 is t4−t1 = T × N, and the trigger signal is delayed by the reference clock by the delay circuit 4 and output.

In the delay circuit 4 of FIG. 1, the delay time detection circuit 11 and the correction time determination circuit 12 perform the intermediate processing with a digital signal. However, the delay time detection circuit 11 in the case where this is all performed with an analog signal. The configuration of the correction time determination circuit 12 is shown in FIG. In the case of FIG. 3, the delay time detection circuit 11 includes a ramp circuit 1.1a and a ramp circuit 1.1a.
It is composed of a sample hold circuit 11c that holds the output from 11a at the rising timing of the reference clock immediately after the trigger signal is input. The correction time determination circuit 12 is composed of a subtraction circuit 12c that subtracts the signal level from the sample hold circuit 11c from the signal level according to the cycle T of the reference clock, and the output from the subtraction circuit 12c relates to the correction time T2. The signal is input to the delay correction circuit 14 as a signal.

As described above, the ramp circuits 1 and 11a that form the delay time detection circuit 11 and the ramp circuits 2 and 14a that form the delay correction circuit 14 are used in the range where the signal is stable, so that they are accurate. The delay time can be detected and the signal from the counter circuit 13 can be delayed.
Further, even when the delay time is long, the delay time is mainly set by the counter circuit 13, so that the delay can be accurately realized by an integral multiple of the cycle of the reference clock.

In FIG. 1, the fine adjustment value T3 (0.ltoreq.T3.ltoreq.T: T is the cycle of the reference clock) set by the setting unit 9 is also input to the arithmetic circuit 12a via the processing circuit 7 in FIG. Assuming that the fine adjustment value T3 is used, the arithmetic circuit 1
2a, the correction time T2 may be obtained by T2 = T-T1 + T3. As a result, the delay time can be set more finely than the period T of the reference clock. Similarly, it is assumed that the level signal corresponding to the fine adjustment value T3 is also input to the subtraction circuit 12c shown in FIG. 3, and the subtraction circuit 12c further adds this signal to make the delay time finer than the cycle T of the reference clock. You can set it.

In the present embodiment, the correction time determination circuit 12 in the delay circuit 4 preferably determines the correction time T2 with reference to "T" for one cycle of the reference clock. The present invention is not limited to this, and the correction time T2 may be calculated with reference to an integral multiple of the cycle T within a range in which the ramp signal from the ramp circuit 2.14a is stable. Further, although the fine adjustment value T3 input to the correction time determination circuit 12 is described as being within one cycle T of the reference clock as a preferable range, the fine adjustment value T3 is not limited to this. Further, the delay circuit 4 described above may perform not only the delay of the trigger signal but also the delay process for the signal that needs to be delayed in the EOS oscilloscope.

[0027]

As described above, according to the electro-optic sampling oscilloscope of the present invention, the following effects can be obtained. The ramp circuits 1 and 11a that form the delay time detection circuit 11 and the ramp circuits 2 and 14a that form the delay correction circuit 14 are used within a stable signal range, so that the delay time can be accurately detected and the counter can be used. The signal from the circuit 13 can be delayed, and
Even if the delay time is long, the counter circuit 13 is mainly used.
Since the delay time is set by, the delay of an integral multiple of the cycle of the reference clock can be realized accurately and stably.
Furthermore, by allowing the fine adjustment value T3 to be set in the delay circuit 4, the delay time can be set more finely than the cycle T of the reference clock.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a delay circuit in an EOS oscilloscope according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the delay circuit in FIG.

3 is another circuit configuration diagram of a delay time detection circuit and a correction time determination circuit in the delay circuit of FIG.

FIG. 4 is a diagram showing a configuration of an EOS oscilloscope.

FIG. 5 is a diagram for explaining the role of a delay circuit in an EOS oscilloscope.

FIG. 6 is a diagram showing a circuit configuration in a conventional example of a delay circuit in an EOS oscilloscope.

FIG. 7 is a diagram for explaining the operation of the delay circuit in FIG.

[Explanation of symbols]

1 Main body of EOS oscilloscope 2 Electro-optic probe 3 Trigger circuit 4 Delay circuit 5 Timing generation circuit 6 Optical pulse generation circuit 7 A / D conversion circuit 8 Processing circuit 9 Setting section 11 Delay time detection circuit 11a Lamp circuit 1 11b A / D
Conversion circuit 12 Correction time determination circuit 12a Operation circuit 12b D / A
Conversion circuit 13 Counter circuit 14 Delay correction circuit 14a Ramp circuit 2 14b Comparison circuit 11c Sample hold circuit 12c Subtraction circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Kikuchi 4-19-7 Kamata, Ota-ku, Tokyo Ando Electric Co., Ltd. (72) Yoshio Endo 4-19-7 Kamata, Ota-ku, Tokyo Ando Electric Incorporated (72) Inventor Mitsuru Shinagawa 3-19-3 Nishishinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Tadao Nagatsuma 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Telegraph and Telephone Corporation (72) Inventor Ichiyoshi Matsuhiro 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) Reference JP-A-1-98973 (JP, A) Kaihei 4-109171 (JP, A) JP-A-55-42003 (JP, A) Actual Kaihei 5-52770 (JP, U) JP-B-45-40876 (JP, B1) (58) Fields investigated ( Int.Cl. ⁷ , DB name) G01R 13/00-13/42

Claims (6)

(57) [Claims] 1. An electro-optical sampling oscilloscope that measures a signal under measurement by using an optical pulse generated based on a signal from a delay circuit that delays a trigger signal according to a waveform observation position of the signal under measurement. Wherein the delay circuit detects a value corresponding to the delay time of the reference clock from the reference clock generation circuit with respect to the trigger signal, and a value detected by the delay time detection circuit. A correction time determination circuit that determines a correction time so as to be an integral multiple of the reference clock, a counter circuit that counts the reference clock to a predetermined value by using the trigger signal as a trigger, and the correction time determination circuit And a delay correction circuit for delaying the output signal from the counter circuit by the correction time by using the signal related to the correction time. Electro-optical sampling oscilloscope, characterized in that. 2. The delay time detection circuit includes a ramp circuit that outputs a ramp waveform by using the trigger signal as a trigger, and an output from the ramp circuit that is analog by using the reference clock input immediately after the trigger signal as a trigger. A digitally changing A / D conversion circuit, the correction time determination circuit subtracting an output value from the A / D conversion circuit from a value corresponding to an integral multiple of the cycle of the reference clock; , D for converting the value from the arithmetic circuit into digital / analog
The electro-optic sampling oscilloscope according to claim 1, wherein the electro-optic sampling oscilloscope comprises an A / A conversion circuit. 3. The delay time detection circuit holds a output from the ramp circuit with a ramp circuit that outputs a ramp waveform by using the trigger signal as a trigger, and the reference clock that is input immediately after the trigger signal as a trigger. The correction time determination circuit is a subtraction circuit for subtracting a signal corresponding to an integral multiple of the cycle of the reference clock and an output signal from the sample hall circuit. The electro-optic sampling oscilloscope according to claim 1. 4. An electro-optical sampling oscilloscope that measures a signal under measurement by using an optical pulse generated based on a signal from a delay circuit that delays a trigger signal according to a waveform observation position of the signal under measurement. Wherein the delay circuit uses a ramp circuit that outputs a ramp waveform by using the trigger signal as a trigger and a reference clock from a reference clock generation circuit that is input immediately after the trigger signal as a trigger, and outputs the output from the ramp circuit. Analog and digital changing A
A delay time detection circuit including a D / D conversion circuit, and an operation of subtracting an output value from the delay time detection circuit from a value corresponding to an integral multiple of the cycle of the reference clock and adding a set fine adjustment value. A correction time determination circuit including a circuit and a D / A conversion circuit that performs digital / analog conversion of the value from the arithmetic circuit; a counter circuit that counts the reference clock to a predetermined value by using the trigger signal as a trigger; An electro-optic sampling oscilloscope, comprising: a delay correction circuit that delays an output signal from the counter circuit with a signal from the correction time determination circuit using a signal from the time determination circuit. 5. An electro-optic sampling oscilloscope for measuring a signal under measurement by using an optical pulse generated based on a signal from a delay circuit that delays a trigger signal according to a waveform observation position of the signal under measurement. Wherein the delay circuit uses a ramp circuit that outputs a ramp waveform by using the trigger signal as a trigger and a reference clock from a reference clock generation circuit that is input immediately after the trigger signal as a trigger, and outputs the output from the ramp circuit. A delay time detection circuit including a sample hold circuit for holding, a signal corresponding to an integral multiple of the cycle of the reference clock and an output signal from the sample hall circuit are subtracted, and a signal related to a set fine adjustment value is added. And a correction time determining circuit for counting the reference clock up to a predetermined value by using the trigger signal as a trigger. A counter circuit, and a delay correction circuit that delays an output signal from the counter circuit with a signal from the correction time determination circuit using a signal from the correction time determination circuit. An electro-optical sampling oscilloscope. 6. The delay correction circuit includes a ramp circuit that outputs a ramp waveform using an output signal from the counter circuit as a trigger, and a comparison that compares an output from the ramp circuit and an output from the correction time determination circuit. 6. The electro-optic sampling oscilloscope according to claim 1, wherein the electro-optic sampling oscilloscope comprises a circuit.