JP3372467B2 - Electro-optic sampling oscilloscope - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optic sampling oscilloscope.

[0002]

2. Description of the Related Art Recently, for example, an electro-optic sampling oscilloscope capable of measuring without disturbing a circuit under test is used for signal measurement of a circuit under test that handles a signal having an ultra-high bit rate of 2.4 Gbps. Has been.
Here, the electro-optic sampling oscilloscope uses an electro-optic probe that detects the signal under measurement by utilizing the electro-optic effect.

Further, the above-mentioned electro-optical sampling oscilloscope (1) is easy to measure because it does not require a ground line when measuring a signal. (2) The metal pin at the tip of the electro-optical probe is removed from the circuit system. Since they are isolated from each other, a high input impedance can be realized, and as a result, the state of the measured point is hardly disturbed. (3) Since the optical pulse is used, wideband measurement up to GHz order is possible. , It is especially used for the measurement of communication information systems, which are becoming faster.

FIG. 3 is a block diagram showing the configuration of a conventional electro-optic sampling oscilloscope using the above-described measurement principle. The electro-optic sampling oscilloscope shown in this figure comprises a main body 1 and an electro-optic probe 2. The main body 1 is composed of a trigger circuit 3, a timing generation circuit 4, an optical pulse generation circuit 5, an A / D (analog / digital) converter 6, a processing circuit 7, and a setting section 8.

The trigger circuit 3 generates a trigger signal having a frequency set by the setting section 8 based on a trigger signal input from the outside. The timing generation circuit 4 generates the timing of generating the optical pulse and A / D in the A / D converter 6.
A timing signal for timing the D conversion is generated. This timing signal is generated from the desired sample rate, the trigger signal input from the trigger circuit 3, and the clock signal from the internal clock. Here, the sample rate means a rate determined by the processing circuit 7 based on the x-axis scale which is the enlargement factor of the measurement signal in the time direction set by the setting unit 8.

The optical pulse generation circuit 5 generates an optical pulse based on the timing signal generated by the timing generation circuit 4 and supplies it to the electro-optic probe 2.
Then, the optical pulse that has undergone the polarization change is detected by a polarization detection optical system (not shown) in the electro-optic probe 2, and the detection signal as the detection result is amplified and A / D converted by the A / D converter 6. Then, it is input to the processing circuit 7.
Then, the processing circuit 7 performs processing such as displaying the signal under measurement.

[0007]

By the way, in the conventional electro-optic sampling oscilloscope, if the trigger signal is unstable or random, a measurement error occurs that the waveform of the measured signal as the measurement result is disturbed. To do. However, in the conventional electro-optic sampling oscilloscope, from the viewpoint of the measurer, the trigger signal may be unstable or random, causing a measurement error, or the measured signal itself may not be correct. There is a drawback that it is not possible to distinguish whether it is stable and is being measured normally. The present invention has been made under such a background, and an object thereof is to provide an electro-optical sampling oscilloscope capable of notifying a measurement person of a measurement error resulting from an unstable trigger signal. To do.

[0008]

According to a first aspect of the present invention, an electro-optical sampling oscilloscope that measures a signal under measurement by using an optical pulse generated based on a trigger signal is provided at regular intervals. A count means for sequentially counting the number of "1" bits in the trigger signal, a comparison means for comparing two count results of the count means, and a comparison result of the comparison means, the trigger signal is While displaying that it is stable,
Display means for displaying that the trigger signal is unstable and that a measurement error has occurred when the comparison results of the comparison means do not match. The invention according to claim 2 is the electro-optical sampling oscilloscope according to claim 1, wherein the counting means counts "0" bits instead of the "1" bits. According to a third aspect of the present invention, in the electro-optical sampling oscilloscope according to the first or second aspect, first latching means for latching the count result of the counting means at regular intervals, and the first latching means. Second latching means for latching the count result latched by the means at regular intervals, and the comparing means includes two count results latched by the first and second latch means, respectively. It is characterized by comparing.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a main part of an electro-optical sampling oscilloscope according to an embodiment of the present invention. In this figure, 10 is a control unit for generating the synchronization signal Ss shown in FIG. 2A from the above-mentioned internal clock Sck. The cycle of the synchronization signal Ss corresponds to, for example, the cycle of the 8-bit digital signal. The period of the synchronization signal Ss is not limited to 8 bits, and may be any number of bits such as 16 or 32 bits.

Reference numeral 11 denotes the trigger signal St (see FIG. 2).
(See (b)), but in one cycle of the synchronization signal Ss
It is a counter that counts the number of bits at H level, and outputs the count result as count data D. Here, the synchronization signal Ss and the trigger signal St are asynchronous. 12 is the synchronization signal Ss This is a latch circuit that latches the count data D for one cycle in synchronization and counts the latched count data D with the count data Dn +.
Output as 1. A latch circuit 13 latches the count data D for one cycle latched by the latch circuit 12 in synchronization with the synchronization signal Ss, and outputs the latched count data D as count data Dn.

Reference numeral 14 denotes a comparison unit for comparing the count data Dn + 1 and the count data Dn sequentially input from the latch circuit 12 and the latch circuit 13 in synchronization with the synchronization signal Ss. Output as Sc. A display unit 15 displays the comparison result of the comparison unit 14, and is, for example, a lamp, a light emitting diode, a liquid crystal display, or the like.

Next, the operation of the electro-optic sampling oscilloscope according to the above-described embodiment will be described.
At time t0 shown in FIG. 2A, the internal clock Sck
Is input to the control unit 10, the control unit 10 generates the synchronization signal Ss shown in FIG. 2A from the internal clock Sck and outputs it to the counter 11, the latch circuit 12, and the latch circuit 13. .

As a result, the counter 11 is shown in FIG.
The count of the number of bits for which the trigger signal St shown in is at "H" level is started. Then, at time t1 shown in FIG. 2A, the counter 11 indicates that the trigger signal St is "H" in the period T0 from time t0 to time t1.
The result of counting the number of bits is output as count data D. In the example shown in FIG. 2B, the period T0
The bit of the trigger signal St in "1100000"
Since it is "0", the count data D is "2".
The count data D of “2” is latched by the latch circuit 12.

Also, at time t1, the counter 11
Restarts counting the number of bits for which the trigger signal St shown in FIG. 2B is at the "H" level. Then, at time t2 shown in FIG. 2A, the counter 11 is
The count result of the bit for which the trigger signal St is "H" is output as the count data D.

In the example shown in FIG. 2B, the bit of the trigger signal St in the period T1 is the same as "110" in the period T0.
Since it is 00000 ", the count data D is" 2 ".
Is. The count data D of "2" is latched by the latch circuit 12, and the count data D of "2" in the period T0 latched by the latch circuit 12 is latched by the latch circuit 13. This allows
From the latch circuit 12, the count data Dn + 1 of "2" is output.
Is output to the comparison unit 14, and the count data Dn of “2” is output from the latch circuit 13 to the comparison unit 14.

As a result, the comparison section 14 compares the count data Dn ("2") with the count data Dn + 1 ("2"). In this case, since the two match, the comparison unit 14 outputs the comparison result signal Sc indicating the match. As a result, the display unit 15 displays that the trigger signal St is stable, or neither of them is displayed.

Further, at time t2, the counter 11
Restarts counting the number of bits for which the trigger signal St shown in FIG. 2B is at the "H" level. Then, at time t3 shown in FIG. 2 (a), the counter 11 operates in the period T2 from time t2 to time t3.
The count result of the number of bits for which the trigger signal St is "H" is output as count data D.

In the example shown in FIG. 2B, the bit of the trigger signal St in the period T2 is different from that in the period T1 "110".
Since it is 01100 ", the count data D is" 4 ".
Is. The count data D of "4" is latched by the latch circuit 12, and the count data of "2" in the period T1 latched by the latch circuit 12 is latched by the latch circuit 13. As a result, the latch circuit 12 outputs the count data Dn + 1 of “4” to the comparison unit 14, and the latch circuit 13 outputs the count data Dn of “2” to the comparison unit 14.

As a result, the comparison section 14 compares the count data Dn ("2") with the count data Dn + 1 ("4"). In this case, since the two do not match, the comparison unit 14 outputs the comparison result signal Sc indicating that they do not match. As a result, the display unit 15 displays the trigger signal St
Is unstable and that a measurement error has occurred.

As described above, the electro-optic sampling oscilloscope according to the embodiment of the present invention is configured to display on the display unit 15 whether or not the trigger signal St is stable. It is possible to notify the measurer of a measurement error caused by the instability.

Although one embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and design changes within the scope not departing from the gist of the present invention. Even so, it is included in the present invention. For example, in the electro-optical sampling oscilloscope according to the above-described embodiment, an example in which the stability of the trigger signal St is determined by comparing the count data Dn + 1 and the count data Dn has been described, but the present invention is not limited to this. Alternatively, the plurality of count data D may be stored in the memory and the stability of the trigger signal St may be determined by the histogram created based on the plurality of count data D.

That is, in the above histogram,
The horizontal axis represents the count value of bit "1" in one cycle of the synchronization signal Ss, and the vertical axis represents the frequency. Then, when a plurality of points in this histogram are concentrated, it is determined that the trigger signal St is stable, while when the plurality of points are dispersed, the trigger signal St is unsatisfactory. It is judged to be stable.

In the electro-optic sampling oscilloscope according to the above-described embodiment, the trigger signal S
Although the example of counting the number of "1" bits in t has been described, the present invention is not limited to this, and "0" bits may be counted instead of the "1" bits.

In the electro-optic sampling oscilloscope according to the above-described embodiment, the trigger signal is judged to be stable when the count data Dn and the count data Dn + 1 shown in FIG. 1 completely match. However, the criteria are not limited to this example, and the criteria listed below may be used. (B) When the difference between the count data Dn and the count data Dn + 1 is ± 1, it is determined that the trigger signal St is stable. This is in consideration of the error amount due to the deviation of the count timing of the counter 11, which is caused by the non-synchronization of the trigger signal St and the synchronization signal Ss as described above. (B) The difference between the count data Dn and the count data Dn + 1 is within the allowable value of the jitter amount of the trigger signal St (for example,
If it is within 10%), it is determined that the trigger signal St is stable.

[0025]

As described above, according to the present invention, whether the trigger signal is unstable or not is displayed on the display means, so that the measurement error caused by the unstable trigger signal is generated. The effect of being able to notify the measurer is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an electro-optical sampling oscilloscope according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram illustrating an operation of the electro-optical sampling oscilloscope according to the same embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional electro-optical sampling oscilloscope.

[Explanation of symbols]

10 Control unit 11 counter 12 Latch circuit 13 Latch circuit 14 Comparison section 15 Display

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Kikuchi 4-19-7 Kamata, Ota-ku, Tokyo Ando Electric Co., Ltd. (72) Nobuichi Banjo 4-19-7 Kamata, Ota-ku, Tokyo Ando Electric Co., Ltd. (72) Inventor Yoshio Endo 4-19-7 Kamata, Ota-ku, Tokyo Ando Electric Co., Ltd. (72) Inventor Mitsuru Shinagawa 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nihon Telegraph Telephone Company (72) Inventor Tadao Nagatsuma 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Junzo Yamada 3-19-3 Nishishinjuku, Shinjuku-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) Reference JP-A-9-178780 (JP, A) JP-A-6-201803 (JP, A) JP-A-7-43393 (JP, A) JP-A-6- 242152 (JP, A) (58) The field (Int.Cl. ^7, DB name) G01R 13/00 - 13/42

Claims (3)

(57) [Claims] 1. An electro-optical sampling oscilloscope for measuring a signal under measurement by using an optical pulse generated based on a trigger signal, wherein the number of "1" bits in the trigger signal is sequentially set at regular intervals. Counting means for counting, comparing means for comparing two counting results of the counting means, and when the comparison result of the comparing means is coincident, the trigger signal is displayed to be stable, while the comparing means And a display means for displaying that the trigger signal is unstable and that a measurement error has occurred, when the comparison result of 1. is non-coincident. 2. The electro-optical sampling oscilloscope according to claim 1, wherein the counting means counts “0” bits instead of the “1” bits. 3. A first latch means for latching the count result of the count means at regular intervals, and a second latch for latching the count result latched by the first latch means at regular intervals. 3. The electro-optical sampling oscilloscope according to claim 1, further comprising: means for comparing the two count results latched by the first and second latch means, respectively. .