JP3379905B2 - Electro-optic sampling oscilloscope - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric field generated by a signal under measurement, which is coupled to an electro-optic crystal and generates an optical pulse based on a timing signal generated in synchronization with a trigger signal divided by a trigger circuit. Incident on the electro-optic crystal, and is related to the electro-optic sampling oscilloscope that observes the waveform of the signal under measurement depending on the polarization state of the incident optical pulse, and especially converts the trigger signal input from the outside into a pulse train of the target period. The present invention relates to an electro-optical sampling oscilloscope having a trigger circuit.

[0002]

2. Description of the Related Art It is possible to observe the waveform of a signal under measurement by coupling an electric field generated by the signal under measurement with an electro-optic crystal, injecting laser light into the electro-optic crystal, and observing the polarization state of the laser light. Here, pulse the laser light,
When the signal under measurement is sampled, it can be measured with very high time resolution. An electro-optic sampling oscilloscope uses an electro-optic probe that takes advantage of this phenomenon. This electro-optical sampling oscilloscope (hereinafter abbreviated as “EOS oscilloscope”) is compared with a conventional sampling oscilloscope using an electric probe, and 1) does not require a ground line when measuring a signal, so Easy 2) Since the metal pin at the tip of the electro-optic probe is insulated from the circuit system, a high input impedance can be realized, and as a result, the state of the measured point is hardly disturbed 3) Since an optical pulse is used It has attracted attention because it has a feature that it can measure wideband up to GHz order.

Next, the configuration of the EOS oscilloscope is shown in FIG.
Will be explained. The EOS oscilloscope includes an EOS oscilloscope body 1 and an electro-optic probe 2. In FIG. 4, the main body 1 of the EOS oscilloscope includes a timing generation circuit 3, a trigger circuit 4, an optical pulse generation circuit 5, an A / D converter 6, a processing circuit 7, and a setting unit 8.
Composed of.

Here, the trigger circuit 4 generates a trigger down signal Std by dividing the trigger signal Str having an unknown period input from the outside into a target period. Further, the timing generation circuit 3 is configured to detect the optical pulse generation timing and A / D.
A timing signal that is a timing signal for A / D conversion in the converter 6 is generated. The timing signal is generated with the desired sample rate, the trigger down signal Std from the trigger circuit 4, and the clock signal from the internal clock as input signals. Here, the desired sample rate means the sample rate determined by the processing circuit 7 based on the x-axis scale which is the enlargement factor of the measurement signal in the time direction set by the setting unit 8. In addition, the trigger signal S
The frequency division of tr is performed by dividing the trigger signal Str into a cycle close to the cycle of the desired sample rate when the cycle of the trigger signal is shorter than the cycle of the desired sample rate. A timing signal is generated by a trigger down signal Std (referred to as “down”). The optical pulse generation circuit 5 generates an optical pulse based on the signal from the timing generation circuit 3 and supplies it to the electro-optic probe 2. Then, the optical pulse subjected to the polarization change is subjected to polarization detection and the like by a polarization detection optical system (not shown) in the electro-optic probe 2, and the signal is input to the main body 1 of the EOS oscilloscope. This signal is A / D
The converter 6 performs signal amplification and A / D conversion. Then, the A / D converted signal is processed by the processing circuit 7 for displaying the signal to be measured and the like.

FIG. 5 is a diagram showing the trigger circuit 4 in FIG. 4 in more detail. In FIG. 5, reference numeral 41 is a gate circuit for outputting a trigger down signal Std obtained by masking and dividing the frequency of the trigger signal Str.
Is a timer circuit that determines the mask width of the gate circuit 41. Reference numeral 43 is a pulse width shaping circuit which shapes the pulse width of the output pulse of the gate circuit 41 into a required pulse width and outputs the pulse width.

Next, the operation of the prior art shown in FIG. 5 is shown in FIG.
Will be described with reference to. The trigger signal Str is a pulse train with an unknown constant period input from the outside (FIG. 6A).
reference). Here, the trigger signal St input from the outside is used.
It is assumed that the cycle of r is 30 [nS]. Further, it is assumed that the cycle of the desired sample rate is 250 [nS]. First, the timer circuit 42 uses the trigger signal Str as a trigger to set a period (250 [n
S]) and the signal having the same pulse width is inverted and output (FIG. 6).
(See (b)). This signal is a signal for masking the trigger signal Str, and falls almost simultaneously with the rising of the trigger signal Str, rises after 250 [nS], and falls with the rising of the trigger signal Str immediately after this rising. .

The gate circuit 41 outputs a logical product of the trigger signal Str and the inverted mask signal (see FIG. 6 (c)). The pulse width shaping circuit 43 shapes the pulse width of the output of the gate circuit 41 into a required width and outputs it (FIG. 6 (d)).
reference). This signal becomes the trigger down signal Std.
By this operation, the pulse within 250 [nS] from the rising edge of the trigger signal Str is masked and is not output. Therefore, the cycle of the trigger signal Str is 30 [nS], whereas the pulse of the trigger down signal Std is The cycle is
It becomes 270 [nS]. In this way, the trigger circuit 4
Can trigger down to a cycle close to the desired sample rate.

[0008]

However, the cycle of the trigger signal str is 240 [nS] (see FIG. 6 (e)).
In this case, when the trigger signal str is cut out by the output of the timer circuit 42 (see FIG. 6 (f)) which is the inverted pulse width signal of 250 [nS], the output of the gate circuit 41 has a cycle of 480. [NS] (see FIG. 6G), and the cycle of the trigger down signal Std in this case is 48
It becomes 0 [nS] (see FIG. 6 (h)).

In the EOS oscilloscopes shown in FIGS. 4 and 5, this is always desired since the masking is performed with the pulse having the same pulse width as the period of the desired sample rate from the rising of the trigger signal Str of the unknown period. This is because the frequency is divided in a cycle longer than the sample rate. Therefore, depending on the settings of the cycle of the input trigger signal Str and the cycle of the desired sample rate, the cycle may not be close to the cycle of the desired sample rate. Trigger signal St
The period of the trigger down signal Std obtained by triggering r down is preferably close to the period of the desired sample rate. However, in the frequency division according to the related art described above, the period of the desired sample rate is 250 [nS], but the trigger down signal is The cycle of the signal Std becomes 480 [nS], and there is a problem that the frequency is divided into a cycle that is almost double.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an electro-optical sampling oscilloscope capable of accurately generating a trigger down signal having a cycle close to the cycle of a desired sample rate. .

[0011]

In order to achieve the above object, the invention according to claim 1 of the present invention divides a trigger signal input from the outside into a cycle close to a desired sample rate by a trigger circuit. In the electro-optical sampling oscilloscope that outputs a cycled trigger down signal, generates an optical pulse based on a timing signal generated in synchronization with the trigger down signal, and measures the signal under measurement, the trigger circuit is A mask width determination circuit that determines an upper limit value and a lower limit value of the desired sample rate, extracts a pulse of the trigger signal within the range of the upper limit value and the lower limit value, and obtains a mask width based on the period of the extracted pulse. The trigger signal is masked by the mask width determined by the mask width determination circuit, and the trigger signal is divided in frequency. Characterized by comprising a first gate circuit for outputting a down signal.

According to a second aspect of the present invention, the mask width determination circuit sets a period larger than the period of the desired sample rate as an initial value of an upper limit value, and a period smaller than the period of the desired sample rate, A control circuit which is set as an initial value of the lower limit value and which changes and outputs the upper limit value and the lower limit value based on an input counter signal, and a pulse having a width corresponding to the lower limit value, which receives the lower limit value. And a second timer circuit that receives the upper limit value and outputs a pulse having a width corresponding to the upper limit value, and outputs of the first timer circuit and the second timer circuit A second gate circuit for extracting a pulse train of the trigger signal between the upper limit value and the lower limit value,
A counter for counting the number of pulses of the pulse train extracted in the second gate circuit and outputting the result to the control circuit.

According to a third aspect of the present invention, when the count value of the counter is 0 (zero), the control circuit increases the upper limit value and the lower limit value to gradually increase the upper limit value. If a value and a lower limit value are set and the count value is 2 or more, the upper limit value and the lower limit value are set so as to gradually narrow the interval between the upper limit value and the lower limit value, and the count value is It is characterized in that the above setting is repeated until it becomes 1.

According to a fourth aspect of the present invention, in the control circuit, the count value of the counter is 0 (zero), and even if the interval between the upper limit value and the lower limit value is expanded to a limit value, the counter count is increased. When the value is 0 (zero), the upper limit value and the lower limit value are not set.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An electro-optical sampling oscilloscope according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a diagram showing a configuration example of the EOS oscilloscope. As mentioned above, the EOS oscilloscope
OS oscilloscope body 1 and electro-optic probe 2
It is composed of The main body 1 of the EOS oscilloscope includes a trigger circuit 4, a timing generation circuit 3, an optical pulse generation circuit 5, an A / D converter 6, a processing circuit 7, and a setting unit 8.
It is composed of The outline of the operation of the EOS oscilloscope is as described above, and the description thereof will be omitted. And
The trigger circuit 4, which is a feature of the present invention, will be described in detail below.

FIG. 1 shows an EOS according to an embodiment of the present invention.
It is a figure which shows the structure of the trigger circuit 4 of an oscilloscope.
In FIG. 1, reference numeral 41a denotes a trigger signal Str that masks a trigger signal Str input from the outside.
It is a gate circuit that divides the frequency. Reference numeral 4a is a mask width determination circuit that determines the mask width when masking the trigger signal Str, and includes a gate circuit 41b, timer circuits 42a and 42b, a counter 44, and a control circuit 45. The gate circuit 41b uses the trigger signal St
It is a circuit for approximating the cycle of the trigger down signal Std obtained by dividing r to the cycle of the desired sample rate. The timer circuit 42a is a timer circuit that determines the lower limit value of the mask width, and the timer circuit 42b is a timer circuit that determines the upper limit value of the mask width. The counter 44 is the gate circuit 4
The pulses of the trigger signal str masked by 1b are counted. The control circuit 45 is a control circuit that controls the timer circuits 42a and 42b to change the mask width until the count value of the counter 44 becomes "1". Reference numeral 43 is a pulse width shaping circuit for shaping the pulse width into a required pulse width. The output of the pulse width shaping circuit 43 becomes the trigger down signal Std.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG.
Will be explained. Here, the cycle of the trigger signal Str input from the outside is 30 [nS] (FIG. 2A).
Refer to). First, the operation of obtaining the width of the mask will be described. The control circuit 45 obtains the upper limit value and the lower limit value of the cycle of the desired sample rate based on the desired sample rate input from the processing circuit 7. For example, for the upper limit value and the lower limit value, + 10% of the cycle of the desired sample rate is the upper limit value, and -10% is the lower limit value. At this time, when the cycle of the desired sample rate is 250 [nS], the upper limit value is 275 [nS] and the lower limit value is 225 [nS].
Becomes Next, the control circuit 45 outputs the obtained lower limit value to the timer circuit 42a and the timer circuit 4a.
The obtained upper limit value is output for 2b. Timer circuit 4
2a triggers the output of the gate circuit 41a and outputs a pulse having a pulse width corresponding to the input lower limit value (see FIG. 2B). This waveform rises almost at the same time as the output of the gate circuit 41a, and falls after a time (225 [nS]) corresponding to the lower limit value. 2 (a)
(B) shows the correspondence with the trigger signal Str selected by the gate circuit 41a.

Next, the timer circuit 42b is connected to the timer circuit 4
At the same time when the output of 2a rises, it rises and outputs a pulse having a pulse width corresponding to the upper limit value (see FIG. 2C). Similar to the timer circuit 42a, this waveform rises almost at the same time as the trigger signal Str and falls after a time corresponding to the upper limit value (275 [nS]).

Next, the gate circuit 41b is connected to the timer circuit 42.
A signal that becomes "H" (high) (see FIG. 2D) is generated internally only between the fall of the output of a and the fall of the output of the timer circuit 42b, and this signal and the trigger signal S
The logical product with tr is output (see FIG. 2 (e)). The output of this logical product means that the pulse train of the trigger signal Str within the range of ± 10% of the period of the desired sample rate is taken out, and this pulse train is output to the counter 44.

Next, the counter 44 counts the rising edge of the pulse of the input pulse train and outputs it to the control circuit 45. Here, the control circuit 45 determines whether or not the count value of the counter 44 is “1”. If the count value is “2” or more, the upper limit value and the lower limit value obtained from the desired sample rate are set to the timer circuit. The interval between the fall of the output of 42a and the fall of the output of the timer circuit 42b is changed to be narrow (see FIGS. 2F and 2G). That is,
The lower limit value is made larger than the value set at this time, and the upper limit value is made smaller than the value set at this time. The upper limit value and the lower limit value are changed step by step depending on the resolution of the hardware configuring the control circuit 45. Then, based on the changed upper and lower limits,
Fall of output of timer circuit 42a and timer circuit 42
A signal which becomes "H" (high) only during the falling edge of the output of b (internal signal of the gate circuit 41b, see FIG. 2 (h))
The pulse of the trigger signal Str is cut out by
(See (i)). In this way, the operation of changing the upper limit value and the lower limit value is repeated until the count value of the counter 44 becomes "1". By this operation, the lower limit pulse width is 22
5 + T1 [nS] (see FIG. 2 (f)), and the upper limit pulse width is 275-T2 [nS] (see FIG. 2 (g)).
Becomes The pulse width of this lower limit value becomes the mask width for masking the trigger signal Str.

Next, the operation of dividing the frequency of the trigger signal Str by using the mask width obtained by the above-mentioned processing will be described. First, when the count value of the counter 44 becomes "1", the gate circuit 41a inverts the output of the timer circuit 42a and outputs a logical product of the inverted signal and the trigger signal Str (FIG. 2). (See (j)).
This output has a period of 240 [nS], and this output is shaped into a required pulse width by the pulse width shaping circuit 43 and output. This output (not shown) becomes the trigger down signal Std, and its cycle becomes 240 [nS]. Further, the count value of the counter 44 is equal to or more than “2”, and while the upper limit value and the lower limit value are changed, the gate circuit 41 can be operated until the count value of the counter 44 becomes “1”.
As for the output of a, since the pulse masked by the lower limit value at that time is output, the trigger down signal Std does not become undefined or not output.

Further, the period of the desired sample rate ± 10
When the count value of the counter 44 is “0” at the time when the upper limit value and the lower limit value are set to%, the control circuit 45
The difference between the upper limit value and the lower limit value is gradually increased until the count value becomes “1”. That is, the upper limit value and the lower limit value are changed so that the interval between the fall of the output of the timer circuit 42a and the fall of the output of the timer circuit 42b becomes large. When the counter value of the counter 44 is “0” and the difference between the upper limit value and the lower limit value is to be increased, a limit value to be increased is determined and increased to that value. Even if the difference between the upper limit value and the lower limit value is increased to the limit value, if the count value of the counter 44 is “0”, the cycle of the trigger signal Str is much larger than the cycle of the desired sample rate. In this case, the upper limit and lower limit are not set. As a result, the output of the timer circuit 42a is always "L" (low), and as a result, the trigger signal Str becomes the trigger down signal Std as it is. Alternatively, if the period of the desired sample rate can be changed, the process of changing the desired sample rate is performed.

Next, referring to FIG. 3, the trigger signal Str
The operation when the cycle is 240 [nS] (see FIG. 2A) will be described. The desired sample rate is
It is set to 250 [nS] as in the above-mentioned example. First, the timer circuit 42a has a pulse width of 225 [n
S] pulse is output (see FIG. 3B). On the other hand, the timer circuit 42b has a pulse width of 275 [n
S] pulse is output (see FIG. 3C). Next, between the lower limit value and the upper limit value (the output of the gate circuit 41b is "H")
(High), the trigger signal Str of FIG.
Count the number of rising pulses. At this point, the number of rising edges of the pulse is “1” (FIG. 3).
Therefore, the upper limit value and the lower limit value are not changed.
The gate circuit 41a inverts the output of the timer circuit 42a at this time (see FIG. 3 (f)), and outputs the logical product of this output and the trigger signal Str (see FIG. 3 (g)). The pulse width shaping circuit 43 shapes the output pulse of the gate circuit 41a into a required pulse width and outputs it (see FIG. 3 (h)). This output becomes the trigger down signal Std,
A pulse is output at a cycle of 0 [nS]. in this way,
In the conventional technique, the trigger is down to the cycle of 480 [nS], but in the present embodiment, the trigger can be down to the cycle of 240 [nS] close to the cycle of the desired sample rate of 250 [nS].

As described above, the width for masking the trigger signal Str is ± 1 of the cycle of the desired sample rate.
By setting the range to 0%, gradually narrowing this range, and extracting the pulses in this range, the trigger signal Str can be triggered down to a cycle close to the cycle of the desired sample rate. The range of the upper limit value and the lower limit value obtained from the cycle of the desired sample rate (± 10% in the above example) may be determined based on the range in which the EOS oscilloscope operates accurately with respect to the desired sample rate.

[0025]

As described above, according to the invention described in claim 1, the range between the upper limit value and the lower limit value of the cycle of the desired sample rate is set, and the frequency is divided into cycles within this range. Since this is done, it is possible to obtain an effect that the frequency can be divided into a cycle close to the cycle of the desired sample rate. Also,
According to the second aspect of the present invention, since a simple circuit is used as the mask width determination circuit, the effect that the trigger circuit can be configured by only a simple circuit is obtained. Further, claim 3
According to the invention described in (1), even when the frequency cannot be divided into the cycle between the set upper limit value and the lower limit value, it is possible to obtain the effect that the frequency can be divided into the cycle closest to the cycle of the desired sample rate. To be Further, according to the invention described in claim 4, when the trigger signal is input such that the setting of the upper limit value and the lower limit value exceeds the hardware limit value, the trigger signal itself is used as the trigger down signal. Therefore, it is possible to prevent the trigger down signal from becoming undefined or being not output.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a trigger circuit in an EOS oscilloscope according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation timing of the trigger circuit in the embodiment shown in FIG.

FIG. 3 is a timing chart showing the timing of another operation of the trigger circuit in the embodiment shown in FIG.

FIG. 4 is a block diagram showing a configuration of an EOS oscilloscope.

FIG. 5 is a block diagram showing a configuration of a conventional example of a trigger circuit in an EOS oscilloscope.

FIG. 6 is a timing chart showing the timing of the conventional trigger circuit shown in FIG.

[Explanation of symbols]

1 ... Main body of EOS oscilloscope, 2 ... Electro-optical probe, 3 ... Timing generation circuit, 4 ... Trigger circuit, 4a ... Mask width determination circuit, 41a, 41
b ... Gate circuit, 42a, 42b ... Timer circuit, 43 ... Pulse width shaping circuit, 44 ... Counter, 45 ... Control circuit, 5 ... Optical pulse generation circuit,
6 ... A / D converter, 7 ... processing circuit, 8 ... setting unit.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Kikuchi 4-19-7 Kamata, Ota-ku, Tokyo Within Ando Electric Co., Ltd. (72) Nobuichi Banjo 4-19-7 Kamata, Ota-ku, Tokyo Ando Electric Co., Ltd. (72) Inventor Yoshio Endo 4-19-7 Kamata, Ota-ku, Tokyo Ando Electric Co., Ltd. (72) Inventor Mitsuru Shinagawa 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nihon Telegraph Telephone Co., Ltd. (72) Inventor Tadao Nagatsuma 3-19-3 Nishishinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Junzo Yamada 3-19-3 Nishishinjuku, Shinjuku-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) Reference JP-A-9-54119 (JP, A) JP-A-6-167515 (JP, A) JP-A-63-191966 (JP, A) JP-A-55- 130232 (JP, A) -220144 (JP, A) JP flat 5-273247 (JP, A) (58 ) investigated the field (Int.Cl. ^7, DB name) G01R 13/00 - 13/42

Claims (4)

(57) [Claims] 1. A trigger down signal obtained by dividing a trigger signal input from the outside into a period close to a desired sample rate by a trigger circuit, and based on a timing signal generated in synchronization with the trigger down signal. In an electro-optical sampling oscilloscope that generates an optical pulse and measures a signal under measurement, the trigger circuit defines an upper limit value and a lower limit value of the desired sample rate, and the trigger within the range of the upper limit value and the lower limit value. A mask width determination circuit that extracts a pulse of a signal and obtains a mask width based on the period of the extracted pulse; and a mask width determined by the mask width determination circuit, masks the trigger signal, and the trigger signal A first gate circuit that outputs the trigger-down signal obtained by dividing Pulling oscilloscope. 2. The mask width determination circuit sets a cycle larger than the cycle of the desired sample rate as an initial value of an upper limit value, and sets a cycle smaller than the cycle of the desired sample rate as an initial value of a lower limit value. And a control circuit that changes and outputs the upper limit value and the lower limit value based on the input counter signal, and a first timer that receives the lower limit value and outputs a pulse having a width corresponding to the lower limit value. A circuit, a second timer circuit that receives the upper limit value and outputs a pulse having a width corresponding to the upper limit value, and the upper limit value based on the outputs of the first timer circuit and the second timer circuit. And a second gate circuit for extracting a pulse train of the trigger signal between the lower limit value and the lower limit value, counting the number of pulses of the pulse train extracted in the second gate circuit, Electro-optic sampling oscilloscope according to claim 1, characterized in that it comprises a counter for outputting to the control circuit. 3. The control circuit, when the count value of the counter is 0 (zero), sets the upper limit value and the lower limit value so as to gradually widen the interval between the upper limit value and the lower limit value. , The count value is 2
If it is above, set the upper limit and the lower limit to gradually narrow the interval between the upper limit and the lower limit,
The electro-optic sampling oscilloscope according to claim 2, wherein the setting is repeated until the count value becomes 1. 4. The count value of the counter is 0 (zero), and the count value of the counter is 0 (zero) even if the interval between the upper limit value and the lower limit value is expanded to a limit value. The electro-optical sampling oscilloscope according to claim 3, wherein if there is, the upper limit value and the lower limit value are not set.