JP3404383B2 - Memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION Integrated circuit buses for computers and video devices that enable high speed transfer of data blocks, especially to and from memory devices, consume less power, and have higher system reliability. Describe the interface. It also describes new ways to implement the bus architecture.

[0002]

BACKGROUND OF THE INVENTION Semiconductor computer memory is conventionally designed and configured to use one memory device for each bit, or small group of bits, of any individual computer word. The word size depends on the choice of computer. Typical word sizes range from 4 to 64 bits. Each memory device is connected in parallel to a series of address lines and to one of a series of data buses. When the computer asks to read from and write to a particular memory location, the address is placed on the address line, and some of the memory devices are used with a separate device select line for each device needed. Or all are activated. One or more devices can be connected to each data line, but typically only a few data lines are connected to one memory device. Thus, data line 0 is connected to device 0, data line 1 is connected to device 1, and so on.
Thus, data is accessed or provided in parallel for each read or write operation of the memory. In order for the system to work properly, every single memory bit in every memory must be guaranteed to work properly.

To understand the concept of the present invention, it is helpful to study the architecture of conventional memory devices. Almost any type of memory device (the most widely used dynamic random access memory (D
RAM), static RAM (SRAM), and read-only memory (ROM) devices), many bits are accessed in parallel each time the system performs a memory cycle. However, each time the memory device is cycled, only a small portion of the accessed bits that are available internally cross the boundaries of the memory device to the outside world.

Referring to FIG. 1, recent DRAM and SRA
All M and ROM designs have an internal architecture with row (word) lines 5 and column (bit) lines 6 so that the memory cells can fill the two-dimensional area 1. When a particular word line is enabled, all of the corresponding data bits are transferred to the bit line. Conventional DRAM
Some utilize this organization to reduce the number of pins required to send an address. The address of a given memory cell is divided into two addresses, a row and a column. Each of these two addresses can be multiplexed on a bus with half the bandwidth required by conventional memory cell addresses.

<Comparison with Prior Art> The conventional memory device has attempted to solve the problem that not all accesses succeed when the memory is accessed at high speed. U.S. Pat. No. 3,821,715 (Hoff et al.) To Intel Corp. for the first 4-bit microprocessor.
ration). That patent describes a bus that connects one central processing unit (CPU) to multiple RAMs and ROMs. The bus multiplexes addresses and data on a 4-bit wide bus and uses point-to-point control signals to select specific RAMs and ROMs. The access time is fixed and only one processing element is allowed.
There is no block mode type operation and, most importantly, not all interface signals between devices are sent through the bus (ROM and RAM control lines and R
AM selection line is between the two points).

In US Pat. No. 4,315,308 (Jackson), one CPU is
Describes the bus that connects to the interface. The invention uses multiplexed addresses, data and control information over one 16-bit wide bus.
Block mode operation is defined. A block of that length is sent as part of the control sequence. Also, a variable access time operation using a "stretch" cycle signal is performed. It lacks a large number of processing elements, is not adaptable to a large number of outstanding requirements, and again, not all interface signals are sent by the bus.

US Pat. No. 4,449,207 (Kung et al.) Describes a DRAM that multiplexes addresses and data on an internal bus. The external interface to this DRAM is conventional and has separate connections for control, address and data.

US Pat. Nos. 4,764,846 and 4,706,166 (Go) show stacked die 3D with connections along one edge.
The package structure is described. These packages are difficult to use due to the point-to-point wiring required to interconnect conventional memory devices to the processing unit. The two patents extend complex techniques to solve those problems. No attempt has been made to solve the problem by changing the interface.

US Pat. No. 3,969,706 (Proebsting et al.) Describes a state-of-the-art DRAM interface. Addresses are bidirectionally multiplexed and have separate pins for data and control (RAS, CAS, WE, C
S). The number of pins increases with the size of the DRAM, and in memory devices using such DRAMs many of the connections must be made between two points.

There are many backplanes in the prior art, but none have the combinations or features of the invention described. Many backplane buses are 1
Address and data are multiplexed on one bus (for example, NU bus). ELSXI and other split-transaction buses (US Pat. Nos. 4,595,923 and 4,481,625 (Roberts
s))) was realized. ELSXI also realized a relatively low voltage swing current mode ECL driver (about 1V swing). Address-space registers are implemented on most backplane buses, as are certain modes of block mode operation.

Although almost all backplane buses implement certain arbitration schemes, the arbitration schemes disclosed herein differ from each of them. US Pat. No. 4,837,682 (Culler),
No. 4,818,985 No. 4 (Ikeda), No. 4,779,
No. 089 (Theus), No. 4,745
No. 548 (Blahut) describes a conventional scheme. All log N additional signals, where N is the number of potential bus requesters, (Chias (Theu
s), Blahut), or additional delay to control the bus (Ikeda, Cull).
er)). None of the buses described in those patents or other documents use bus connections alone. All include some point-to-point connections on the backplane. None of the other aspects of the invention, such as fetching each data block from one device, or small, low cost 3D packaging, apply to the backplane bus.

The clocking scheme used with the present invention in this specification has not previously been used, and in fact it is not possible to implement it on a backplane bus due to the signal degradation caused by connector stubs. Have difficulty. U.S. Pat. No. 4,247,817 (Heller) describes a clocking scheme that uses two clock lines, but in contrast to the normal rise time signal used herein. It uses a ramp-shaped clock signal.

US Pat. No. 4,646,279 (Voss) describes a video RAM which implements a parallel load and serial output shift register at the output of the DRAM. This generally allows for significantly higher bandwidth (and doubles the width of the shift-out shift-out path).
Extended twice more than that). The rest of the interface to DRAM (RAS, CAS, multiplexed addresses, etc.) remains the same as for conventional DRAM.

[0014]

SUMMARY OF THE INVENTION It is an object of the present invention to provide high speed data in a efficient and cost effective manner for large blocks of data from one memory device by an external user, such as a microprocessor. The use of a new bus interface built into the semiconductor device to support access.

Another object of the present invention is to provide an interface circuit that alleviates a clock distribution problem including clock skew.

[0016]

According to the present invention, there is provided a synchronous memory device having an array of memory cells, the memory device having the following configuration. That is, the clock receiver circuit for receiving an external clock signal having a fixed frequency, the input receiver circuit including a plurality of input receivers for extracting a read operation request in synchronization with the external clock signal, A delay locked loop circuit coupled to the receiver circuit for outputting data in synchronization with the external clock signal, the output circuit including a plurality of output drivers for transferring the data to an external bus during a read operation. An output drive circuit for outputting to the output drive circuit, the output drive circuit including a plurality of output drivers for outputting a first portion of data in response to a rising edge of the external clock signal, and a second portion of the data. And a plurality of output drivers that output according to the falling edge of the external clock signal. Details of such a memory device will be described in the following embodiments, particularly in paragraphs 0022 to 0030 and 0040.
~ 0044, 0086 ~ 0088, 0095 ~ 0103
And the figures relating to them. This memory device can alleviate the clock distribution problem.

The specification comprises at least two semiconductor devices including at least one memory device connected in parallel to a bus, the bus comprising the address, data and control required by said memory device. It includes a plurality of bus lines for carrying almost all of the information, the control information includes device selection information, the bus has bus lines well less than the number of bits in an address, and the buses are individual devices. A memory subsystem is disclosed that conveys device selection information without the need for a separate device selection line directly connected to. The memory subsystem has a standard DRAM, as shown in FIG.
13,14, ROM (or SRAM) 12, microprocessor CPU 11, I / O devices, disk controllers, or other specialized devices such as high speed switches, commonly used for point-to-point and The devices are modified to use a fully bus-based interface rather than a bus-based wiring combination. The new bus includes clock signals, power and multiplexed addresses, data signals and control signals. In the preferred implementation, eight bus data lines and AddressValid bus lines carry addresses, data, and control information to memory addresses up to 40 bits wide. Sixteen bus data lines or another number of bus data lines may be used to implement the teachings of the present invention. New buses are used to connect elements such as memory, peripherals, switches, and processing units.

It is also indicated that DRAMs and other memory devices receive addresses and other information over the bus and send or receive the required data over the same bus. Each memory device contains only one bus interface and no other signal pins. Other devices that can be included in the device can be connected to the bus and other non-bus lines such as input / output lines. The bus supports large data block transfers and split transactions, allowing the user to achieve high bus utilization.

The DRAM connected to this bus differs from conventional DRAM in several ways. Registers are provided that can store other information appropriate to the chip, such as control information, device identification, device type, and address range for each independent part of the device. Since new bus interfaces must be added and the internals of conventional DRAM devices need not be modified, they can pass data to and from the bus at the peak data rate of the bus. This requires modification of the column access circuitry in the DRAM, where die size increase is minimal. A circuit is provided to generate a low skew internal device clock for devices on the bus, and a circuit is provided to provide another demultiplexing input signal and a multiplexing output signal.

The bus has a very high clock speed (hundreds of MH
Wide bus bandwidth is achieved by operating in z). This high clock speed is enabled by the restricted environment of the bus. Bus lines are impedance controlled and doubly terminated lines. At a clock speed of 500 MHz, the longest bus transit time is less than 1 ns (typical bus length is about 10 cm). Also, due to the packaging used, the pin pitch can be very close to the pad pitch. The loading from the individual devices to the bus is very small. In the preferred implementation, this increases the stub capacity by 1-2p.
Generally, F and inductance can be set to 0.52 nH. Each device 15, 16, 17 shown in FIG. 3 has pins on only one side, which pins are directly connected to the bus 18. A transceiver device 19 may be included to interface a number of devices to higher order buses via pins 20.

The main result of the architecture disclosed in this specification is to increase the bandwidth of DRAM access. The present invention reduces manufacturing and manufacturing costs,
The goal is to reduce power consumption and increase packing density and system reliability.

[0022]

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a high speed, multiple bus for communication between a processor and a storage device, and contributes to providing a device for use in the bus system. The present invention can also be used to connect processing devices to other devices such as I / O interfaces and disk controllers. A bus consists of a relatively small number of lines connected in parallel to each device on the bus, and the bus allows virtually all the addresses and data that a device needs to communicate with other devices on the bus. , Carry control information. In many systems using the present invention, the bus carries almost all signals between all devices in the entire system. Device selection information for each device on the bus is carried on the bus and does not require a separate device selection line. Also, address and data information can be sent over the same line, eliminating the need for separate address and data lines. Using the mechanism described here, very large addresses (40 bits in the example) and large blocks of data (10
24 bytes for a small number of bus lines (8 plus 1 in the embodiment)
Control line).

Virtually all signals required by a computer system can be bussed. Those skilled in the art will appreciate that a particular device, such as a CPU, can be connected to other signal lines besides the bus of the present invention and to a separate bus, such as a bus to a separate cache memory. Specific devices, such as crosspoint switches, can be connected to multiple independent buses of the present invention. In this embodiment, a memory device having no connection other than the bus connection described here is provided, and a CPU using the bus of the present invention as a main connection to the memory and other devices on the bus, if not entirely, is used. Set up.

All modern DRAMs, SRAMs, ROMs
The design has an internal architecture of row (word) and column (bit) lines to efficiently tile the two-dimensional region. In FIG. 1, each word line 5 and bit line 6
1-bit data is stored at the intersection of. When a particular word line becomes available, all corresponding data bits are transferred to the bit line. This data, which is about 4000 bits at a time in a 4 Mbit DRAM, is then loaded into the column amplifier (sense amplifier) 3 and held for use in the I / O circuit.

The invention presented here allows data from the sense amplifier to be loaded 32 bits at a time on an internal device bus operating at approximately 125 MHz.
This internal device bus moves data around the device and the data is multiplexed onto an 8-bit wide external bus interface operating at about 500 MHz.

In the bus architecture of the present invention, the CP
U, master (bus controller) such as direct memory access unit (DMA) or floating point unit (FPU), and DR
Connect slave devices such as AM, SRAM, ROM storage devices. The slave device responds to the control signal and the master sends the control signal. Those skilled in the art will appreciate that some devices sometimes operate as masters and slaves, depending on the mode of operation and the state of the system. For example, a storage device generally has only a slave function, but D
MA controller, disk controller, CPU is slave,
It may have both master functions. Many other semiconductor devices, including other special purpose devices such as I / O devices, disk controllers and high speed switches, can be modified for use with the buses of the present invention.

Each semiconductor device has a device identification (device I
D) Contains a set of internal registers, including registers, device type description registers, control registers, and other registers containing information related to device type. In an embodiment, a semiconductor device connected to the bus has a set of 1's indicating a register for specifying a memory address included in the device and a time until (or should) the device can transmit or receive data. It has a built-in access time register that stores one or more delay times.

Most of these registers can be modified or set as part of the initialization sequence that occurs when the system is booted or reset.
During the initialization sequence, each device on the bus is assigned a unique device ID number stored in the device ID register. The bus master then accesses using those device ID numbers to access the access time register, control register,
The system can be configured by setting appropriate registers in other devices, including memory registers. Each slave can have one or several access time registers (4 in the preferred embodiment). In one embodiment, one access time register is permanently or semi-permanently programmed with a constant value in each slave to facilitate certain control functions. A preferred embodiment of the initialization sequence is detailed below.

All information sent between the master and slave devices is sent, for example, through an 8-bit wide external bus. This is because a master device, such as a microprocessor, gains exclusive control of the external bus (ie becomes the bus master) and sends request packets (a sequence of bytes of address and control information) to one or more slaves on the bus. This is done by defining a protocol that sends to the device to initiate the transaction. In the teachings of the present invention, an address can consist of 16 to 40 bits or more. Each slave on the bus decodes the request packet to see if it needs to respond to that packet. The slave to which the packet is sent then initiates the internal processes required to perform the requested bus transaction on demand. The requesting master may also need to perform certain internal processes before the bus transaction begins. After the designated access time, the slave responds by returning one or more bytes (8 bits) of data or storing the information obtained from the bus. One or more access times can be provided so that different types of responses can result at different times.

The request packet and its corresponding bus access are separated by a selected number of bus cycles, and the same or another master makes an additional request or a simple bus access. To be able to use the bus at. Therefore, multiple independent accesses are possible, maximizing bus utilization and transferring short data blocks. When transferring a long data block, the overhead due to bus address, control, and access time is small compared to the total time of requesting and transferring the block, so that the bus can be used efficiently without duplication.

<Device Address Mapping> Another unique aspect of the present invention is that each storage device has all the functions of the memory board of a conventional backplane bus computer system, and has independent memory subs. It is a system. Each storage device can be a single storage part or subdivided into two or more separate storage parts. The memory device includes a memory address register for each separate memory portion. A failed storage device (or even a small portion of the device) can be "recorded" with the loss of a small small portion of memory, effectively maintaining the functionality of the entire system. Recording a failed device can be done in two ways, both compatible with the present invention.

In a preferred first method, an address register within each storage device (or an independent separate portion thereof) is used to store information defining the range of bus addresses to which the storage device responds. This is similar to the conventional method used in the memory board of the conventional backplane bus system. The address register typically contains one pointer to a block of known size, or one pointer and a constant or variable block size value, or one at the beginning of each memory block and the other at the end. (Ie "upper" and "lower")
Two pointers to can be included. By properly setting the address register, a series of functional memory devices or distributed memory parts can be made to respond to a contiguous address range, and system access can be performed in contiguous blocks of memory. (Mostly limited by the number of good devices connected to the bus).
Since a range of addresses can be assigned to the memory blocks in the first memory device or memory part, the memory block of the next memory device or memory part is one higher than the last address of the previous block ( It is possible to assign addresses starting with the address (or lower in the memory structure).

The preferred device for use in the present invention includes device type register information that specifies the chip type, including how much memory the device has and how it is configured. The master performs appropriate memory tests by reading and writing each memory cell in one or more select orders to test the proper function of each accessible isolation portion of the memory (partially I
The address value (4 in the preferred embodiment) is stored in the address space register of the device based on information such as the D number and device type.
Up to 0 bit, 10 ¹² bytes) can be continuously written. Non-functional or damaged storage parts can be assigned special address values which can be interpreted to avoid the system from using its memory.

The second method is to impose a burden on the system master or the master to avoid a defective device.
CPUs and DMA controllers typically have some address translation buffer (TLB) that maps from virtual to physical (bus) addresses. The TLB can be programmed with relatively simple software to use only the working memory (the data structure describing the working memory can be easily generated). For masters that do not have a TLB built-in (eg, an image display generator), a small and simple RAM can be used to map a contiguous range of addresses to the addresses in the functional storage.

Both methods work, so that the system can continue to operate with a significant amount of non-functional devices on the remaining memory. The system constructed in accordance with the present invention is meant to have much improved reliability over existing systems, including the ability to build a system with few field failures.

Bus: The preferred bus architecture of the present invention is 11 signals (ie BusData "0: 7", AddrVal).
id, Clk1, Clk2) as well as an input reference level and a power supply, ground line connected in parallel to each device. Signals are placed on the bus during normal bus cycles.
The notation “signal [i: j]” refers to a specific range of a signal or line, for example BusData [0: 7] is
BusData0, BusData1, ... BusD
It means ata7. BusData "0: 7"
The bus lines for signals form a byte-wide multiplexed data or address or control bus. AddrValid indicates when the bus holds a valid address request, decodes the bus data as an address to the slave, and handles the pending request if the address is contained in that slave. Command. Both clocks provide a synchronized high speed clock for all devices on the bus. In addition to the signals on the bus, one other line (ResetIn) is used to connect each device in series to assign a unique device ID number to every device in the system during initialization.
ResetOut) (detailed later).

Bus cycles are grouped into even or odd cycle pairs in order to allow a very high data rate of this external bus compared to the gate delay of the internal logic. It should be noted that all devices connected to the bus use the same even or odd label of the bus cycle and start operation on even cycles. This is done by the clocking method.

Protocols and Bus Operations The bus uses a relatively simple, synchronous, split transaction block-oriented protocol for bus transactions. One purpose of this system is to keep the centralized intelligence on the master, thus keeping the slaves as simple as possible (since there are generally more slaves than masters). To reduce slave complexity,
The slave should be able to fully initiate or complete internal stages of the device, including internal activities that must occur prior to the subsequent bus access stage, so that the slave can respond to requests at specified times. The time of this bus access phase is known to all devices on the bus, and each master is responsible for ensuring that the bus is free when bus access begins. Therefore, slaves never worry about bus arbitration. This approach eliminates arbitration in a single master system and simplifies the slave bus interface.

In the preferred embodiment of the invention, to initiate a bus transfer to the bus, the master sends out a series of consecutive byte request packets containing address and control information. It is desirable to use request packets that contain an even number of bytes, and each packet should start with an even bus cycle.

The device selection function is handled by using the bus data line. For all slaves, decode the request packet address, determine whether it contains the request address,
If it contains, Ad that commands the data block transfer to return data to the master (for read request) or to accept data from the master (for write request)
Drive drValid. The master can also select a specific device by transmitting the device ID number in a request packet. The preferred embodiment indicates that all devices on the bus should interpret the packet by choosing a special device ID number. This allows the master to broadcast messages and, for example, set the selection control registers of all devices to the same value.

The data block transfer is started at an even cycle at the time designated by the request packet control information. If the device has started a specific function such as memory address setting before the start of the bus access stage, it will start the data block transfer almost immediately during the internal stage of the device. The time for loading the data block on the bus line is selected from the value stored in the access time register of the slave. The data timings for reading and writing are the same.
The only difference is which device drives the bus. For reading, the slave drives the bus, the master receives the value from the bus, for writing, the master drives the bus, and the selected slave receives the value from the bus.

In the embodiment of the invention shown in FIG. 4, the request packet 22 contains 6 bytes of data, ie 4.5 address bytes and 1.5 control bytes. Each request is a 9-bit multiplexed data / address line (AddrValid2) for all 6 bytes of the request packet.
3 + BusData [0: 7] 24) is used. Setting an AddrValid = 1 of 23 in an even cycle (otherwise unused) would result in a request packet (control information)
Shows the start of. Add in the validity request packet
rValid27 (last byte) must be 0. Asserting this signal on the last byte will invalidate the request packet. This is used in the collision detection arbitration logic (detailed below). Byte 25-26
Is the first 35 address bits (address [0: 3
5]) is included. The last byte is AddrVal
id27 (invalidation switch), remaining address bits (address [36:39]), block size [0:
3] (control information) 28 is included.

The first byte is AccessTy, which is an operation code that specifies the type of access, for example.
Mas at a position reserved for the master sending the packet to include pe [0: 3] and its master ID number
It contains two 4-bit fields containing control information for ter [0: 3]. Master numbers 1 to 15 are possible, master number 0 is reserved for special system commands. Packets with Master [0: 3] = 0 are invalidation special packets and are treated as such.

The access type field specifies whether the requested operation is a read or a write, and the type of access is a control of a register or other part of the device, such as memory. In the preferred embodiment, AccessType [0] is a read / write switch, and if it is 1, the operation requests a read from the slave (the slave reads the requested memory block and puts the memory contents on the bus) and 0.
Then the operation requires a write to the slave (the slave reads the data from the bus and writes it to memory). AccessType [1: 3] provides up to 8 different access types for slaves, and Ac
accessType [1: 2] indicates the timing of the response stored in AccessRegN of the access time register. Access time register selection can be direct selection or pre-selected access time by getting the specific opcode that registers it (see table below).
It can be indirectly selected by obtaining the slave corresponding to the selected operation code with.
The remaining bits, AccessType [3], can be used to send additional information to the slave about the request.

One special type of access is control register access, which requires addressing the selected register of the selected slave. In the preferred implementation of the invention, AccessType [1: equal to zero.
3] indicates the control register request, and the address field of the packet indicates the desired control register. For example, the most significant 2 bytes are the device ID number (indicating which slave is addressed), the lower 3 bytes can specify the register address, and indicate or include the data to load into its control register. be able to. The control register address is used to initialize the access time register, so (for example, access register 0
It is desirable to use a programmable or hardwired fixed response time that is within (AccessReg0), preferably 8 cycles. Control register access can also be used to initialize or modify other registers, including address registers.

The method of the present invention is particularly provided with access mode control of DRAM. One such access mode is page mode or normal RAS access.
Determine if it is an access. In normal mode (conventional DRAM and the present invention), the DRAM column amplifier (or latch) is precharged (or precharged) to an intermediate value between logic 0 and 1. This precharge allows access to the rows in the RAM as soon as either an input (write) or output (read) access request is received, allowing the column amplifier to sense the data quickly. In page mode (both conventional and invention), the DRAM holds data from previous read or write operations in column amplifiers or latches. If subsequent requests to access the data are directed to the same row, the DRAM does not have to wait for the data to be sensed (it has already been sensed) and the access time for this data is less than the normal access time. Is also much shorter. Page mode generally allows much faster access to data, but blocks of data are smaller (data equal to the number of amplifiers). However, if the requested data is not in the selected row, the request must wait for the RAM to be precharged before initiating the normal mode access, so the access time will be longer than the normal access time. The two access time registers of each DRAM contain the access times used in normal mode and page mode access, respectively.

The access mode also determines whether the DRAM should precharge the amplifier or save the amplifier contents for later page mode access. The general setting is "precharge after normal access"
However, although it is “save after page mode access”, “precharge after page mode access” or “save after normal access” is also a selectable operation mode. The DRAM can also be set to precharge the amplifier if it is not accessed within the selected time period.

In page mode, the data stored in the DRAM amplifier can be accessed in much less time than it takes to read the data in normal mode (10-20 nanoseconds vs 40-100 nanoseconds). Seconds).
This data can be retained for long term use. However, if those amplifiers (and thus the bit lines) are not precharged after the access, subsequent accesses to different memory words (rows) will be about 40 times because the amplifiers must be precharged before latching to the new value. A -100 nanosecond precharge time penalty will be imposed.

The contents of the amplifier (sense amplifier) can be held in this way and used as a cache, and small data blocks can be accessed quickly and repeatedly. DRAM-based page mode caches have been tried in the prior art using conventional DRAM mechanisms,
Not very efficient as each computer requires several chips. Such conventional page mode caches contain many bits (eg 32 chips x 4).
It has almost no K-bit) independent storage item (entry). In other words, at any given time, the amplifier holds only a few different blocks or memory "local areas" (4K in the example above).
A single block of words). Simulations have shown that 100 or more blocks are required to achieve a high hit rate (90% or more requests can find the requested data in cache memory) regardless of the size of each block. As an example, "Analytic Cache Model" by Anant Agarwal et al., "ACM Transactions on Computer Systems," 7 (2), pp. 1
84-215 (May 1989).

By the mechanism of the memory of the present invention, each DR
The AM can hold one to more than one (4 for 4 Mbit DRAM) separately addressed independent data blocks. 100 such DRAMs
Personal computers or workstations (i.e., 400 blocks or fields) are very high and highly repetitive compared to low (50-80%) variably hit rates using conventionally configured DRAMs. Possible hit rates (average 98-99%) can be achieved. Furthermore, because of the time penalty associated with deferring precharge due to page mode cache "misses," traditional DRAM-based page mode caches have generally been found to perform less well than without any cache. .

For DRAM slave access, the access type is generally used as follows. Access type Application Access time [1: 3] ――――――――――――――――――――――――――――――――――― 0 Control register access Fixed , 8 [access register 0] 1 unused fixed, 8 [access register 0] 2-3 unused access register 1 4-5 page mode DRAM access access register 2 6-7 normal DRAM access access register 3

For those skilled in the art, the sequence of available bits is
It will be appreciated that they can be designated as switches that control their access modes. For example, AccessType [2] = page mode / normal switch AccessType [3] = precharge / data storage switch

The block size [0: 3] specifies the transfer size of the data block. Block size [0]
Is 0, the remaining bits are the block size (0-7)
Is a binary display of. If the block size [0] is 1, the remaining bits give the block size as a binary power of 2 from 8 to 1024. Zero-length blocks are
For example, it can be interpreted as a special command for reproducing the DRAM without bringing data or changing the DRAM from the page mode to the normal access mode and vice versa. Block size [0: 2] Number of bytes in block ―――――――――――――――――――――――――― 0-7 Respectively 0-7 8 8 9 16 10 32 11 64 12 128 13 256 56 14 512 15 1024 One of ordinary skill in the art will appreciate that other block size encoding schemes or values may be used.

In most cases, the slave responds to the selected access time by reading data from the bus through the bus line bus data [0: 7] or writing data to the bus, and AddrValid will be a logical zero. . In the preferred embodiment, effectively 1 for each memory access.
Only one storage device is needed, ie one block will be read from or written to one storage device.

Retry Format In some cases the slave may not be able to correctly respond to a request, eg a read or write request. In such a situation, the slave will sometimes receive N (o) ACK (nowle
dge) or an error message called a retry message. The retry message can include information about the conditions that require a retry, but this will increase system requirements for both slave and master circuits. Simple messages that only indicate that an error has occurred allow for less complex slaves, and the master can take the necessary steps to understand the cause of the error and correct it.

Under certain conditions, for example, a slave may not be able to supply the requested data. During page mode access, the selected DRAM must be in page mode and the requested address must match the address of the data held in the amplifier or latch. Each DRAM can check this match during page mode access. If no match is found, DR
The AM begins precharging and sends a retry message back to the master during the first cycle of the data block (the rest of the replied block is ignored). The master then waits for the precharge time (which is set to correspond to the type of slave in question stored in the precharge register of the special register) and then requests the normal DRAM access (access type = 6 or Send again as 7).

In a preferred form of the invention, by driving AddrValid to be true at exactly the time the slave was supposed to begin reading or writing data,
The slave notifies the retry. The master, which was expecting to write to the slave, is adding AddVal during writing.
You must monitor the id and take the necessary corrective action if a retry message is detected. FIG. 5 illustrates the format of the retry message 28. This is useful for read requests, the first (even) cycle is 23 AddrValid = 1 and Master
It consists of [0: 3] = 0. AddrValid is 0 for normal data block transfer, and master 0
Note that there is no (only 1 to 15 possible).
All DRAMs and masters can easily understand such packets as invalidation request packets and thus retry messages. In this type of bus transaction, although the contents are undefined in the above embodiment, Master [0: 3] and AddrValid23
All fields except can be used as information fields. Those skilled in the art will appreciate that another way to indicate a retry message is to add a data invalid line and signal to the bus. This signal can be asserted in case of NACK.

<Bus Arbitration> In the case of a single master, the arbitration problem does not occur by definition. The master sends a request packet and keeps track of how long the bus is busy in response to the packet. The master can schedule multiple requests so that the corresponding data block transfers do not overlap.

The bus architecture of the present invention is also useful in multiple master configurations. When two or more masters are on the same bus, each master must keep track of all outstanding transactions, so when each master sends a request packet and sends it to the corresponding data block transfer. I know if I can access it. However, it may happen that two or more masters must send request packets at about the same time, detect multiple requests, and resort to some bus arbitration.

There are many ways for each master to record when the bus is busy. The easy way is
Each master, for example, (one indicating the closest future point when the bus will be busy and the other the future future point when the bus will be free, ie the end of the most recent incomplete data block transfer) Maintaining the two pointers is to maintain the bus busy data structure. Using this information, each master has enough time to send a request packet (under the protocol described above) before it is busy with another data block transfer, and when. And whether the corresponding data block transfer interferes with the pending bus transaction. Therefore, each master must read all request packets and update its bus busy data structure to maintain information about when the bus is free.

When more than one master is on the bus, the masters often send independent request packets during the same bus cycle. These multiple requests collide when each such master simultaneously drives the bus with different information, resulting in chaotic request information and the desired data block transfer does not occur. In the preferred form of the invention, a logical 1
To the bus data or AddValid line, each device on the bus drives that line with a current greater than or equal to the high logic value of the system. However, the device does not drive a line with a logic zero. That is, the lines are simply maintained at the voltage corresponding to the low logic value. Each master has at least some or all of the bus data and Add.
Because it tests the voltage on the rValid line, the master does not drive on a given bus cycle, but it can detect a logic "1" on the lines driven by other masters even though the expected level is "0".

Another way to detect collisions is to select one or more bus lines for collision notification. Each requesting master drives its line and monitors for above normal drive currents (or ">1" logic values) indicating requests by one or more masters. Those skilled in the art will appreciate that this can be done by protocols including BusData and AddrValid lines, or by using additional bus lines.

In the preferred form of the invention, each master detects collisions by monitoring the lines it does not drive to see if another master is driving them. In FIG. 4, the first byte of the request packet contains the number of each master attempting to use the bus (Master [0: 3]). When two masters send packet requests starting at the same point in time, the master number is logically "OR'ed" with them so that one or both of the masters monitor the data on the bus, Collisions can be detected by comparing with what they have sent. For example, when the requests by the master numbers 2 (0010) and 5 (0101) collide, the bus is Master [0: 3] = 7.
It is driven by the value of (0010 + 0101 = 0111).
Master number 5 detects that the signal Master [2] = 1 and master 2 has Master [1] and Mas [1].
Detecting that ter [3] = 1, both masters will know that a collision has occurred. Another example is Masters 2 and 11,
On the other hand, the bus has Master [0: 3] = 11 (00
10 + 1011 = 1011), the master 11 cannot easily detect this collision, but the master 2 can. If a collision is detected, each master detecting the collision will add byte 5 AddrVa of request packet 22.
It drives the value of lid27 to 1, which is detected by all masters, including master 11 in the second example above, and forces the following bus arbitration cycle.

Another collision condition is that master A sends a request packet in cycle 0 and master B tries to send a request packet beginning with cycle 2 of the first request packet, thereby overlapping the first request packet. This may happen in some cases. This is because the bus operates at high speed, so the logic in the second starting master detects the request initiated in cycle 0 by the first master fast enough,
It often occurs because it delays its own demands and cannot react quickly. Master B finally realizes that it shouldn't have sent the request packet (and thus almost certainly destroys the address Master A was trying to send), but like the simultaneous collision above, Drive 1 on AddrValid in byte 5 of request packet 27 of 1 to force arbitration. The logic in the preferred embodiment is fast enough that the master will detect request packets by other masters by cycle 3 of the first request packet, so that any master will receive request packets that may collide after cycle 2. Not likely to send.

The slave device does not have to detect the collision directly, but must wait until the last byte (byte 5) has been read to make sure the packet is valid to avoid doing anything unrecoverable. I have to. Request packets with Master [0: 3] equal to 0 (retry signal) are ignored and do not cause a collision. Subsequent bytes are also ignored in such packets.

To initiate arbitration after a collision, wait a preselected number of cycles (4 cycles in the preferred embodiment) after the abandoned request packet, and use the next free cycle for bus arbitration (in the preferred embodiment). Use the next available even cycle). Each colliding master is sending a request packet to all other colliding masters, each colliding master has been assigned a priority, and each master has its request at that priority. Notify that you can do it.

FIG. 6 illustrates one preferred method of performing this arbitration. Each conflicting master announces its intent to send a request packet by driving the single bus data line during the single bus cycle corresponding to its assigned master number (1-15 in this example). In the 2-byte arbitration cycle 29, byte 0 is assigned to request 1-7 from master 1-7 (bit 0 is unused) and byte 1 is assigned to request 8-15 from master 8-15. . At least one device and each conflicting master read its value on the bus during the arbitration cycle to determine and store which master wants to use the bus. Those skilled in the art will appreciate that a single byte can be allocated for an arbitration request if the system contains more bus lines than the master.

The fixed priority method (using the master number, first selecting the lowest number) is then used to determine the priority,
Order the requests in a bus arbitration queue maintained by at least one device. These requests are queued by the master of each bus busy data structure and are not allowed until the bus arbitration queue is cleared. One of ordinary skill in the art will appreciate that other priority schemes can be used, starting with assigning priorities according to the physical location of each master.

System Configuration / Reset In the bus-based system of the present invention, each device on the bus is unique under the conditions (after power-up or otherwise) desired or required by the system. A mechanism for providing a device identifier (device ID) is provided.
The master can then use this device ID to access the particular device, and in particular to set and modify the registers of the particular device, including the control registers and address registers. In one embodiment, one master is designated to perform the entire system configuration process. The master is a set of unique device IDs for each device connected to the bus system.
Give a number. In the preferred embodiment, each device connected to the bus contains a special device type register that identifies the device type, eg, CPU, 4 Mbit memory, 64 Mbit memory or disk controller. The configuration master checks each device, determines the device type, sets the appropriate control registers including access time registers, checks each storage device, and sets all appropriate memory address registers. .

One means of setting a unique device ID number is to have each device select the device ID number in turn and store that value in an internal device ID register. For example, the master may hand each device in the sequence a serial device ID number through a shift register or hand a token from device to device so that the device with the token may read device ID information from another line. You can In an embodiment, device ID numbers are assigned to devices according to physical relationships, such as order along the bus.

In the preferred embodiment of the present invention, the device ID setting is a reset input (ResetI) of a pair of pins on each device.
n) and reset output (ResetOut). These pins handle normal logic signals and are used only during device ID configuration. On each rising edge of the clock, each device replicates the reset input (input) into a four stage reset shift register. The output of the reset shift register is connected to the reset output, which in turn is connected to the reset input of the next sequentially connected device. Virtually all devices on the bus are thereby daisy chained together. For example, the first reset signal may cause the device to clear all internal registers, eg, clear all internal registers, while the reset input at a device is at a logical one or when the select bit of the reset shift register goes from zero to non-zero. Hard reset by resetting. A second reset signal (which is the falling edge of the reset input) in combination with a changeable value on the external bus causes the device to latch the contents of the external bus into the internal device ID register (Device [0: 7]). Let

To reset all devices on a bus, the master must set the reset input line of the first device to "1" long enough to reset all devices on the bus. (Set the time to the number of devices taking 4 cycles-the maximum number of devices on the desired bus configuration is 25)
6 (8 bits), so 1024 cycles are always sufficient time to reset the entire device). The reset input is then dropped to "0" and the BusData line is driven with the first and subsequent device ID numbers, which change every four cycle pulses. Subsequent devices set their ID number in the corresponding device ID register as the falling edge of the reset input propagates through the shift register of the daisy chain device. FIG. 14 shows the reset input of the first device going low when the master drives the first device ID to the bus data line bus data [0: 3]. The first device then latches its first device ID. After 4 clock cycles, the master outputs the bus data [0:
3] to the next device ID, the reset output of the first device goes low, which causes the reset input of the next daisy chain device to go low, and the next device sends the next device ID number to the bus data [0: 3] to enable latching. In one embodiment, one master is assigned device ID 0 and it is that master's responsibility to control the reset input line and bus drive subsequent device ID numbers at the appropriate times. In the preferred embodiment, each device waits two clock cycles after the reset input goes low before latching the device ID number from the bus data [0: 3].

Those skilled in the art will appreciate that a long ID number can be distributed to the devices by having each device read multiple bytes from the bus and have the value latched in the device ID register. Those skilled in the art will also appreciate that there are other ways to get a device ID number for a unique device. For example, a series of serial numbers can be clocked along the reset input line to instruct each device at a particular time to latch the current reset shift register value into the device ID register.

The configuration master selects and sets the access time in each access time register in each slave for a period long enough to allow the slave to make the actual desired memory access. For example, normal DRA
For M accesses, this time must be longer than the row address strobe (RAS) access time. If this condition is not met, the slave will not be able to transmit accurate data. The value stored in the slave's access time register should be half the number of bus cycles the slave device should wait before using the bus in response to a request. An access time value of "1" thereby indicates that the slave should not access the bus until at least two cycles after the last byte of the request packet has been received. The value of the access register 0 is fixed to 8 (cycle) to facilitate access to the control register.

More than one master device can be included in the bus architecture of the present invention. The reset or initialization sequence also includes determining if there are multiple masters on the bus, and if so, a unique master ID for each.
Try to assign a number. Those skilled in the art will appreciate that there are many ways to do this. For example, the master polls each device, determines, for example, what device it is by reading the special register, and writes the next available master ID number to the special register for each master device. be able to.

<ECC> Error detection and correction ([ECC
C]) method can be implemented in this system. E
CC information is generally calculated for a block of data when the block of data is first written to memory. Data block is usually defined binary size (eg: 2
56 bits) and the ECC information uses significantly fewer bits. Each conventional binary data block is typically stored with the addition of ECC bits, creating the potential problem of producing a block size that is not a defined binary power.

In an embodiment of the invention, ECC information is stored separately from the corresponding data, which in turn is stored in blocks having a defined binary size. The ECC information and corresponding data can be stored in separate DRAM devices, for example. The data can be read without ECC using a single request packet, but to write or read the error correction data, two request packets are used, one for the data and the other for the corresponding ECC information. I need. ECC information is not always stored permanently, and in some cases ECC information can be obtained without sending request packets or without bus data block transfers.

In an embodiment, a standard data block size can be selected for use with the ECC and the ECC method determines the required number of bits of information in the corresponding ECC block. Program the RAM containing ECC information to be equal to (1) the time to access the standard data block plus the access time to the normal RAM (including data) minus the time to send the request packet (6 bytes). The access time or (2) the access time equal to the access time of the normal RAM minus the time to access the standard ECC block minus the time to send the request packet can be stored. The master simply reads the EC to read the ECC block that corresponds to the data block.
A request for that data is issued immediately after the request for the C block. The ECC / RAM waits for the selected access time, and transfers that data (in the case of (1) above) to data R
Immediately after the AM ejects the data block, the bus is placed on the bus. Those skilled in the art will understand that the access time described in the case of (2) above can be used to load the ECC before the data is loaded on the bus line, and the data write is explained for the read. It will be appreciated that the method can be done analogously. Also those paired E
Understand the bus busy structure and the adjustments that must be made in the request packet arbitration method to meet CC requirements.

The flexibility of this system allows the system designer to select the size of the data block and the number of ECC bits using the storage device of the present invention. Note that the data stream on the bus can be interpreted in various ways. For example, the sequence is 2 ^m E
2 ⁿ data bytes followed by CC bytes (or vice versa), or sequence is 8 data bytes plus 1E
It can also be 2 ^k iterations of CC bytes. Other information, such as the information used by directory-based cache coherence schemes, can also be managed in this way. For example, Anant Agarwal et al., "Canonicalizable Directory Scheme for Cache Consistency," 1st
5th International Computer Architecture Symposium,
1988 pp. See 280-289. One of ordinary skill in the art will appreciate other ways of implementing ECC within the teachings of the present invention.

<Low Power Supply 3-D Packaging> Another major advantage of the present invention is that it significantly reduces the power consumption of the storage system. Almost all of the power consumed in a conventional DRAM is lost during row (row) access. By using a single row access in a single RAM to supply all bits for a block request (compared to row access in each of the multiple RAMs of a conventional storage system), the power per bit is Can be very small. Since the power lost by the storage device using the present invention is significantly reduced, it may be possible to place the device closer than in conventional designs.

The bus architecture of the present invention enables innovative 3-D packaging techniques. By using a narrowly multiplexed (temporally shared) bus, the pin count for any large storage device can be kept very small at the 20 pin level. Furthermore, this pin count is DRAM
The density can be kept constant from one generation to the next.
The low dissipation of power allows the pin pitch (the space between the IC pins) to be narrowed to make each package smaller. With current surface mount technology that supports pin pitches as low as 20 mils, all off-device connections can be made at one end of the storage device. Semiconductor dies useful in the present invention have connections or pads along one end of the die and can be routed or otherwise connected to package pins with wires of similar length.
This geometry allows for very short leads with an effective lead length of 4 mm or less in some cases. Further, the present invention uses only bused interconnects, with each pad on each device being connected by a bus to a corresponding pad on another device.

The use of low pin counts and end connection buses allows for a simple 3-D package, which allows devices to be stacked and the buses to be connected along one end of the stack. You can The fact that all signals are on the bus is important for implementing a simple 3-D structure. Without this, the complexity of the "backplane" would be too difficult to be cost effective with current technology. The individual devices in the stack of the present invention can be very tightly packed due to the low power dissipation of the entire storage system, allowing the devices to be stacked side-by-side or one above the other. Conventional plastic injection molding small outline (SO) package is about 2.5 mm (100 mil)
, But the final limit is the device die thickness, which is 0.2- using current wafer technology.
Small size level of 0.5 mm.

<Electrical description of the bus> By using a device that is very power consuming and physically closely packed, the bus can be made very short, which in turn allows for short propagation times and high data rates. become. The bus of an embodiment of the present invention consists of a set of resistive termination controlled impedance transmission circuits capable of operating up to a data rate of 500 MHz (2 nanosecond cycle). The characteristics of the transmission line are strongly influenced by the load caused by the DRAM (or other slave) attached to the bus. These devices add lumped capacity to the line that lowers the impedance of the line and reduces the transmission rate. In the loaded environment, the bus impedance is on the order of 25 ohms,
Propagation speed is about c / 4 (c = speed of light) to 7.5 cm /
It is often ns. To operate at a 2 ns data rate, transit time on the bus should be less than 1 ns, leaving 1 ns for setting and holding time of input receivers (described below) and clock drift (skew). Should be. Therefore, the bus line should be very short, about 8 cm or less for maximum performance. Low performance systems can have much longer lines, eg a 4 ns bus can have a 24 cm line (3 ns transit time, 1 ns setting, hold time).

In the embodiment, the bus is the same as described above (paragraph 006).
It is driven by current as in 1) and uses a current driver (exciter). Each output must be capable of sinking 50 mA resulting in an output swing of about 500 mV or more. In the preferred embodiment of the invention, the bus is active low. The non-asserted state (high value) is considered a logical zero, so the asserted value (low state) is a logical one. Those skilled in the art will appreciate that the method of the present invention can also be implemented with opposite logical relationships to voltage. The value of the deasserted state is set by the voltage across the terminating resistor and should be high enough to allow the output to operate as a current source with as little as possible to reduce power dissipation. These constraints result in a termination voltage of about 2V above ground in the preferred implementation. With the current source driver, the output voltage is proportional to the sum of the power supplies driving (exciting) the bus.

In FIG. 7, the two devices are driving the bus at the same time and are not in a stable state, but because of the propagation delay on the wire, device B42 (already asserting a logic 1 on the bus) still drives the bus. During this time, a situation may arise in which device A41 can start driving its bus portion 44. In a system with a current source driver, the values at points 44 and 45 are a logical one when B42 is driving the bus (prior to time 46). When B42 is switched off at the time point 46 when A41 is switched on, the voltage at the output point 44 of A41 temporarily falls below the normal value due to the additional drive by A41. The voltage returns to its normal value at time 47 when the effect of turning off B42 is detected. The voltage at time point 45 becomes a logic 0 when device B42 is turned off and device A4
It falls at time 47 when the effect of turning on one is detected. The value on the bus is 1 because the logic 1 driven by the current from device A41 propagates regardless of the previous value on the bus.
It is reliably settled after a number of flight (t _f ) delays (ie the time it takes for the signal to propagate from one end of the bus to the other). When using voltage excitation (as in ECL wiring OR (wired-or)), a logical 1 on the bus (from device B42 previously driven) is emitted by device A41 and the furthest away from the system. Part (eg device 4)
The transition detected by 3) is blocked until after one flight delay after the turn-off waveform from device B42 arrives at device A41, resulting in a worst case settling time of twice the flight delay time.

<Clocking> Accurately clocking a high-speed bus without causing an error due to propagation delay causes each device to monitor two bus clock signals and becomes a true system clock. Can be done internally. A mechanism may be provided to send the bus clock information on one or two lines so that each bus-connected device produces a zero skew internal device clock with respect to all other device clocks. In the preferred embodiment of FIG. 8, bus clock generator 50 at one end of the bus propagates the preceding bus clock signal in one direction along the bus, eg, on line 53 from left to right to the far end of the bus. The same clock signal is then sent through a direct connection to the second line 54 and propagates from right to left returning along the bus from the far end to the starting point as a late arrival bus clock signal. A single bus clock line can also be used if it remains unterminated at the far end of the bus, and the leading bus clock signal can be reflected along the same line as the terminating bus clock signal. .

FIG. 8b shows that the two bus clock signals received by each device 51, 52 at different times (due to the propagation delay along the wire) have a constant intermediate value along the bus between the two bus clocks. This is an example of having a time point. In each of the devices 51 and 52, the clock 1 (53)
The rising edge 56 of the clock 2 (54) comes after the rising edge 55 of. Similarly, the falling edge 57 of the clock 1 (53) is followed by the falling edge 58 of the clock 2 (54).
Is coming. This waveform relationship is found in all other devices on the bus. Devices closer to the clock generator may take longer clock 1 than devices farther from the generator because the clock pulses take longer to travel through the bus and back along line 54.
Although the separation between clock and clock 2 is large, the corresponding intermediate time points 59, 60 between the rising and falling edges of any device are of equal length on each clock line between the far end of the bus and that device. So it is fixed. Each device must extract two bus clocks and generate its own device clock (internal clock) at the midpoint between the two.

The clock distribution problem is that the bus clock and device clock speed equal to the bus cycle data rate divided by 2 (ie, bus clock period is 2 bus cycle periods).
It can be further reduced by using Therefore, the 500 MHz bus should use a 250 MHz clock rate. This reduction in frequency offers two advantages. First, all signals on the bus will have the same worst case data rate (500M
The data on the Hz bus can only be changed every 2ns). Second, by clocking at half the bus cycle data rate, for example, defining an even cycle as one when the internal device clock is 0 and an odd cycle as one when the internal device clock is 1, And even bus cycle labeling can be eliminated.

<Multiple Bus> The above bus length limitation limits the total number of devices that can be placed on a single bus. With a 2.5 mm space between the devices, a single 8 cm bath holds about 32 devices. One of ordinary skill in the art will appreciate the particular application of the present invention where the overall data rate on the bus is adequate but requires much more equipment (more than 32) for storage or processing. Larger systems use one or more memory subsystems (generally 32 or near the maximum possible with a bus design, a primary of two or more devices connected to a transceiver device) using the teachings of the present invention. It can be easily constructed by using a bus unit).

In FIG. 9, each primary bus unit can be mounted on a single circuit board 66, sometimes referred to as a memory stick. Each transceiver device 19 also connects to a transceiver bus 65 that is electrically and otherwise similar or identical to the primary bus 18 described above. In the preferred embodiment, there is no transceiver delay between masters because all masters are on the transceiver bus, and all storage is on the primary bus unit so that all memory accesses experience equivalent transceiver delays. Those skilled in the art will understand how to implement a system in which the master is on one or more bus units and the storage is on the transceiver bus as well as the primary bus unit. In general, the teachings of each of the inventions described with respect to storage devices can be implemented with one or more storage devices and transceiver devices on an attached primary bus unit. Other devices, generically referred to as peripherals, including disk controllers, video controllers, and I / O devices, can be attached to the transceiver bus or primary bus unit as desired. Those skilled in the art will understand how to use a single primary bus unit or multiple primary bus units as required by a transceiver bus in a particular system design.

The transceiver is functionally very simple. They detect request packets on the transceiver bus and send them to their primary bus unit. If the request packet requires a write to a device on the transceiver's primary bus unit, that transceiver keeps a record of the access time and block size and takes all data from the transceiver bus during that time. Send to. The transceiver also monitors its primary bus unit and sends any data that exits it to the transceiver bus. The high speed of the bus means that the transceiver must be pipelined, requiring an additional delay of one or two cycles to pass data through the transceiver in either direction. It is necessary to increase the access time stored in the master on the transceiver bus to account for transceiver delay,
The access time stored in the slave on the primary bus unit should not be changed.

Those skilled in the art will appreciate that more sophisticated transceivers can control transmissions to and from the primary bus unit. The additional control line TrncvrRW sets the line to Ad
The information on the data line for all devices on the transceiver bus when used with the drValid line is 1) request packet, 2) valid data to slave, 3) valid data from slave, or 4) invalid data ( Or play bus)
Can be bussed to all devices on the transceiver bus. By using this additional control line, the transceiver does not have to keep track of when data needs to be sent from its primary bus to the transceiver bus, and whenever the control signal indicates condition 2) above Transceivers send all data from their primary bus to the transceiver bus. In the preferred embodiment of the present invention, AddrValid and Trnc
If both vrRW are low, there is no bus activity and the transceiver remains idle. The controller sending the request packet drives AddValid high, indicating to all devices on the transceiver bus that each transceiver is sending a request packet to be sent to its primary bus unit. Each controller attempting to write to the slave has AddrValid and Trncvr
Drive both RW high to indicate that valid data for the slave is on the data line. Each transceiver device then transmits all the data from the transceiver bus line to its respective primary bus unit. Controllers expecting to receive information from slaves also
Drives the rncvrRW line high, but AddrVali
d should not be driven, thereby indicating to each transceiver to send data coming from the slave to its primary local bus to the transceiver bus. More advanced transceivers understand signals destined for or coming from their primary bus unit and only send signals on demand.

FIG. 9 shows an example of physical installation of the transceiver. One important feature of this physical structure is that the bus of each transceiver 19 is a DRAM or other device 15, 16, 17 on the primary bus unit 66.
Is to integrate with the original bus of. The transceiver 19 has pins on two sides and is mounted flat on the primary bus unit with the pins of the first set connected to the primary bus 18. The second set of transceiver pins 20 are at right angles to the first set of pins and are oriented to attach transceiver 19 to transceiver bus 65 much like DRAMs are attached to the primary bus unit. Transceiver buses can generally be flat and at different planes at right angles to the plane of each primary bus unit. The transceiver bus can also be generally circular and mounted tangentially perpendicular to the primary bus unit.

By using this two-level method, 50
A system including zero or more slaves (16 buses of 32 DRAMs each) can be easily constructed. Those skilled in the art will understand that the above device ID scheme can be modified to accommodate more than 256 devices, for example by using a long device ID or using an additional register to hold a portion of the device ID. Extending this scheme to three dimensions, transceiver bus units are arranged in parallel and on each,
Multiple transceiver buses can be connected by placing the corresponding signal lines on the bus through the appropriate transceivers.
Next you can build a transceiver bus. With such a secondary transceiver bus, thousands of slave devices can be effectively connected to a single bus.

<< Device Interface >> The device interface to the high speed bus can be divided into three main parts. The first part is the electrical interface. This part includes the input receiver, bus driver, and clock generation circuit. The second part includes an address comparison circuit and a timing register. This part receives the incoming request packet, determines if the request is for that device, and if so, initiates an internal access and sends the data to the pin at the correct time. Lastly, the portion for memory devices such as DRAM is a DRAM column access path. This part is the conventional DR
DR a bandwidth larger than the bandwidth given by AM
It needs to be fed to and taken out from the AM amplifier. The implementation of the electrical interface and DRAM column access path is described in more detail in the following sections. Those skilled in the art will understand how to modify conventional address compare circuits and conventional register circuits to implement the present invention.

<Electrical Interface-I / O Circuit> FIG. 10 shows a block diagram of a desirable I / O circuit for address / data / control lines. This circuit is especially
Although suitable for use with M devices, those skilled in the art could use or modify it for use with other devices connected to the bus of the present invention. It includes a set of input receivers 71, 72, an output driver 76 connected to the input / output line 69 and pad 75, an internal clock 73 and a complementary signal 74 of the internal clock. The clocked input receiver takes advantage of the synchronous nature of the bus. To further relax the performance requirements of the device input receiver, each device pin, and thus each bus line, is clocked in two to extract even cycle inputs on the one hand and odd cycle inputs on the other hand. Connected to the receiver. By pin demultiplexing (demultiplexing) the input 70 in this way, each clocked amplifier (input receiver) is given a complete 2 ns cycle to fully accommodate the bus low voltage swing signal. Amplify to value CMOS logic signal. Those skilled in the art will appreciate that additional clocked input receivers can be used within the teachings of the present invention. For example, four input receivers can be connected to each device pin and clocked by a modified internal device clock to transfer bits sequentially from the bus to the internal device circuitry, with faster external bus speeds or longer settling times for bus low voltage. All values of shake signal CM
It can be amplified to an OS logic signal.

The output driver is very simple and has a single NMO
It consists of an S pull-down transistor 76. This transistor is also sized to sink 50 mA required by the bus under worst case conditions. For 0.8 micron CMOS technology, the transistors need to be about 200 microns long. Overall bus performance can be improved by using a feedback technique to control the output transistor current so that the current through the device is approximately 50 mA under all operating conditions (although this is a suitable bus). Not absolutely necessary for operation). One example of many methods known to those skilled in the art for using feedback techniques to control current is given in Hans Schumacher et al. Solid State Circuit, Volume 25 (1), pp.150-154 (1990 1990)
Month). Controlling this current improves performance and reduces power dissipation. This output driver, which can operate at 500 MHz, is also controlled by a suitable multiplexer with two or more (preferably 4) inputs connected to other internal chip circuitry (all of which are well known in the prior art). Can be designed according to).

The input receivers of all slaves must be able to operate during every cycle to determine if the signal on the bus is a valid request packet. This requirement leads to some constraints on the input circuit. In addition to requiring small acquisition and decomposition delays, the circuit must acquire very little or no DC power and very little AC power and re-inject very little current into the input or reference line. Standard clocking DRAM shown in FIG.
The amplifier meets all these requirements except the need for constant input current. As this amplifier goes from detection to extraction, the capacitances of internal nodes 83 and 84 of FIG. 11 are discharged through reference line 68 and input 69, respectively. Although this particular current is small, the sum of such currents in the reference line from all inputs summed for all devices can be quite large.

The fact that the sign of the current depends on the previously received data exacerbates the problem. One way to solve this problem is to divide the extraction period into two stages. During the first stage, the inputs are shorted to a buffered version of the reference level (which will have an offset).
During the second stage, connect the input to the true input. In this scheme, the input must still charge nodes 83, 84 from the reference value to the current input value, so the input current is not completely removed, but the total charge required is reduced by a factor of about 10 (2. Only a 0.25V change is needed, not a 5V change). Those skilled in the art will appreciate that many more methods can be used to provide a clocking amplifier that operates at very low input currents.

One important part of the I / O circuit generates the internal device clock based on the leading and trailing bus clocks. Controlling clock skew (difference in clock timing between devices) is important in a system running at 2 ns cycle, so that the internal device clock is generated so that the input sampling circuit and the output driver are between the two bus clocks. Try to operate as close to time as possible in the middle.

A block diagram of the internal device clock generation circuit is shown in FIG. 12, and a corresponding timing diagram is shown in FIG.
The basic idea behind this circuit is relatively simple. The DC swing amplifier 102 is used to convert the small swing bus clock into a full swing CMOS signal. This signal is then supplied to the variable delay line 103. The output of the delay line 103 is 3
One of the additional delay circuit, i.e. a 104 with a fixed delay (t _0), the same fixed delay and (t ₀₎ and 105 having a second variable delay (X), the same fixed delay (t ₀₎ and the second
Is provided to 106 having half the variable delay (X / 2) of. The outputs 107 and 108 of the delay lines 104 and 105 are connected to the leading and trailing bus clock inputs 100 and 110, respectively.
Clocked input receiver (receiver) connected to
01 and 111 are driven. Those input receivers 10
1, 111 has the same design as the receiver described above and shown in FIG. The variable delay lines 103, 105 are adjusted through the feedback lines 116, 115 so that the receivers 101, 111 extract the bus clock at their transitions. In the delay lines 103 and 105, the trailing edge 120 of the output 107 is the clock 1 (53) of the preceding bus clock.
At the falling edge 121 of (the input sampling circuit 101
It is adjusted to precede by a time 128 (equal to the delay in). Similarly, in the delay line 105, the trailing edge 122 is the trailing edge 123 of the clock 2 (54) of the last arrival bus clock.
Is adjusted so that it is preceded by the delay 128 of the input sampling circuit 111.

Outputs 107 and 108 are synchronized with the two bus clocks, and finally output 73 of delay line 106 is output 1
Since the output 73 is in the middle between 07 and 108, that is, the output 73 is at the output 107 and the output 73 is at the time 12 before the output 108.
Since it follows by the same amount of time as 9, output 73 becomes the internal device clock (ie internal clock) intermediate the bus clock. Falling of internal device clock 73 124
Precedes the actual input sampling 125 time by a delay of one sample operation. In this circuit configuration, the output 10
By adjusting 7, 108, the bus clock is the input receiver 10
1,111 is extracted at the transition of the bus clock, so that substantially all device input receivers 71 and 72 (see FIG.
0) delay can be automatically balanced.

In the embodiment, on the other hand, the internal device clock 73
2 sets of delay lines are used to produce the true value of the other, and on the other hand to produce the complementary signal 74 without adding an inverter delay. The dual circuit allows the generation of truly complementary clocks with very low skew. The complementary internal device clocks are used to clock the "even" input receivers for sampling at time 127,
The true internal device clock is used to clock the "odd" input receiver for extraction at time 125. The true and complementary internal device clocks are also used to select which data to drive to the output driver. The gate delay between the internal device clock and the output circuit driving the bus is slightly greater than the corresponding delay in the input circuit,
That means new data is always put on the bus shortly after the old data is extracted.

<Modification of DRAM Column Access> FIG. 15 shows a block diagram of a conventional 4 Mbit DRAM 130. The DRAM memory array is divided into eight subarrays, for example 150-157. Each sub-array is divided into an array of memory cells 148,149. Row address selection is performed by the decoder 146. Column decoders 147A and 147B including column amplifiers
Can set their column amplifiers through the center of each sub-array to precharge or latch the most recently stored value as detailed above. Internal I / O lines connect each set of amplifiers gated by the corresponding column decoder to the input and output circuits ultimately connected to the device pins. These I / O lines are used to drive data from selected bit lines to data pins (part of pins 131-145) or to receive data from the pins and write to selected bit lines. Conventionally, such column access paths constructed with this constraint do not have sufficient bandwidth to interface to high speed buses. The method of the present invention does not require changes to the overall method used for column access, but changes implementation details. Many of these details have been selectively implemented in certain high speed storage devices, but never in the bus architecture of the present invention.

It is impossible to run (run) the internal input / output line at a high bus cycle speed by the conventional method. The preferred method reads and writes some (preferably 4) bytes during each cycle and modifies the column access path to run (run) at a slower rate (the number of bytes accessed per cycle). Inverse number, preferably 1/4 of bus cycle speed). Three methods are used to provide the necessary additional internal I / O lines and to supply data to the memory cells at that rate. First, the number of I / O bit lines in each sub-array through column decoder 147 is, for example, eight 16 for each of the two columns of column amplifiers, and during each cycle the column decoder is "Upper" half 1
Select a set of columns from 48 and a set of columns from the "bottom" half 149 (where the column decoder is 1 per I / O bit line).
Choose two column amplifiers). Second, each column I / O line is divided in half and the left half 147A of each sub-array is divided.
And the right half 147B (each subarray divided into four quadrants) carries data separately on separate internal I / O lines, and the column decoder selects amplifiers from each of the right and left halves of the subarray. , Double the number of bits that can be obtained in each cycle. Therefore, each column decode selection turns on n column amplifiers, where n is four times the number of I / O lines in the bus for each subarray quadrant (upper left, upper left, lower left and lower right). Equal (8 lines x 4 = 32 lines each in the preferred embodiment) Finally, during each RAS cycle, two different sub-arrays, eg 157, 153, are accessed, which also makes available input containing data. Double the number of output lines, taking into account these changes together, increases the internal I / O bandwidth by a factor of at least 8. Four internal buses are used to route those internal I / O lines. By increasing the number of partitions and dividing them in between, greatly reducing the capacity of each internal I / O line, thereby also reducing the column access time and further increasing the column access bandwidth.

The multiplexed, gated input receiver described above enables high speed input from the device pins to the internal I / O lines and finally to the memory. The multiplexed output driver described above is used to maintain the data flow that can be obtained using the above approach. Control means are provided to select whether the device pin information should be treated as an address and therefore be decoded, or whether the input data to be placed on the internal I / O line or the output data to be read therefrom.

Each sub-array can access 32 bits, 16 bits from the left sub-array and 16 bits from the right sub-array, every cycle. There are eight I / O lines per amplifier row, with two sub-arrays accessed at a time, the DRAM can provide 64 bits per cycle. This extra I / O bandwidth is not needed for reading (and is probably not used),
It may be necessary for writing. Write bandwidth availability is a more difficult problem than read bandwidth because overwriting values in the amplifier is a slow operation and depends on how the amplifier is connected to the bit line. is there. The extra set of internal I / O lines will provide some bandwidth margin for write operations.

Those skilled in the art will appreciate that various modifications of the teachings of the present invention can be further implemented within the scope of the claims of the present invention.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic 2D organization of a memory device.

FIG. 2 is a schematic block diagram showing parallel connection of all buses and serial reset lines to each device inside the device.

FIG. 3 is a perspective view of the device of the present invention showing the 3D packaging of the semiconductor device on the main bus.

FIG. 4 shows a format of a request packet.

FIG. 5 shows the format of a retry response from a slave.

[Fig. 6] Bus after a request packet collision occurs at the bus
Show how cycles and arbitration are handled.

FIG. 7 is a diagram showing a timing at which signals from two devices are temporarily overlapped and simultaneously drive a bus.

FIG. 8 shows connections and timing between a bus clock and devices on the bus.

FIG. 9 shows a transceiver with several bus units.
FIG. 5 is a perspective view showing how a transceiver can be used to connect to a bus.

FIG. 10 is a block diagram and schematic of input / output circuits used to connect a device to a bus.

FIG. 11 is a circuit diagram of a clocked sense amplifier used as a bus input receiver.

FIG. 12 is a block diagram showing how an internal device clock is generated from two bus clock signals using an adjustable delay line.

FIG. 13 is a timing diagram showing the relationship of signals in the block diagram of FIG.

FIG. 14 is a timing diagram of the preferred means for implementing the reset procedure of the present invention.

FIG. 15 is a diagram showing the overall organization of a 4M bit DRAM divided into eight sub-arrays.

[Explanation of symbols]

15, 16, 17 ......... Memory device, 18 ...
… (Primary) bus, 19 ……… Transceiver device, 20 ……
... Pin, 22 ......... Request packet, 41 ...
... Device A, 42 ... ... Device B, 50 ...
... Bus clock generator, 51, 52 ... ... memory device, 53, 5
4 ......... Clock line, 65 ......... Transceiver bus, 66 ...
... Circuit boards 71, 72 ..... Input receivers, 73,7
4 ... Clock, 76 ... Output driver, 100 ... Early arrival bus clock input 101, 111 ... Clocked receiver 103 ... Variable delay line 104 ...
... fixed delay line (t ₀ ) 105 ... variable delay line (t ₀ + X) 106 ... variable delay line (t ₀ + X / 2) 110 ... late arrival bus clock input.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI G06F 1/04 330Z (56) Reference JP-A-2-8950 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/40-11/419 G06F 12/00 G06F 1/10 H03K 5/26

Claims (6)

(57) [Claims] 1. A synchronous memory device having an array of memory cells, comprising a clock receiver circuit for receiving a fixed frequency external clock signal, comprising a plurality of input receivers, wherein An input receiver circuit for synchronously extracting a read operation request, and a delay locked loop circuit coupled to the clock receiver circuit for outputting data in synchronization with the external clock signal, An output driver circuit is provided that includes a plurality of output drivers and outputs data to an external bus during a read operation, the plurality of output drivers having a first portion of data on a rising edge of the external clock signal. And a second portion of data according to the falling edge of the external clock signal. 2. The memory device according to claim 1, wherein the delay lock loop circuit generates a first internal clock signal in synchronization with the external clock signal, and the plurality of output drivers include the output driver. Outputting a first portion of data in response to a rising edge of the first internal clock signal,
A memory device characterized by the above. 3. The memory device according to claim 2, wherein the delay lock loop circuit generates a second internal clock signal synchronized with the external clock signal, and the plurality of output drivers include the second internal clock signal. A memory device which outputs a second portion of data in response to a rising edge of a second internal clock signal. 4. The memory device according to claim 3, wherein the input receiver circuit operates in response to the first internal clock signal and is responsive to a transition of the first internal clock signal. A first input latch that latches first data; and a second input latch that operates in response to the second internal clock signal and latches second data in response to a transition of the second internal clock signal. A memory device comprising: and. 5. A synchronous memory device having an array of memory cells, comprising a clock receiver circuit for receiving first and second external clock signals, the clock receiver circuit being coupled to the clock receiver circuit. A delay lock for producing first and second internal clock signals respectively synchronized with the first and second external clock signals.
An input receiver circuit is provided that includes a loop circuit and that extracts a read operation request in synchronization with the first and second external clock signals. A plurality of input receivers that latch in synchronization with a clock signal are included, a plurality of output drivers are included, and an output driving circuit that outputs data to an external bus during a read operation is provided And a second portion of the data in response to the transition of the first internal clock signal and a second portion of the data in response to the transition of the second internal clock signal. Memory device. 6. The memory device according to claim 5, wherein the input receiver circuit operates in response to the first internal clock signal and is responsive to a transition of the first internal clock signal. A first input latch that latches first data; and a second input latch that operates in response to the second internal clock signal and latches second data in response to a transition of the second internal clock signal A memory device comprising: and.