JP3352998B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device such as a thin film transistor which is excellent in reliability and mass productivity and has high yield, and a method of manufacturing the same. The present invention is applied to a driving circuit such as a liquid crystal display or a thin film image sensor, a three-dimensional integrated circuit, or the like as an application field thereof.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated circuit has mainly been a monolithic type formed on a semiconductor substrate such as silicon. However, in recent years, an attempt has been made to form a semiconductor integrated circuit on an insulating substrate such as glass or sapphire. . The reason is that the operating speed is improved by reducing the parasitic capacitance between the substrate and the wiring, and that the glass material such as quartz is inexpensive because there is no size limitation like a silicon wafer, This is because the separation between elements is easy, and a latch-up phenomenon which is a problem particularly in a CMOS monolithic integrated circuit does not occur. In addition, apart from the above reasons, in liquid crystal displays and contact image sensors,
Since a semiconductor element and a liquid crystal element or a photodetection element need to be integrally formed, it is necessary to form a thin film transistor (TFT) on a transparent substrate.

For these reasons, thin-film semiconductor elements have been formed on insulating substrates. FIG. 5 shows a TFT as an example of a conventional thin film semiconductor device. As shown in the figure, a film 503 such as silicon oxide is formed as a passivation film on an insulating substrate 501, and a TFT is formed thereon independently of other TFTs. TFT
Are a source (drain) region 507 and a drain (source) region 509, a channel formation region (also simply referred to as a channel region) 508 sandwiched therebetween, a gate insulating film 504, and a gate electrode 510, similarly to the MOSFET of the monolithic integrated circuit. And a source (drain) electrode 511
And a drain (source) electrode 512. Also,
An interlayer insulator 506 such as PSG is provided to enable multilayer wiring.

The example shown in FIG. 5 is called a forward coplanar type, but the TFT is also called an inverse coplanar type, a forward stagger type, or an inverse stagger type depending on the arrangement of the gate electrode and the channel region. Although there is a form, the details will be left to other documents and will not be described further here.

[0005]

In a monolithic integrated circuit, contamination by alkali ions such as sodium and potassium or transition metal ions such as iron, copper and nickel is a serious problem. Great care has been taken to stop it. TFT
But the problem of these ions is equally serious, and attention is paid to cleaning the production process to minimize contamination. In addition, measures are taken to prevent these contaminations from reaching the element.

The difference between a thin film semiconductor device and a monolithic integrated circuit is that the concentration of contaminant ions in the substrate is relatively high. In other words, single-crystal silicon used for monolithic integrated circuits has been produced to eliminate these harmful contaminants with the accumulation of technology for many years. Is 10 ¹⁰ cm ⁻³ or less.

However, in general, the concentration of contaminant elements in an insulating substrate for a thin film semiconductor element is not low. Of course, for single-crystal substrates such as spinel substrates and sapphire substrates,
Although it is theoretically possible to reduce the concentration of the foreign element which is the above-mentioned pollution source, it is not practical from a profit viewpoint. Also,
Quartz substrates can be ideally prevented from invading foreign elements if they are manufactured by a gas phase reaction using high-purity silane gas and oxygen as raw materials.However, since the structure is amorphous, the foreign elements are once incorporated. It is difficult to discharge this to the outside when it is spilled. In addition, it is necessary to use a low-price substrate for the substrate used for the liquid crystal display, particularly because the cost problem is prioritized. It contains. Some of these foreign elements themselves are not preferable for the semiconductor element, and in the process of adding these foreign elements, they may be mixed in from the outside or may be contained as impurities in the added material.

For example, TN glass is an inexpensive glass substrate having good heat resistance and a coefficient of thermal expansion close to that of silicon. Therefore, TN glass is preferable as a substrate for a liquid crystal display, but contains about 5% of lithium. Part of this lithium is ionized and enters the semiconductor element as mobile ions, resulting in deterioration of the element. In addition, it is difficult to produce lithium having a high purity of 99% or more.
% Of sodium. The ionization rate of sodium is as large as about 10%, and this sodium ion has a very serious effect on the characteristics of the device.

In a conventional thin-film semiconductor device, as shown in FIG. 5, silicon oxide or the like is used as a passivation film, and PSG or BPSG is used as an interlayer insulator for the penetration of mobile ions. Have been addressed by gettering these mobile ions.
However, it has been difficult to sufficiently prevent contamination by these methods. An object of the present invention is to prevent the element from deteriorating due to penetration of these contaminant elements and ions.

[0010]

According to the present invention, in order to suppress the above-mentioned contamination, a blocking action against mobile ions such as silicon nitride, aluminum oxide and tantalum oxide is provided at the lower and upper portions of the thin film semiconductor device, respectively. (Blocking film).

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical example of the present invention is shown in FIG. FIG. 1 shows a TFT using the present invention.
That is, a first silicon nitride film is formed as the first blocking film 102 on the insulating substrate 101. First
Has an effect of preventing contamination from the substrate.
Then, a film 103 having good adhesion to a silicon material such as silicon oxide is formed over the first silicon nitride film.
If a semiconductor film is formed directly on the first silicon nitride without forming the film 103 and a TFT is manufactured, the channel region becomes conductive due to trap levels generated at the interface between the silicon nitride and the semiconductor material. Will not work. Therefore, it is important to provide such a buffer.

On the film 103, a TFT is formed. T
FT includes a source (drain) region 107 and a drain (source) region 109, and a channel region 10 interposed therebetween.
8, a gate insulating film 104 and a gate electrode 110.
The source, drain, and channel regions of the TFT are formed of a single crystal, polycrystal, or amorphous semiconductor material. As the semiconductor material, for example, silicon, germanium, silicon carbide, and alloys thereof can be used.

Then, a second silicon nitride film is formed as a second blocking film 105 covering the TFT. Here, it is a feature of the present invention that the second silicon nitride film is formed after the fabrication of the TFT and before the electrode is formed on the source and / or the drain. In the related art, a silicon nitride film as a final passivation film is formed after the formation of an electrode, but the present invention has a different purpose from a silicon nitride film formed in such a meaning. That is, the second silicon nitride film in the present invention is formed to enclose the TFT together with the first silicon nitride film, and is intended to prevent contamination in the electrode forming step after the TFT is formed. Is what you do. Therefore, after a TFT and its associated electrodes and wirings are formed according to the present invention, a silicon nitride film may be formed as a final passivation film as in the related art.

After the formation of the second silicon nitride film, the interlayer insulating film 106 is formed using an interlayer back insulating material, for example, PSG.
Are formed, and a source (drain) electrode 111 and a drain (source) electrode 112 are formed.

In the example of FIG. 1, however, the gate insulating film extends far away, and there is a possibility that the gate insulating film may enter the inside of the TFT from its end. An improvement of this is the example shown in FIG. 2, in which the gate insulating film is only on the TFT, so that there is no problem as in FIG. However, in this case, since the source region and the drain region in the portion adjacent to the channel region are in contact with the silicon nitride film, the silicon nitride in this portion is polarized by the gate voltage or traps electrons, thereby causing the TFT to operate. May interfere.

FIG. 3 shows an example which overcomes the above problem.
Here, the source region and the drain region adjacent to the channel region are not adjacent to the silicon nitride film. Therefore, the difficulties of polarization of silicon nitride and electron trap are solved. However, when a self-alignment process using a gate electrode as a mask is employed in forming the source and drain regions, an acceptor or a donor element must be implanted through a gate insulating film in this example, as in the example of FIG. Therefore, if the ion implantation method is adopted, it is necessary to increase the acceleration energy of the ions. At this time, as a result of implanting high-speed ions, the source and drain regions may be expanded due to the secondary scattering.

In FIG. 2, reference numeral 201 denotes an insulating substrate;
2 is a first silicon nitride film, 203 is a buffer insulating film such as silicon oxide, 204 is a gate insulating film, 205 is a second silicon nitride film, 206 is an interlayer insulating film, and 207 is a source (drain).
Region, 208 is a channel region, 209 is a drain (source) region, 210 is a gate electrode, 211 is a source (drain) electrode, and 212 is a drain (source) electrode.
In FIG. 3, reference numeral 301 denotes an insulating substrate; 302, a first silicon nitride film; 303, a buffer insulating film such as silicon oxide;
304, a gate insulating film; 305, a second silicon nitride film;
06 is an interlayer insulating film, 307 is a source (drain) region,
308 is a channel region, 309 is a drain (source) region, 310 is a gate electrode, 311 is a source (drain)
The electrode 312 is a drain (source) electrode.

In the present invention, when a silicon nitride film is used as the blocking film, x = 1.0 to x = 1.7 when SiN _x is represented by a chemical formula, and in particular, x = 1.7
The stoichiometric composition from 1.3 to x = 1.35 (x = 1.3
Good results were obtained with 3) or a similar one. Therefore, in the present invention, the silicon nitride has a reduced pressure CV.
It was better to form by the D method. However, it goes without saying that even with a silicon nitride film formed by a plasma CVD method or a photo CVD method, the reliability of the element is improved as compared with the case where the present invention is not used.

If a silicon nitride film is to be formed by a low pressure CVD method, dichlorosilane (S
iCl ₂ H ₂ ) and ammonia (NH ₃ ) at a pressure of 1
500 to 800 ° C at 0 to 1000 Pa, preferably 55
The reaction may be performed at 0 to 750 ° C. Of course, silane (SiH ₄ ) or tetrachlorosilane (SiCl ₄ ) may be used.

Further, as described above, aluminum oxide or tantalum oxide is used as a blocking film in addition to silicon nitride. In order to form these films, a CVD method or a sputtering method may be used. For example, to form an aluminum oxide film, trimethylaluminum Al (CH ₃ ) ₃ is converted to nitrogen oxide (N ₂ O, NO, NO ₂ ).
And the like.

FIG. 4 shows an example of forming a low impurity concentration drain (LDD), which is a known technique, using the present invention. First, a silicon nitride film 402 having a thickness of 50 to 1000 nm is formed on an insulating substrate 401 such as quartz or AN glass by a low pressure CVD method. At this time, if not only the front surface but also the back surface of the substrate is covered with the silicon nitride film, the present invention can be implemented more reliably and effectively. That is, in the manufacturing process, mobile ions generated from the back surface (although they are contained in the substrate) often reach the front surface for various reasons, and as a result, for example,
Mobile ions penetrate into the gate oxide film during fabrication. Also, if the back surface is a source of mobile ions, the manufacturing apparatus such as a film forming apparatus is constantly contaminated by mobile ions. Therefore, in order to maintain the cleanliness of the manufacturing apparatus, a silicon nitride film is formed on the back surface of the substrate. It is necessary to provide. A silicon oxide film 403 for buffering is formed on the silicon nitride
By the method D, a thickness of 50 to 1000 nm is formed. At this time, if a gas containing halogen such as hydrogen chloride at a volume ratio of 3% to 6%, for example, about 5% is mixed in the source gas, a halogen element is taken into the obtained silicon oxide film. Since this halogen binds to an alkali ion such as sodium and fixes sodium, a greater effect can be obtained in preventing sodium contamination. However, excessive addition of halogen is not preferable because it makes the film rough and deteriorates adhesion and surface flatness.

Next, an amorphous silicon film to which neither a donor nor an acceptor is added is formed by a low pressure CVD method or a plasma CVD method.
20 to 500 thickness by VD method or sputtering method
Only nm is formed. Then, this is etched on the island. A gate insulating film having a thickness of 10 to 100 n is formed thereon.
m silicon oxide film is formed by a low pressure CVD method or a sputtering method. Also at this time, as described above,
Alternatively, a halogen material gas may be mixed in the sputtering gas.

Then, a polycrystalline or microcrystalline silicon film doped with phosphorus to about 10 ²¹ cm ^-3 is formed thereon by low pressure CVD or plasma CVD. Then, the silicon film and a gate insulating film (silicon oxide) thereunder are patterned to form a gate electrode 410 and a gate insulating film 404.

Further, ion implantation is performed in a self-aligned manner by using the gate electrode as a mask to form a source (drain) region 407 and a drain (source) region 408 having a relatively low impurity concentration (about 10 ¹⁷ to 10 ¹⁹ cm ⁻³ ). To form A portion where the impurity has not been implanted remains as a channel region 408. Thus, FIG. 4A is obtained.

Next, as shown in FIG.
The PSG film 413 is formed entirely by the method. Then, this is etched by a known directional etching to form a side wall 414 beside the gate electrode. afterwards,
The ion implantation is performed again, and the source (drain) region 407a and the drain (source) region 4
09a is formed. A region with a low impurity concentration includes a source (drain) region 407b and a drain (source) region 409.
As b, LDD is formed. Thus, FIG.
Get.

Thereafter, as shown in FIG.
The silicon nitride film 405 is entirely formed to a thickness of 50 by the VD method.
To 1000 nm. Thereafter, the silicon film is crystallized by low-temperature annealing at, for example, about 600 ° C., and the source and drain regions are activated. This step may be performed by laser annealing. In this way, a TFT intermediate is obtained.

The example of FIG. 4 is merely an example of the present invention, and it will be apparent that the present invention is not limited to the steps described above. In the example of FIG. 4, as in the example of FIG. 3, there is no portion where the silicon nitride film, the gate electrode, and the source or drain region are adjacent to each other. That is, unlike the case of FIG. 2, since the side wall 414 exists, there is no problem as shown in FIG. Further, different from FIG. 3, there is a feature that a donor or an acceptor can be easily added.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The characteristics of a TFT using the present invention will be described. The TFT used in this embodiment is an LDD type TFT manufactured on a quartz glass substrate according to the process shown in FIG.
First, a silicon nitride film 402 having a thickness of 100 nm is formed on a quartz glass substrate 401 and on its back and side surfaces (that is, the entire substrate) by a low-pressure CVD method, and further, a silicon oxide film (low-temperature oxide film) is continuously formed by a low-pressure CVD method. (LTO
403) was formed to a thickness of 200 nm, and finally, an amorphous silicon film was formed to a thickness of 30 nm also by the low pressure CVD method. The maximum process temperature at this time is 6
00 ° C. Next, the amorphous silicon film was patterned into an island shape. Then, a very thin portion of the surface of the amorphous silicon film, a thickness of 2 to 10 nm, was oxidized by an anodic oxidation method. After that, the silicon oxide film is
00 nm was formed. Here, the sputtering atmosphere was a mixed gas of oxygen and argon or another rare gas, and the partial pressure of oxygen was 80% or more. At this time, a defect occurs in the underlying film due to the sputtering impact. For example, when the underlying layer is a silicon film, oxygen atoms are implanted in silicon, and the concentration of oxygen increases. In such a state, silicon has many polar levels. That is, the boundary between silicon and silicon oxide is not clear. However, if a thin anodic oxide film is formed in advance as in this embodiment, since the silicon oxide already exists at the time of sputtering, the above-described mixing of atoms is avoided, and the silicon film and the oxidized The boundary of the silicon film is kept.

After the formation of the silicon oxide film, a 300 nm-thick n ⁺ -type microcrystalline silicon film containing about 10 ²¹ cm ^{−3 of} phosphorus was formed by a low pressure CVD method. The maximum process temperature of the above film formation was 650 ° C. After that, the gate electrode was patterned to form a gate electrode 410 and a gate insulating film 404. Further, arsenic ions were implanted by 2 × 10 ¹⁸ cm ⁻³ by ion implantation to form source and drain regions 407 and 409. Thus, FIG. 4A was obtained.

Next, as shown in FIG. 4B, a PSG film 413 was formed by a low pressure CVD method, and a side wall 414 shown in FIG. 4C was formed by directional etching.
Further, arsenic ions are added to region 4 by ion implantation.
5 × 10 ²⁰ cm ^{−3 was} implanted into 07a and 409a.

Thereafter, the silicon nitride film 405 is entirely depressurized C
It was formed by the VD method. Thus, FIG. 4D was obtained. Then, it is annealed at 620 ° C. for 48 hours in a vacuum,
Regions 407a, 407b, 408, 409a, 409b
Was activated. Then, a PSG film was entirely formed as an interlayer insulator by a low pressure CVD method, holes for electrodes were formed, and aluminum electrodes were formed in the source region and the drain region. Then, finally, a silicon nitride film was formed again by the low pressure CVD method for the purpose of passivation.

The TFT thus formed was extremely reliable. It was shown that the so-called bias-temperature processing (BT processing) did not change the operation characteristics of the device. An example is shown in FIG. The BT process is shown in FIG.
And routed as in circuit diagram shown in, it was performed by adding a bias voltage V _B between the source gate (G) in warm (S), drain (D). In particular,
Immediately after the fabrication, the gate voltage-drain current characteristics of the TFT were measured at room temperature (V _B = 0).
Of the gate voltage-drain current characteristics of (V _B = + 2
0 V), and then again apply a voltage of −20 V to the gate electrode at 150 ° C. for 1 hour, and then measure the gate voltage-drain current characteristics of the TFT at room temperature (V _B = −20).
V) Variation in the threshold voltage of the TFT was examined.

FIG. 6B shows the characteristics of the TFT manufactured by the method described above. As described above, the characteristics were not affected at all by the bias voltage V _B, and as a result of precise measurement, the fluctuation of the threshold voltage was 0.2 V or less.

On the other hand, the structure shown in FIG. 6A is manufactured by the same process as that shown in this embodiment except that the silicon nitride films 402 and 405 are not provided. properties have gone largely dependent on the V _B as such. Such a change in the characteristics (a change in the threshold voltage) is described as being caused by mobile ions such as sodium in the gate insulating film. The larger the change, the more the mobile ions, and as shown in FIG. It is described that those with little fluctuation have a small amount of mobile ions. From the fluctuation range of the threshold voltage, it is estimated that the amount of mobile ions in the gate electrode of the TFT manufactured in this example is about 8 × 10 ¹⁰ cm ⁻³ . That is, it was shown that by providing a silicon nitride film as in the present invention, it is possible to significantly improve the characteristics of the TFT and improve the reliability.

[0035]

According to the present invention, a thin film semiconductor device such as a TFT which is less affected by mobile ions such as sodium can be manufactured. Conventionally, it has become possible to form a TFT even on a substrate on which elements cannot be formed due to the presence of mobile ions. In order to carry out the present invention, a coplanar type TFT as shown in FIGS. 1 to 4 or an inverse coplanar type, a staggered type, or an inverted staggered type TFT may be used. Further, the present invention does not impose any restrictions on the operation of the thin film semiconductor element, so that the silicon of the transistor may be amorphous, polycrystalline, microcrystalline, or in the intermediate state. It will be clear that they may be single crystals or even single crystals.

[Brief description of the drawings]

FIG. 1 shows an example of a TFT according to the present invention.

FIG. 2 shows an example of a TFT according to the present invention.

FIG. 3 shows an example of a TFT according to the present invention.

FIG. 4 shows an example of manufacturing a TFT according to the present invention.

FIG. 5 shows an example of a conventional TFT.

FIG. 6 shows characteristics of a TFT using the present invention and a TFT not using the TFT.

[Explanation of symbols]

 Reference Signs List 101 insulating substrate 102 first blocking film 103 buffer insulating film 104 gate insulating film 105 second blocking film 106 interlayer insulating film 107 source (drain) region 108 channel region 109 drain (source) region 110 gate electrode 111 source (drain) ) Electrode 112 Drain (source) electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 29/78 627F (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336 H01L 21 / 318 H01L 21/322

Claims (6)

(57) [Claims] 1. A blocking film is formed on an insulating substrate.
The blocking layer silicon oxide film containing a halogen is formed on, made of silicon in close contact with the silicon oxide film
A method for manufacturing a semiconductor device, comprising: forming a semiconductor film, forming a thin film transistor having the semiconductor film, a gate insulating film, and a gate electrode, forming a silicon nitride film on the thin film transistor, and then annealing. . 2. A blocking film is formed on an insulating substrate,
The blocking layer silicon oxide film containing a halogen is formed on, made of silicon in close contact with the silicon oxide film
Forming a semiconductor film, forming a thin film transistor having the semiconductor film, the gate insulating film, and the gate electrode; forming a silicon nitride film on the thin film transistor; and performing an annealing process, and forming an interlayer insulating film on the silicon nitride film. A method for manufacturing a semiconductor device, which is formed. 3. The method according to claim 2, wherein the interlayer insulating film is made of P
A method for manufacturing a semiconductor device, which is an SG film. 4. The method according to claim 1, wherein the silicon nitride film is formed by a low pressure CVD method or a plasma CVD method.
A method for manufacturing a semiconductor device, which is formed by a method or a photo-CVD method. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the silicon nitride film has a thickness of 50 to 1000 nm. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the annealing is thermal annealing or laser annealing.