JP3334466B2 - Parallel / serial conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a parallel / serial conversion circuit.

[0002]

2. Description of the Related Art A conventional parallel / serial conversion circuit includes:
The parallel data is shifted using a shift register and output as a pulse synchronized with a clock signal.

[0003]

However, in the parallel / serial conversion circuit having the above-described configuration, the serial output signal output is a pulse signal synchronized with the clock signal, and the pulse width is the shortest. Since the width is the same as that of the signal, there is a possibility that a mistake (improper conversion) occurs on the transmission line. This becomes more remarkable as the speed of the clock signal serving as the carrier increases.

In order to prevent this problem, it is necessary to use an expensive transmission line having excellent noise resistance, such as a coaxial cable or a shielded wire.

[0005] The present invention has been made in view of the above points, and an object of the present invention is to provide a parallel / serial conversion circuit that outputs stable serial signal data.

[0006]

According to the first aspect of the present invention,
Parallel signals and the latch clock signal and click of a predetermined bit
Data input terminal lock signal are entered and Ratchikuro
Clock signal terminal, clock input terminal, and ripple carry
A signal output terminal, and based on the clock signal input to the clock input terminal, the data of the parallel signal input when the parallel signal and the latch clock signal are input.
Li when it reaches a predetermined count value counts to have
A counter that outputs a ripple carry signal from the ripple carry signal output terminal and serial signal data input
Data input terminal and latch clock signal.
Clock input terminal input as a clock signal and ripple
Reset where carry signal is input as reset signal
And a data output terminal. When the latch clock signal is input , the output of the data output terminal becomes HIGH.
Of the serial signal input to the data input terminal
Data from the data output terminal and input to the reset terminal
Data output pin at the rise of the ripple carry signal
And resetting the output of the counter to LOW so that when the latch clock signal is inputted, a latch section which keeps outputting a serial signal until a ripple carry signal is inputted from the counter section is provided. It is a feature.

According to a second aspect of the present invention, in the parallel / serial conversion circuit according to the first aspect, the counter section counts up after inverting data of the input parallel signal. It is characterized by the following.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an overall configuration of a parallel / serial conversion circuit according to one embodiment of the present invention. The parallel / serial conversion circuit according to the present embodiment includes a presettable counter circuit 1 as a counter unit and a D flip-flop circuit 2 as a latch unit. The presettable counter circuit 1 has a data input terminal DATA, a clock input terminal CLK1, a latch clock signal input terminal RCK, and a ripple carry signal output terminal RCY. The data input terminal DATA is for inverting input of parallel signal data of a predetermined bit. The clock input terminal CLK1 is for inputting a clock signal. The latch clock signal input terminal RCK inputs a latch clock signal indicating the start of counting. The ripple carry signal output terminal RCY outputs a ripple carry signal indicating the end of counting when a predetermined count value is reached.

The D flip-flop circuit 2 has a data input terminal D, a clock input terminal CLK2, a reset terminal R, and a data output terminal OUT. The data input terminal D
This is for inputting serial signal data. The clock input terminal CLK2 is for inputting a latch clock signal. The reset terminal R is for inputting a ripple carry signal. The data output terminal OUT outputs the data of the serial signal input to the data input terminal D when the latch clock signal is input to the clock input terminal CLK2, and outputs when the ripple carry signal is input to the reset terminal R. Is to end.

Hereinafter, the operation of this embodiment will be described. In this embodiment, for convenience of explanation, an operation of converting a parallel signal of 4-bit data of “1010” as an input into a serial signal will be described. FIG. 2 is a timing chart showing the operation of the parallel / serial conversion circuit according to the present embodiment. When the data of the parallel signal is input to the data input terminal DATA, the data is latched at the rising edge of the latch clock signal input to the latch clock signal input terminal RCK and is inverted and input. Therefore, in the present embodiment, a data value of “0101” is input.

Then, counting is performed based on the clock signal input to the clock input terminal CLK1, and when the count value reaches “1111”, the counting is terminated, and a ripple carry signal indicating the end of the count is output from the ripple carry signal output terminal RCY. Output.

When the latch clock signal is input to the clock input terminal CLK2, the D flip-flop circuit 2 sets the output of the data output terminal OUT to "HIGH" and outputs the serial signal input to the data input terminal D. Data is output, and the output of the data output terminal OUT is reset to “LOW” at the rise of the ripple carry signal input to the reset terminal R. By using the output signal from the data output terminal OUT as a serial signal, a parallel signal can be converted to a serial signal. Here, the presettable counter 1 starts counting from 0 again, but the output from the D flip-flop circuit 2 does not appear unless the data is latched next at the rising edge of the latch clock signal.

Therefore, since the pulse width corresponding to the data of the parallel signal is defined by the count value of the clock signal, the possibility that data transmitted on the transmission line is missed (is not correctly converted) is reduced. Also, since the bit error occurs only in the lower bit error (the upper bit error is less likely to occur because the pulse width is counted),
The bit error checking mechanism can be simplified. Further, since the required data is defined by the pulse width, the data can be easily compressed as compared with a transmission signal in which HIGH data and LOW data are complicated, which reduces errors on the transmission line.

In the present embodiment, the case where a parallel signal composed of 4-bit data is converted into a serial signal has been described. However, the present invention is not limited to this, and 2n bits (n = 3,...) , K) have the same effect. In the present embodiment,
The case where the count-up is performed after inverting the data of the parallel signal has been described. However, the present invention is not limited to this. Even if the count-down is performed using the data of the parallel signal as the count value, the parallel signal is serialized. It can be converted to a signal.

[0015] claimed invention in claim 1, wherein the data input terminal and the latch clock signal terminal and click the parallel signal and the latch clock signal and the clock signal of a predetermined bit are entered
Has a lock input terminal and a ripple carry signal output terminal
Then, when the parallel signal and the latch clock signal are input, the data of the input parallel signal is clock input.
Counts based on the clock signal input to the pin and outputs a ripple carry signal when the count reaches a predetermined value.
Counter that outputs a ripple carry signal from the signal output terminal, and a data input that receives serial signal data
Pin and latch clock signal input as clock signal
Clock input terminal and ripple carry signal
The reset terminal input as a set signal and the data output
And a power terminal, wherein in the latch clock signal is input the output of the data output terminal to HIGH data input
Data output of serial signal data input to the slave
Ripple output from the terminal and input to the reset terminal
Reset of the data output terminal at the rise of the carry signal
And the latch section keeps outputting a serial signal until the ripple carry signal is inputted from the counter section when the latch clock signal is inputted, so that the data transmitted through the transmission path is provided. Is less likely to be missed (not converted correctly)
In addition, since only a lower bit error occurs in a bit error (an upper bit error hardly occurs because the pulse width is counted), a bit error check mechanism can be simplified, and necessary data is defined by the pulse width. So
Provided is a parallel / serial conversion circuit that facilitates data compression as compared with a transmission signal in which HIGH data and LOW data are complicated, which can reduce errors on a transmission line and that outputs stable serial signal data. I was able to.

According to a second aspect of the present invention, in the parallel / serial conversion circuit according to the first aspect, the counter section counts up after inverting the data of the input parallel signal. The possibility that data transmitted along the path is missed (is not correctly converted) is reduced, and bit errors occur only in lower bits (errors in upper bits are less likely to occur because the pulse width is counted). Since the error checking mechanism can be simplified and the required data is defined by the pulse width, the data can be easily compressed as compared with a transmission signal in which HIGH data and LOW data are complicated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an overall configuration of a parallel / serial conversion circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the parallel / serial conversion circuit conversion circuit according to the present embodiment.

[Explanation of symbols]

 1 Presettable counter circuit 2 D flip-flop circuit DATA Data input terminal CLK1, CLK2 Clock input terminal RCK Latch clock signal input terminal RCY Ripple carry signal output terminal D Data input terminal R Reset terminal OUT Data output terminal

Claims (2)

(57) [Claims] 1. A predetermined bit parallel signal and the latch clock signal and a data input terminal及 a clock signal are entered
Clock signal terminal, clock input terminal,
It has a pull carry signal output terminal, and when the parallel signal and the latch clock signal are input, the data of the parallel signal input is input to the clock input terminal.
A counter that outputs a ripple carry signal from a ripple carry signal output terminal when a predetermined count value is reached based on a count signal based on the serial signal;
A data input terminal to which data is input and a latch clock
Clock input terminal for inputting a signal as a clock signal
And the ripple carry signal is input as a reset signal.
And a data output terminal. When the latch clock signal is input , the output of the data output terminal is
Is set to HIGH and the serial signal input to the data input terminal is
Output data from the data output terminal and reset
At the rising edge of the ripple carry signal input to the
Reset the output of the data output terminal to LOW
And a latch section for continuously outputting a serial signal until the ripple carry signal is input from the counter section when the latch clock signal is input. 2. The parallel / serial conversion circuit according to claim 1, wherein the counter section counts up after inverting data of the input parallel signal.