CN118573346A - Synchronous handshake circuit, data transmitting terminal and data transmission system - Google Patents

Abstract

The embodiment of the disclosure provides a synchronous handshake circuit, a data transmitting terminal and a data transmission system, which comprises: the gating signal generation module and the first triggering module; the strobe signal generation module is configured to select a clock signal with a period from the clock signals of the data sending end and output the clock signal to the first trigger module under the control of a strobe control signal; the first trigger module is configured to output a handshake request signal to the data receiving end under the triggering of a periodic clock signal until the handshake response signal sent by the data receiving end is received, and the handshake request signal is stopped being output. When target data to be transmitted exists at the data transmitting end, the gating signal generating module selects a clock signal with a period to output to the first triggering module under the control of the gating control signal, synchronous handshake between the data transmitting end and the data receiving end is realized in the clock signal with the period, handshake duration of the handshake between the data transmitting end and the data receiving end is reduced, and data processing speed is improved.

Description

Synchronous handshake circuit, data transmitting terminal and data transmission system

Technical Field

Embodiments of the present disclosure relate to the field of integrated circuit technology and related technology, and in particular, to a synchronous handshake circuit, a data transmitting terminal, and a data transmission system.

Background

In a classical synchronous handshake circuit, a data transmitting end transmits a handshake request signal which is continuously high, a data receiving end beats the handshake request signal for two times and then generates a handshake response signal, and data is stored and transmitted to a downstream circuit for use. The data transmitting end receives the handshake response signal and then beats two beats, and then pulls down the handshake request signal, thus completing one-time synchronous handshake.

In the prior art, the number of beats of the handshake request signal and the handshake response signal at the data transmitting end causes long handshake process of the data transmitting end and the data receiving end, which is not beneficial to realizing high-speed processing of data.

Disclosure of Invention

Embodiments described herein provide a synchronous handshake circuit, a data transmitting terminal, and a data transmission system that solve the problems of the prior art.

According to a first aspect of the present disclosure, there is provided a synchronous handshake circuit applied to a data transmitting terminal, including: the gating signal generation module and the first triggering module;

the strobe signal generation module is configured to select a clock signal with a period from the clock signals of the data sending end to output to the first trigger module under the control of a strobe control signal;

The first trigger module is configured to output a handshake request signal to a data receiving end under the triggering of the clock signal of one period until the handshake response signal sent by the data receiving end is received, and the handshake request signal is stopped being output.

In some embodiments of the present disclosure, when the data transmitting end has target data to be transmitted, the strobe control signal is triggered by a rising edge of a clock signal of the data transmitting end so as to change a level, so that a high level pulse width of the strobe control signal is a clock period of the clock signal of the data transmitting end at this time;

the gating signal generation module is configured to determine whether to output a clock signal with a period to the first trigger module according to the level of the gating control signal when the clock signal of the data sending end rises.

In some embodiments of the present disclosure, the strobe signal generating module includes a first latch and an and gate;

the data input end of the first latch is connected with the gating control signal, the enabling end of the first latch is connected with the clock signal of the data transmitting end, the output end of the first latch is electrically connected with the first input end of the AND gate, the second input end of the AND gate is connected with the clock signal of the data transmitting end, and the output end of the AND gate is used for outputting a clock signal of a period.

In some embodiments of the present disclosure, the first trigger module includes a first trigger, a clock end of the first trigger is connected to the strobe signal generating module to receive the clock signal of the period, a data input end of the first trigger is connected to a high level, an output end of the first trigger is used for outputting the handshake request signal, and a clear end of the first trigger is used for receiving the handshake response signal.

In some embodiments of the present disclosure, the synchronization handshake circuit further comprises a memory module;

The storage module is configured to latch or register the target data under the triggering of the clock signal of one period.

In some embodiments of the present disclosure, the memory module includes a second latch or register;

The data input end of the second latch or the register is used for connecting the target data, the pulse input end of the second latch or the register is connected with the clock signal of one period, and the output end of the second latch or the register is used for latching or registering the target data.

According to a second aspect of the present disclosure, there is provided a data transmitting end comprising the synchronization handshake circuit according to any of the first aspects.

According to a third aspect of the present disclosure, there is provided a data transmission system comprising: a data transmitting end and a data receiving end;

the data transmitting end comprises the synchronous handshake circuit in any one of the first aspect;

The data receiving end comprises a second triggering module, and the second triggering module is configured to output the handshake response signal to the synchronous handshake circuit under the triggering of a clock signal of the data receiving end after receiving the handshake request signal.

In some embodiments of the present disclosure, the second trigger module includes a second trigger, a data input end of the second trigger is configured to receive the handshake request signal, a clock end of the second trigger is connected to a clock signal of the data receiving end, and an output end of the second trigger is configured to output the handshake response signal.

In some embodiments of the present disclosure, the second trigger module includes a plurality of third triggers connected in sequence,

The output end of the last third trigger is connected with the data input end of the next third trigger, the clock end of each third trigger is connected with the clock signal of the data receiving end, the data input end of the first third trigger is used for receiving the handshake request signal, and the output end of the last third trigger is used for outputting the handshake response signal.

The embodiment of the disclosure provides a synchronous handshake circuit, a data transmitting terminal and a data transmission system, wherein a gating signal generating module selects a clock signal with a period from clock signals of the data transmitting terminal to be output to a first triggering module under the control of a gating control signal; the first triggering module outputs a handshake request signal to the data receiving end under the triggering of a periodic clock signal until the handshake response signal sent by the data receiving end is received, and the handshake request signal is stopped being output. By arranging the gating signal generation module in the synchronous handshake circuit, when target data to be transmitted exists at the data transmitting end, the gating signal generation module selects a clock signal with a period to output to the first trigger module under the control of the gating control signal, and synchronous handshake between the data transmitting end and the data receiving end is realized in the clock signal with the period, so that handshake duration of the handshake between the data transmitting end and the data receiving end is reduced, and data processing speed is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:

Fig. 1 is a schematic diagram of a synchronous handshake circuit according to an embodiment of the present disclosure;

Fig. 2 is a schematic structural diagram of a data transmission system according to an embodiment of the present disclosure;

Fig. 3 is a timing diagram of a data transmission system provided by an embodiment of the present disclosure;

fig. 4 is a schematic diagram of another synchronous handshake circuit provided by an embodiment of the present disclosure;

Fig. 5 is a schematic diagram of a structure of yet another synchronous handshake circuit provided by an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a structure of yet another synchronous handshake circuit provided by an embodiment of the present disclosure;

Fig. 7 is a schematic diagram of a structure of yet another synchronous handshake circuit provided by an embodiment of the present disclosure;

Fig. 8 is a timing diagram of another data transmission system provided by an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts.

In all embodiments of the present disclosure, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or portion of a component).

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Based on the problems existing in the prior art, the embodiment of the present disclosure provides a synchronous handshake circuit, fig. 1 is a schematic structural diagram of the synchronous handshake circuit provided by the embodiment of the present disclosure, fig. 2 is a schematic structural diagram of a data transmission system provided by the embodiment of the present disclosure, and in combination with fig. 1 and fig. 2, the synchronous handshake circuit includes: a strobe signal generation module 10 and a first trigger module 20; the strobe signal generating module 10 is configured to select a clock signal gate clk1 with a period from the clock signals clk1 at the data transmitting end under the control of a strobe control signal valid, and output the clock signal gate clk1 to the first triggering module 20; the first triggering module 20 is configured to output the handshake request signal req to the data receiving terminal 200 under the triggering of the clock signal gate clk1 of a period until the handshake request signal is stopped to be output when the handshake response signal ack sent by the data receiving terminal 200 is received.

In a specific embodiment, the clock signal of the data transmitting end is clk1, if the gating control signal is at a low level at the rising edge of one clock cycle of the clock signal, the gating signal generating module does not select the clock signal of the clock cycle, and if the gating control signal is at a high level at the rising edge of one clock cycle of the clock signal, the gating signal generating module selects the clock signal of the clock cycle and outputs the clock signal of the clock cycle to the first triggering module.

After the selective communication generating module selects a clock signal with a period to output to the first triggering module, the first triggering module receives the clock signal with a period, and outputs a handshake request signal (namely a high level) when the clock signal with a period rises, after the handshake request signal output by the data transmitting end is synchronized to the data receiving end, the data receiving end immediately transmits a handshake response signal to the data transmitting end, which indicates that the handshake request signal is received, and the handshake request signal can be stopped to realize one-time synchronous handshake.

For example, in conjunction with fig. 3, the clock signal at the data transmitting end is clk1, the clock cycle of the clock signal clk1 at the data transmitting end includes a first clock cycle T1, a second clock cycle T2, a third clock cycle T2, and an nth clock cycle Tn, at the rising edge of the first clock cycle T1, that is, at time T0, the strobe control signal valid is at a low level, and at this time, the strobe signal generating module 10 does not strobe the clock signal of the first clock cycle T1, so the strobe signal generating module 10 does not output the clock signal of the first clock cycle T1, and at the rising edge of the second clock cycle T2, that is, at time T1, the strobe control signal valid is at a high level, the strobe signal generating module 10 outputs the clock signal of the second clock cycle T2 to the first triggering module 20. Since the data input end of the first trigger module 20 is constantly connected to the high level, after the first trigger module 20 receives the clock signal of the second clock period T2 output by the strobe signal generating module 10, the first trigger module outputs the handshake request signal req to the data receiving end when the rising edge of the second clock period T2, that is, outputs the high level to the data receiving end, and after the handshake request signal output by the data transmitting end is synchronized to the data receiving end, the data receiving end immediately transmits the handshake response signal ack to the data transmitting end, which indicates that the handshake request signal req is received, and the output of the handshake request signal req can be stopped, at this time, the first trigger module 20 stops outputting the handshake request signal req, that is, the first trigger module sets the handshake request signal from the high level to the low level, and completes one-time synchronization handshake.

The synchronous handshake circuit provided by the embodiment of the disclosure comprises a gating signal generation module, a first trigger module and a second trigger module, wherein the gating signal generation module selects a clock signal of a period from clock signals of a data sending end to output to the first trigger module under the control of a gating control signal; the first triggering module outputs a handshake request signal to the data receiving end under the triggering of a periodic clock signal until the handshake response signal sent by the data receiving end is received, and the handshake request signal is stopped being output. By arranging the gating signal generation module in the synchronous handshake circuit, when target data to be transmitted exists at the data transmitting end, the gating signal generation module selects a clock signal with a period to output to the first trigger module under the control of the gating control signal, and synchronous handshake between the data transmitting end and the data receiving end is realized in the clock signal with the period, so that handshake duration of the handshake between the data transmitting end and the data receiving end is reduced, and data processing speed is improved.

In a specific embodiment, when the data transmitting terminal 100 has the target data to be transmitted, the strobe control signal valid is triggered by the rising edge of the clock signal clk1 of the data transmitting terminal so as to change the level, so that the high level pulse width of the strobe control signal valid is the period width of the clock signal clk1 of the data transmitting terminal at this time; the strobe signal generating module 10 is configured to determine whether to output a clock signal of a period to the first triggering module 20 according to the level of the strobe control signal valid at the rising edge of the clock signal clk1 at the data transmitting end.

Specifically, in conjunction with fig. 3, the clock signal of the data transmitting end is clk1, the strobe control signal is valid, when there is no target data to be transmitted in the data transmitting end, the strobe control signal is kept at a low level, that is, if there is no target data to be transmitted in the data transmitting end before the first clock period T1, the strobe control signal is kept at a low level, if there is no target data to be transmitted in the data transmitting end in the first clock period T1, and at the second clock period T2, there is no target data to be transmitted in the data transmitting end, at this time, the strobe control signal valid is changed from a low level to a high level at the rising edge of the first clock period T1, that is, at the time T0, the strobe control signal valid is changed from a high level to a low level, that is, when there is one target data to be transmitted in the data transmitting end, the high level pulse width of the strobe control signal is the clock period of the data transmitting end. Since the gate control signal is triggered by the rising edge of the clock signal of the data transmission terminal to change its level, the rising edge of the gate control signal from low level to high level is slightly later than the rising edge of the clock signal of the data transmission terminal in the first clock cycle, and the falling edge of the gate control signal from high level to low level is slightly later than the rising edge of the clock signal of the data transmission terminal in the second clock cycle, as shown in fig. 2.

And since the rising edge of the strobe control signal from the low level to the high level is slightly later than the rising edge of the data transmission end in the first clock period, the falling edge of the strobe control signal from the high level to the low level is slightly later than the rising edge of the data transmission end in the second clock period, so that the strobe control signal has not been changed from the low level to the high level and is low at time T0, and therefore the strobe signal generating module 10 does not output the clock signal of the first clock period T1, and the strobe control signal has not been changed from the high level to the low level at time T1 and is high at time T2, and therefore the strobe signal generating module 10 outputs the clock signal of the second clock period T2. At this time, the first trigger module outputs a handshake request signal to the data receiving terminal under the triggering of the clock signal of the second clock period T2, that is, outputs a high level to the data receiving terminal when the rising edge of the clock signal of the second clock period T2, and sets the high level to a low level when the handshake response signal sent by the data receiving terminal is received.

In the above embodiment, it is exemplified that there is the target data to be transmitted at the first clock cycle data transmitting end and the target data to be transmitted at the third clock cycle data transmitting end, and therefore, after time t0, the gate control signal is changed from low level to high level, after time t1, the gate control signal is changed from high level to low level, after time t2, the gate control signal is changed from low level to high level again, and after time t3, the gate control signal is changed from high level to low level again. That is, in the embodiment of the present disclosure, the target data to be transmitted by the data transmitting end is at least one clock period apart.

In addition, in the above embodiment, the example indicates that the strobe control signal valid is triggered by the rising edge of the clock signal clk1 of the data transmitting terminal to change the level, and in other possible embodiments, the strobe control signal valid may also be triggered by the falling edge of the clock signal clk1 of the data transmitting terminal to change the level, which is not specifically limited in the embodiments of the disclosure.

Further, in the embodiment of the present disclosure, the clock signal clk2 at the data receiving end has a frequency greater than the clock signal clk1 at the data transmitting end.

On the basis of the above embodiment, fig. 4 is a schematic structural diagram of another synchronous handshake circuit according to the embodiment of the present disclosure, AND as shown in fig. 4, the strobe signal generating module 10 includes a first Latch1 AND an AND gate AND; the data input end of the first Latch1 is connected with the gating control signal valid, the enabling end of the first Latch1 is connected with the clock signal clk1 of the data transmitting end, the output end of the first Latch1 is electrically connected with the first input end of the AND gate AND, the second input end of the AND gate NAD is connected with the clock signal clk1 of the data transmitting end, AND the output end of the AND gate AND is used for outputting a clock signal of a period.

Referring to fig. 3 and 4, the first Latch1 outputs the gate control signal received at the data input terminal at the high level, and the signal at the output terminal is kept unchanged at the low level of the first Latch 1. Illustratively, at time T0, the enable terminal of the first Latch1 is changed from low to high, AND at time T0, the gate control signal terminated by the data input of the first Latch1 is low, so that the first Latch1 outputs a low to the first input terminal of the AND gate AND, at time T01, the enable terminal of the first Latch1 is changed from high to low, thus, the first Latch1 keeps outputting a low level to the first input terminal of the AND gate AND, AND at time T1, the enable terminal of the first Latch1 is changed from a low level to a high level again, AND at time T1, the gate control signal terminated by the data input terminal of the first Latch1 is a high level, AND therefore, the first Latch1 outputs a high level to the first input terminal of the AND gate AND, AND the enable terminal of the first Latch1 is changed from a high level to a low level again at time T11, AND thus the first Latch1 keeps outputting a high level to the first input terminal of the AND gate AND, AND thus, the gate signal generating block 10 outputs a low level at the first clock period T1, AND the AND gate AND outputs a high level at the first half period of the second clock period T2, that is, the AND gate AND outputs a high level at time T1 to time T11, AND the AND gate AND outputs a low level at the second half period of the second clock period T2, that is, the AND gate AND outputs a low level at time T11 to time T2, that is, the AND gate AND outputs a clock signal of one period.

In a specific embodiment, with continued reference to fig. 4, the first trigger module 20 includes a first trigger D1, where a clock end of the first trigger D1 is connected to the strobe signal generating module 10 to receive a clock signal of a period, a data input end of the first trigger D1 is connected to a high level, an output end of the first trigger D1 is used for outputting the handshake request signal req, and a clear end of the first trigger D1 is used for receiving the handshake response signal ack.

The clock end of the first trigger D1 receives a clock signal of a period output by the strobe signal generating module 10, the data input end of the first trigger D1 receives a high level, when the clock end of the first trigger D1 receives a rising edge signal, the first trigger D1 outputs a handshake request signal, and the zero clearing end of the first trigger D1 is used for setting the handshake request signal to a low level when receiving a handshake response signal ack. That is, at time t1, the clock end of the first trigger D1 receives the rising edge signal, the first trigger D1 outputs the handshake request signal, the handshake request signal is at a high level, and at time t10, the clear end of the first trigger D1 receives the handshake response signal ack, and the first trigger D1 sets the handshake request signal from the high level to the low level.

On the basis of the above embodiment, fig. 5 is a schematic structural diagram of still another synchronous handshake circuit according to the embodiment of the present disclosure, as shown in fig. 5, where the synchronous handshake circuit further includes a memory module 30; the storage module 30 is configured to latch or register target data under the triggering of a clock signal of one cycle.

Wherein the memory module 30 comprises a second latch or register; the data input end of the second latch or register is used for receiving target data, the pulse input end of the second latch or register is connected with a clock signal of one period, and the output end of the second latch or register is used for latching or registering the target data.

Specifically, when the memory module 30 is a second latch, the data input from the data input terminal is latched when the clock signal input from the pulse input terminal is at a high level based on the characteristics of the latch, and since the pulse input terminal of the second latch is terminated with a clock signal of one period, the second latch latches the target data when the pulse input terminal of the second latch is at a high level period in which the clock signal of one period is received, and thus latches the target data in the second clock period T2, as shown in fig. 3 and 5. When the memory module 30 is a register, the data input from the data input terminal is registered when the clock signal input from the pulse input terminal is a rising edge based on the characteristics of the register, and the pulse input terminal of the register is connected with a clock signal of one period, so that when the pulse input terminal of the second latch receives the rising edge of the clock signal of one period, the register registers the target data, and thus the target data is registered in the second clock period T2.

The synchronous handshake circuit further comprises a storage module, latching or registering of target data is achieved based on the storage module, and after synchronous handshake is completed, the latched or registered data are sent to the data receiving end, so that safety of data transmission is improved.

On the basis of the above embodiments, the embodiments of the present disclosure further provide a data transmitting end, which includes the synchronous handshake circuit described in any of the above embodiments, and has the beneficial effects described in any of the above embodiments, which is not specifically illustrated in the embodiments of the present disclosure.

Based on the above embodiments, the data transmission system in conjunction with fig. 2 and fig. 4 includes: a data transmitting end 100 and a data receiving end 200; the data transmitting terminal 100 includes the synchronous handshake circuit according to any of the above embodiments; the data receiving end 200 includes a second triggering module 40, where the second triggering module 40 is configured to output a handshake response signal to the synchronous handshake circuit under the triggering of the clock signal clk2 of the data receiving end after receiving the handshake request signal req.

As a specific embodiment, as shown in fig. 4, the second trigger module 40 includes a second trigger D2, where a data input terminal of the second trigger D2 is configured to receive the handshake request signal req, a clock terminal of the second trigger D2 is connected to the clock signal clk2 of the data receiving terminal, and an output terminal of the second trigger D2 is configured to output the handshake response signal ack.

Specifically, referring to fig. 3 and fig. 4, the data input end of the second trigger D2 receives the handshake request signal req, the clock end of the second trigger D2 receives the clock signal clk2 of the data receiving end, when the request handshake signal req received by the data input end of the second trigger D2 is at a high level, and the clock signal clk2 of the data receiving end received by the clock end of the second trigger D2 is at a rising edge, the output end of the second trigger D2 outputs the handshake response signal ack, and at this time, the clear end of the first trigger D1 in the synchronous handshake circuit sets the handshake request signal req at a low level when the handshake response signal is received.

In the embodiment of the disclosure, after receiving the handshake request signal, the data receiving end outputs the handshake response signal to the first trigger module of the synchronous handshake circuit after beating the handshake request signal, and when receiving the handshake response signal, the first trigger module sets the handshake request signal output to the data receiving end to be low level, so as to complete the primary synchronous handshake circuit, realize synchronous handshake of the data transmitting end and the data receiving end in a clock signal of one period, reduce handshake duration of the handshake of the data transmitting end and the data receiving end, and improve data processing speed.

As another specific embodiment, as shown in fig. 6 or fig. 7, the second trigger module 40 includes a plurality of third flip-flops D3 connected in sequence, where, among the plurality of third flip-flops D3 connected in sequence, an output terminal of a previous third flip-flop D3 is connected to a data input terminal of a next third flip-flop D3, a clock terminal of each third flip-flop D3 is connected to a clock signal clk2 of a data receiving terminal, a data input terminal of the first third flip-flop D3 is used for receiving the handshake request signal req, and an output terminal of a last third flip-flop D3 is used for outputting the handshake response signal ack.

Specifically, referring to fig. 6 and 8, or fig. 7 and 8, the data input terminal of the first third flip-flop D3 is electrically connected to the output terminal of the first flip-flop D1, the data input terminal of the second third flip-flop D3 is electrically connected to the output terminal of the first third flip-flop D3, the clock terminal of the first third flip-flop D3 and the clock terminal of the second third flip-flop D3 terminate the clock signal clk2 of the data receiving terminal, and the output terminal of the second third flip-flop D3 is electrically connected to the clear terminal of the first flip-flop D1. When the request handshake signal req received by the data input terminal of the first third flip-flop D3 is at a high level and the clock signal clk2 of the data receiving terminal received by the clock terminal of the first third flip-flop D3 is at a rising edge, the output terminal of the first third flip-flop D3 outputs a first signal, and when the first signal req_d1 received by the data input terminal of the second third flip-flop D3 is at a high level and the clock signal clk2 of the data receiving terminal received by the clock terminal of the second third flip-flop D3 is at a rising edge, the output terminal of the second third flip-flop D3 outputs a handshake response signal ack, and at this time, the clear terminal of the first flip-flop D1 in the synchronous handshake circuit sets the handshake request signal req to a low level when the handshake response signal is received.

In the embodiment of the disclosure, after receiving the handshake request signal, the data receiving end outputs the handshake response signal to the first trigger module of the synchronous handshake circuit after beating the handshake request signal for two beats, and when receiving the handshake response signal, the first trigger module sets the handshake request signal output to the data receiving end to be low level, so as to complete the primary synchronous handshake circuit.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence number of each step/process described above does not mean that the execution sequence of each step/process should be determined by its functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. Moreover, the foregoing description of the embodiments of the application is provided for the purpose of illustration only, and does not represent the advantages or disadvantages of the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be capable of being practiced otherwise than as specifically illustrated and described. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The foregoing description of the preferred embodiments of the present disclosure is provided only and not intended to limit the disclosure so that various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims (10)

1. A synchronous handshake circuit for use at a data transmitter, comprising: the gating signal generation module and the first triggering module;

the strobe signal generation module is configured to select a clock signal with a period from the clock signals of the data sending end to output to the first trigger module under the control of a strobe control signal;

The first trigger module is configured to output a handshake request signal to a data receiving end under the triggering of the clock signal of one period until the handshake response signal sent by the data receiving end is received, and the handshake request signal is stopped being output.

2. The synchronous handshake circuit according to claim 1, wherein when the data transmitting terminal has target data to be transmitted, the strobe control signal is triggered by a rising edge of a clock signal of the data transmitting terminal to change a level so that a high-level pulse width of the strobe control signal is a clock period of the clock signal of the data transmitting terminal at this time;

the gating signal generation module is configured to determine whether to output a clock signal with a period to the first trigger module according to the level of the gating control signal when the clock signal of the data sending end rises.

3. The synchronous handshake circuit of claim 1 wherein the strobe signal generation module comprises a first latch and an and gate;

the data input end of the first latch is connected with the gating control signal, the enabling end of the first latch is connected with the clock signal of the data transmitting end, the output end of the first latch is electrically connected with the first input end of the AND gate, the second input end of the AND gate is connected with the clock signal of the data transmitting end, and the output end of the AND gate is used for outputting a clock signal of a period.

4. The synchronous handshake circuit according to claim 1, wherein the first trigger module comprises a first trigger, a clock end of the first trigger is connected with the strobe signal generating module to receive the clock signal of the period, a data input end of the first trigger is connected with a high level, an output end of the first trigger is used for outputting the handshake request signal, and a zero clearing end of the first trigger is used for receiving the handshake response signal.

5. The synchronous handshake circuit according to claim 1, further comprising a memory module;

The storage module is configured to latch or register the target data under the triggering of the clock signal of one period.

6. The synchronous handshake circuit of claim 5, wherein the memory module comprises a second latch or register;

The data input end of the second latch or the register is used for connecting the target data, the pulse input end of the second latch or the register is connected with the clock signal of one period, and the output end of the second latch or the register is used for latching or registering the target data.

7. A data transmitting terminal comprising the synchronization handshake circuit of any of claims 1-6.

8. A data transmission system, comprising: a data transmitting end and a data receiving end;

The data transmitting end comprises the synchronous handshake circuit according to any of claims 1-6;

The data receiving end comprises a second triggering module, and the second triggering module is configured to output the handshake response signal to the synchronous handshake circuit under the triggering of a clock signal of the data receiving end after receiving the handshake request signal.

9. The data transmission system of claim 8, wherein the second trigger module comprises a second trigger, a data input of the second trigger is configured to receive the handshake request signal, a clock of the second trigger is terminated with a clock signal of the data receiving terminal, and an output of the second trigger is configured to output the handshake response signal.

10. The data transmission system of claim 8, wherein the second trigger module comprises a plurality of third triggers connected in sequence,

The output end of the last third trigger is connected with the data input end of the next third trigger, the clock end of each third trigger is connected with the clock signal of the data receiving end, the data input end of the first third trigger is used for receiving the handshake request signal, and the output end of the last third trigger is used for outputting the handshake response signal.