JPH05315971A - Serial/parallel conversion circuit - Google Patents

Abstract

PURPOSE:To obtain a serial/parallel(S/P) conversion circuit by a shift register and a simple circuit without using a counter. CONSTITUTION:At the time of resetting the shift register 3, the values of respective bits are set up so that only the least significant bit has a value different from other bits like '0001' and then the propagation of the least significant bit is detected by a data change detecting circuit 4. Since the size of the circuit 4 is smaller than that of a counter and is not changed even the number of bits to be S/P converted is increased, A compact S/P conversion circuit can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial-parallel conversion circuit for converting serial data of digital signals into parallel data.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional 4-bit serial-parallel conversion circuit. 1 is a 4-bit shift register,
2 is a 2-bit counter, and C is a carry output of the counter. FIG. 4 shows a time chart of the conventional 4-bit serial-parallel conversion circuit of FIG.

First, the reset (RESET) terminal is set to "L" to reset the circuit. Next, the RESET terminal is set to "H" to wait for data. After that, the data (DAT
Serial data is input to the A) terminal, and a timing clock for receiving the serial data is input to the CK terminal. This timing clock is also input to the 2-bit counter 2 at the same time to perform a counting operation. The serial data input from the DATA terminal is shifted in the shift register 1 by the timing clock, and the 2-bit counter 2 outputs a carry at the same time when the input of 4 bits of data is completed. With this carry, the serial-parallel conversion is completed to another circuit block, and an RDY signal indicating that it can be used as parallel data is set. The other circuit block receives this signal, reads the parallel data from the D0 to 3 terminals, and then resets it. The terminal is set to "L" and the circuit is reset. Further, the RESET terminal is set to "H" to wait for the next data.

[0004]

However, in the above configuration, the counter is used to generate the RDY signal indicating the completion of the serial-parallel conversion to the other circuit block, which is complicated and large. If the scale becomes large and the number of bits of data to be serial-parallel converted increases, there is a problem that the counter also requires a larger counter.

The present invention solves the above-mentioned conventional problems, is simple and has a small circuit, and even if the number of bits of data to be serial-parallel converted increases, it is sufficient to increase the number of bits of the shift register. -The purpose is to realize a parallel conversion circuit.

[0006]

In order to achieve this object, the serial-parallel conversion circuit of the present invention has a shift register in which a specific value is preset at the start of data input, and a change in data at the final stage. It is composed of a detection circuit.

[0007]

By virtue of the above-described structure, the present invention does not require a counter circuit, which is required in a conventional serial-parallel conversion circuit, but instead uses a simple circuit for detecting a change in data, thereby performing serial-parallel conversion. A circuit can be realized.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a 4-bit serial according to the present invention.
An example of a parallel conversion circuit is shown. Reference numeral 3 is a 4-bit shift register, and 4 is a circuit for detecting that data has changed from "0" to "1".

FIG. 2 is a time chart of the 4-bit serial-parallel conversion circuit according to the present invention shown in FIG. First, the RESET terminal is set to "L", the shift register 3 is preset to "0001", and the data change detection circuit is reset. Next, the RESET terminal is set to "H" to wait for data. After that, serial data is
A timing clock for receiving serial data is input to the K terminal. The data input from the data terminal propagates through the shift register 3 by this timing clock. At this time, the first preset “000
The data of "1" is also propagated, and at the same time as receiving the data of 4 bits, the data of "1" which is the least significant bit of the preset "0001" is propagated through the data change detection circuit 4. The output of the circuit 4 Is sent to another circuit block as an RDY signal indicating that the serial-parallel conversion is completed and it can be used as parallel data.The other circuit block receives this signal and reads the parallel data from terminals D0 to 3 and then Set the RESET terminal to "L"
Then, the shift register is preset and the data change detection circuit 4 is reset. Furthermore, set the RESET terminal to "H"
And wait for the next data. It is needless to say that the preset value of the shift register 3 in FIG. 1 may be “1110” and the data change detection circuit 4 may be a circuit for detecting the change from “1” to “0”.

[0011]

As described above, according to the present invention, a shift register in which a specific value is preset at the start of data input and a circuit for detecting a change in data at the final stage of the shift register are used. A serial-to-parallel conversion circuit that does not require a counter circuit that was necessary for the circuit, is simple and small, and only needs to increase the number of bits in the shift register even if the number of bits of data to be serial-parallel converted increases. realizable.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a serial-parallel conversion circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of the serial-parallel conversion circuit shown in FIG.

FIG. 3 is a diagram showing an example of a configuration of a conventional serial-parallel conversion circuit.

4 is a timing chart of the serial-parallel conversion circuit shown in FIG.

[Explanation of symbols]

 1 shift register 2 2 bit counter 3 shift register 4 data change detection circuit

Claims (1)

[Claims] 1. A serial-parallel conversion circuit comprising a shift register in which a specific value is preset at the start of data input, and a circuit for detecting a change in data at the final stage thereof.