JPS59172104A - Digital data envelope controlling circuit - Google Patents

Abstract

PURPOSE:To perform prescribed envelope control with digital data as it is by a simple circuit which can be formed of an IC by shifting the digital data in the direction of an LSB by the prescribed number of bits. CONSTITUTION:A counter 15 is counted down by the output 100 of a 0-detecting circuit 16 from the time when the content of the counter 15 is set to a number other than zero until the content is reduced to zero. The counting pulse of the counting down a shift clock 102 and the data of a shift register 18 with an M-bit strobe are shifted in the direction of an LSB by a set number of counting. The shifted data are latched by an M-bit latch circuit 19 synchronously to a strobe 104 and outputted as digital data 107. That is to say, by shifting the digital data to the direction of the LSB 1-bit by 1-bit, the analog-converted quantity can practically be attenuated 1/2 by 1/2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a digital data envelope in which data envelope control is performed using digital data in a data system that obtains analog data output from digital data. - Regarding control circuits.

(Prior art) In recent years, as in digital audio, data signals (hereinafter simply referred to as data), which were conventionally treated as IJ near circuits, have been converted into digital data and processed, resulting in low distortion rates. It has become increasingly possible to obtain high-fidelity systems with low noise and sound quality.

By the way, in such a system, for example, an audio signal can be faded in or faded out.

Envelope control of data such as mute is
As shown in the block diagram of the system in FIG. 1(a), after converting digital data 1 to analog data, an analog data envelope control circuit (referred to as analog DECC) 2 converts the digital data to a predetermined envelope. After the control is performed, it is output as analog data 4. This is because the data envelope control circuit usually uses a CR circuit 3 shown in FIG.

However, according to such conventional methods, even though the audio signal has been digitized and subjected to high-fidelity processing, there is a strong possibility that the high-fidelity characteristics will be impaired by mixing such analog circuits. That is, the occurrence of distortion and low-level noise due to the nonlinear characteristics of the C-type circuit cannot be ignored. Furthermore, when converting the circuit into an IC, it is difficult to convert the CB and the circuit into an IC at the same time and they must be used as external components, which is a factor that hinders miniaturization of the entire device. Therefore, a digital data envelope control circuit (referred to as DECC 91) is used instead of the conventional analog DECC2 as shown in FIG. 1(b) where such problems do not occur.
2' is strongly desired to be realized.

(Object of the Invention) An object of the present invention is to provide a digital DECC that satisfies the above-mentioned demands and allows a predetermined envelope control to be performed using digital data as is, using a simple circuit that can be integrated into an IC. It's about doing.

(Structure of the Invention) The circuit of the present invention is a digital data circuit in which one data is composed of M bits.
2. ...M) A shift clock circuit that outputs a bit shift Φ clock, and the output of the shift clock circuit is input, and the system digital data is shifted in the N bit L8B direction as digital own data. It consists of a digital data shift circuit for outputting and a timing circuit for controlling the timing of these circuits.

(Example) 5- Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing a circuit according to an embodiment of the present invention. This embodiment includes a clock inhibit circuit 11, a digital
It is composed of a data shift circuit 12 and a timing circuit 13.

The shift clock circuit 11 includes a counter 15 that can count up to M, a counter content setting circuit 14 that sets the content of the counter 15 from O to Mt, an O detection circuit 16 of the counter 15, and a counter content setting circuit 14 that sets the content of the counter 15 from O to Mt. The clock inhibiting circuit 17 inhibits the input of the system clock 101 of the counter 15 through the output 100, and the input from the counter content setting circuit 14 synchronizes with the first strobe 103. N set to a given value
The bit shift clock 102 is digitized and output to a 7-bit register with an M-bit S strobe that constitutes a data shift circuit.

The digital data shift circuit 12 receives the shift clock 1026- from the shift clock circuit 11 and receives the first strobe 103 from the timing circuit 13.
M bits of digital data inputted in synchronization with the M bit are output as digital data 106 shifted by a predetermined N bits in the LSB (least significant bit of data) direction.
This will be explained with reference to a digital timing chart with a bit strobe and shifted by seven in synchronization with the second strobe 104 from the timing circuit 20. It is assumed that one data (word) is composed of 8 bits.

In FIG. 3, (1) is the system clock 107, (
2) is the system output data 105, and (3) is the first strobe 103. r4) is the second strobe 104 waveform.

(5) is the external setting counter content 108, N = 5.6.7
is set.

The counter content setting circuit 14 sets the externally set counter content in synchronization with the first strobe 103 from the timing circuit 20 . (See Figure 3 (6) d) The M-bit system output digital data 105 is
If you leave this as is and add a D/A converter after this,
This data 105 is a digital signal from which an analog signal is obtained at the output of the D/A converter, and this data 105 is strobed into the shift register 18 with an M-bit strobe in synchronization with the first strobe 103 of the timing circuit 20. When the contents of 15 are set to other than 0, O
According to the output 100 of the detection circuit 16, the clock inhibition circuit 1
When the prohibition of 6 is removed, the counter 15 counts down until it reaches 0. At the same time, this count pulse becomes the 77-talk clock 102 of the M-bit shift register 18, and the data in the M-bit strobe shift register 18 is LSB for the set count number.
shifted in the direction. (See Figure 3 (7) and (8).) The M-bit strobe shift unit after the shift has been completed.
The contents of register 18 are the second
%M bit latch circuit 1 in synchronization with strobe 104
9 and output as digital f-71s power 107. (See Figure 3 (9).) By the way, in the above operation, shifting the contents of the digital fist data in the analog When converted to a quantity, the analog quantity is halved.
It corresponds to doing.

Note that if the bit located in the LSB is 1.

It is not exactly 1/2 because it is truncated by 7 points,
Although it is only approximately 1/2, it is usually determined appropriately depending on the size of data to be handled, such as by selecting a fixed point at the center of M bits, so shift it one bit at a time in the LSB direction. Therefore, the analog equivalent amount is substantially attenuated by 1/2. Also, if the most significant bit of digital data, which is 1, is fi N / bits higher than the LSB, then if the data is shifted in the N' bit LSB direction, the digital data becomes OO...0. , the analog conversion amount becomes 0.

That is, if the data has an M-bit structure, in principle, by shifting the M-bits in the LSB direction, the analog conversion amount becomes O, that is, meets.

The series of operations described above is an analog output waveform diagram showing an embodiment in which the digital data envelope is actually controlled to sweep one data, and it is converted into an analog output.

Here, for simplicity, system output digital data 1
05, a signal whose envelope becomes constant when converted into an analog quantity was used.

10- Also, the time interval of bit shifts such as s'1stl*'3 was made sufficiently long compared to twoRD.

First, when the external setting counter content (2) is 0, the envelope of the system output data (rl) becomes the envelope of the analog output data (3) of the circuit.
/ Next, set the contents of 1 counter 15 to 111, 121. ...1
As you set N1, the output data (
3) envelope is 1/2.1/4 of the system data envelope. ...It is reduced by 1/2. When N=M, the amplitude becomes O, meaning complete muting.

Note that the external setting counter content "3" shown at the right end of Figure 4
In the case of ", it is a change from the previous counter content M. In this way, bit shifting does not have to be done one bit at a time as explained above, but any value between 1 and M can be changed. Can be set.

In the above description, detailed explanations of counters, shift registers, latch circuits, etc. are omitted because they can be easily formed using known techniques. Also, in addition to the circuit configuration used in the example,
The shift clock circuit 11 and the digital data shift circuit 12 can be configured according to appropriate configurations.

(Effects of the Invention) As described above in detail, the circuit of the present invention can perform digital data envelope control by shifting digital data by a predetermined number of bits in the L8B direction. When applied to conventional digital/analog data systems such as digital audio,
After the data is once converted to analog data, it is no longer necessary to perform envelope controls such as analog data in, fade out, and mute. Therefore, there is no fear that the high fidelity characteristics will be impaired due to the associated reduction in distortion rate, generation of low-level shoe sounds, etc. Furthermore, there is no need to use an external CR circuit as in the conventional case. Furthermore, since the circuit of the present invention is composed of a simple digital circuit that can be easily formed, the I.
It is easy to convert into C and contributes to miniaturization of the entire device.

That is, the circuit of the present invention can be used in a digital/analog data system to perform isometric envelope control circuits without sacrificing the high fidelity characteristics of digital data.
A data number envelope control circuit can be provided, and its effects are great.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are waveform diagrams showing examples of digital/analog data output waveforms. 13- In the figure, 1... digital data, 2...
...Analog data envelope 0 control circuit (analog DECC), 2/...Digital data envelope control circuit u (digital DECC), 3. Group CR circuit, 4. Old...
Analog data, 11...Shift clock circuit, 12...Digital data shift circuit, 13...Timing circuit, 14...
・Counter content setting circuit, 15...Counter,
16...0 detection circuit, 17...clock prohibition circuit, 18...M-bit□shift register with strobe, 19...group M-bit latch circuit, 20 ...Timing circuit, 100...
・0 detection circuit output, 101...System clock, 102...Foot conflict lock, 103...
Old...＼ h1 country'' 20th 4th flash 1t 20-

Claims (3)

[Claims] (1) In a digital data circuit where one piece of data is composed of M bits, a predetermined number of N (N=1°2, . . .
M) A shift clock circuit that outputs a bit shift e clock, and a shift clock circuit that receives the output of the shift clock circuit and converts the input system digital data to N bits L8B.
A digital data envelope control circuit comprising: a digital data shift circuit that outputs digital data shifted in the direction; and a timing circuit that controls the timing of these circuits. (2) The shift clock circuit includes a counter that can count up to M, a counter content setting circuit that sets the contents of the counter from 0 to M, a 0 detection circuit of the counter, and an output of the O detection circuit. 2. The digital data envelope control circuit according to claim 1, further comprising a clock inhibiting circuit for inhibiting system clock input to said counter. (3) The digital data shift circuit strobes the digital data input from the system one data at a time, and shifts the data contents in the N-bit L8B direction using the shift clock from the seven clock circuits. An M-bit strobe-equipped shift register for shifting, and an M-bit latch circuit for latching the contents of the strobe-equipped shift register and making it the final digital data output of the system. A digital data envelope control circuit according to claim (1).