JP3263110B2 - Store merge control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a case where two store accesses to the same address of a main storage device are successively performed.
The present invention relates to a store merge control method for writing one store data into a main storage device after merging the main storage control device into one store data. Main memory controller (MC
When a store access to the main storage device is received from the processing device in U), a store access to the same access address may be continuously received during the store access operation.

In such a case, rather than performing store access twice one by one, it is possible to perform one store merge by combining two store data for the same address into one.
It is only necessary to execute the store access twice, and the access performance of the main storage device can be improved. However, merging store data requires a data merging mechanism for each port, resulting in an increase in the amount of hardware, and in a short time until the priority of a request temporarily stored in a priority queue or the like is obtained. If the subsequent store access is not obtained, merging cannot be performed, and the merge validity period allowed for the preceding access is short, so there are few opportunities for merging. No performance improvement can be expected, and improvement of this point is desired.

[0003]

2. Description of the Related Art FIG . 18 is an explanatory diagram of a main storage control device in which a conventional store merge control method is performed. In FIG. 18 , a CPU (not shown) is
Are connected, and three of the processing units 14A to 14C are connected to the pre-port units 16 and 18
And the remaining processing devices 12D are directly connected to the ports.

A store access from the processing device is divided into a request for the priority circuit unit 20, and a store data and a byte mark BM for the store data unit 22. The store merge is performed for store accesses from the processing devices 14A to 14C connected to the preports 16 and 18.

The pre-port unit 16 has a request queue 24 for temporarily holding a request received in a busy state due to a port full in the priority circuit unit 20. The store merge is performed using a period in which the request is held in the pre-portion section 16 as a merge valid period. Also, the merging targets are partial store comrades.

There are two types of store access to the main storage device 10: full store and partial store (partial store). FIG. 21A shows a full store. Assuming that the data of the access address of the main storage device 10 is, for example, 8 bytes (= 64 bits), the CPU as the processing device sets the 1-byte unit as the minimum unit. Store access is possible, and access by store data in which all bytes of the 8-byte store data are valid is called full store. In the case of the full store, the store data is written to the access address of the main storage device 10 as it is.

FIG. 18 (b) shows a partial store, in which the CPU accesses by using stored data in which some of the bytes indicated by hatching in the 8-byte stored data are valid data. In the case of this partial store,
Fetch data is obtained by fetching an access address of the main storage device 10, and store data obtained by merging the fetch data and the store data (partial) is written to the access address of the main storage device 10, and only the hatched portion is written. Perform partial store to rewrite.

Referring again to FIG. 17 , the priority circuit section 20 takes priority between the pre-port section 16 and the processing unit 14D to obtain an access pipeline section 26.
And the main storage interface unit 28 controls the main storage device 10 according to the processing of the access pipeline 26. The store data and the byte mark BM from the pre-portion unit 18 are synchronized with the operations of the priority circuit unit 20 and the access pipeline unit 26, and the data queue of the partial data is merged by the data merge unit 30 of the store data 22. 32, and stored in the data queue 32 at a predetermined timing of the access pipeline unit 26.
Is sent to the main storage device 10 and written to the access address.

Reference numeral 34 denotes a load data unit which, when receiving a load access request, sends a request from the priority circuit unit 20 to the access pipeline unit 26 to transfer data from the access address of the main storage device 10. Load access for reading and sending to the processing devices 14A to 14D is performed.

[0010]

However, in such a conventional store merge control method, a data merge section 30 is provided in the store data section 22, and the merged store data is written into the data queue 32. Therefore, the hardware amount of the data merging mechanism that performs the merging process in units of 8 bytes up to a maximum of 8 bytes is large, resulting in an increase in circuit size and cost.

In the conventional store merge control method, since partial store accesses are merged using a merge circuit, there are few cases where store merge can be performed, and there is a problem that the access performance is not sufficiently improved. Further, in the conventional store merge control method, the store merge can be performed only during the period in which the pre-store unit 16 holds the preceding store access, so that the store merge timing is short, and the store merge opportunity is small, so that the processing performance is improved. Was inadequate.

SUMMARY OF THE INVENTION The present invention has been made in view of such conventional problems, and has been made to improve the main memory access performance by increasing the period and case of store merging without increasing the amount of hardware. An object is to provide a merge control method.

[0013]

FIG. 1 is a diagram illustrating the principle of the present invention. First, the present invention is directed to a store merge control method of an information processing device including a main storage device 10, a main storage control device 12, and a plurality of processing devices 14. According to the present invention, as such a store merge control method, the main storage control device 12 holds an access address of a preceding store access, and compares it with an access address of a subsequent store access to detect an address match. The match detection unit 1 determines whether the store access is a full store that rewrites all data of the main memory access address or a partial access that rewrites a part of the main memory access address, and determines in advance between the preceding store access and the subsequent store access. A store access determining unit 2 for determining that a continuous relationship between the full store and the partial store has been obtained, and an address of a succeeding store access by validating an access address of a preceding store access held in the address match detecting unit 1. Prev address valid signal to be compared with And a store merge operation when three conditions of a match of an access address when a subsequent store access is received, a predetermined continuous relationship between a full store and a partial store, and a preceding address valid signal are satisfied. Is provided.

The store merge start signal is supplied to the byte mark merging unit 5, and merges byte marks indicating valid bytes of each store data of the preceding store access and the subsequent store access. At the same time, the store data merging unit 6 merges the store data of the preceding store access and the subsequent store access. When the store merge is completed, the access execution unit 9 writes the merged byte mark and store data to the main storage device 10 at a predetermined timing after the priority of the preceding store access is taken by the priority circuit unit 20.

Here, the store access determination unit 2 determines a first condition that the preceding store access is a full store and a subsequent store access is also a full store, a second condition that the preceding store access is a partial store and the subsequent store access is also a partial store, third condition preceding store access subsequent store access is full store partial store, and Article 4 reviews the preceding store access is subsequent store access is partial store full store, Izu <br/> Re or is When the condition is satisfied, it is determined that the continuity of store access for performing store merge has been obtained.

The valid signal control unit 3 propagates a reset flag used for reset control of the preceding address valid signal together with an access address, an operation code, and a control flag obtained by a store access request, and the reset flag is transmitted to a predetermined propagation position. Is reached, the preceding address valid signal is reset to end the valid period for merging with the preceding store access.

The byte mark merging unit 5 outputs the current held data after the merge start signal is received, and then holds the input data. When the merge start signal is received, the byte mark merge unit 5 outputs the current held data and simultaneously outputs the current held data. A byte mark merge circuit 78 for holding logical sum data obtained by calculating the logical sum of the held data and the input data is provided at the input stage of the data queue, so that merging by the data queue is unnecessary.

In this case, the byte mark merging section 5 has an in queue counter which counts up by one each time a byte mark is input and specifies the storage position of byte data in the data queue. After counting up the queue counter, all the bits of the byte mark are input and written. When a merge start signal is received, all the bits of the byte mark are input and written without counting up the inque counter.

The byte mark merging section 5 can also merge byte marks in a data queue. In this case, the byte mark merging circuit is simply a shift register. When the byte mark is input and written to the data queue after being up and a merge start signal is received,
Only the valid bit of the byte mark may be input to the data queue and written without counting up the in queue counter.

The store data merging unit 6 further includes a data queue for temporarily storing store data, and an in-queue counter for counting up by one each time the store data is received and designating a storage position of the store data in the data queue. If the merge start signal does not exist, the byte counter is counted up and then all the byte data is input to the data queue and written.When the merge start signal is received, the byte mark is counted up without counting up the in queue counter. By inputting and writing only the byte data specified by the valid bit, two consecutive store data are merged.

For this reason, the out queue counter provided in each data queue for the byte mark and the store data is controlled so as to read out the data stored in the data queue after counting up.

According to the store merge control system of the present invention having such a configuration, the following operation can be obtained.

First, store data is merged using a data queue for temporarily storing store data, as in the case of byte mark merge. Therefore, it is not necessary to provide a merge mechanism for each port. The amount of hardware will be greatly reduced.

The relationship between the preceding store access and the subsequent store access for performing store merging is as follows: (1) preceding full store access + subsequent full store access (2) preceding partial store access + subsequent partial store access (3) preceding partial store access + By expanding to subsequent full store access, the number of cases where store merging can be performed increases, and the access performance to the main storage device can be improved.

Further, conventionally, merging can be performed only while the pre-store access request is held in the pre-portion portion. However, at least the prior-store access priority is acquired and the store data is stored during this mergeable period. Until the store can be merged, increasing the frequency with which store merging is possible,
Improve the access performance of the main storage device.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [Table of Contents] 1. Overall configuration and configuration of main memory control device 2. Configuration of store merge control Access conditions for performing store merge Specific example 5 of store merge Store merge of start-up conditions 6. Merge processing 7 of byte mark and store data. Control of the data queue 8. Operation of store merge 9 . Other merge processing of byte mark

1. FIG. 2 is a block diagram of an embodiment of an information processing apparatus to which the store merge control method of the present invention is applied.

In FIG. 2, reference numeral 10 denotes a main memory (MS)
U) and 12 are main storage control units (MCUs), and the processing unit 1 including a CPU 14A for the main storage control unit 12
4B to 14D are connected. FIG. 3 is a block diagram of an embodiment of the main storage control device 12 of FIG. In FIG. 3, 16
Is a request pre-portion unit, which receives requests from the CPU 12A and the processing devices 12B and 12C in this embodiment. When receiving a request from the device to the main storage device 10, the preporter 16 outputs the request to the priority circuit unit 20 directly or via a request queue.

A request from the pre-port unit 16 and a request from the processing unit 12D are given to the priority circuit unit 20, and when two requests are received at the same time, the priority of one request is taken according to a predetermined procedure, and the access pipeline unit 26 Output to

A pre-portion section 18 for data is provided corresponding to the pre-portion section 16 for request. The CPU 12A, the processing devices 12B, 1
Data from 2C is provided. The pre-portion section 18 outputs the data of the device corresponding to the request output to the priority circuit section 20 to the store data section 22 in synchronization with the pre-portion section 16 for the request. The data from the pre-portion unit 18 and the processing device 1 are stored in the store data unit 22.
Data from 2D is provided.

Here, the CPU 12A and the processing unit 12B
As data from .about.12D, store data and byte marks BM indicating valid bytes of the store data are given. In this embodiment, the store data from the CPU 12A and the processing devices 12B to 12D has a data length of 8 bytes, and at the time of store access, full store access using all 8 bytes of data as store data, or 8 bytes of Partial store access is performed to validate only byte data of 1 to 7 bytes.

The byte mark BM is set to all 1s in the store access, indicating that all bytes of the store data are valid. In the partial store access, the bit corresponding to the valid byte is 1, and the bit corresponding to the invalid byte is 1. It becomes 0. The access whose priority is taken by the priority circuit unit 20 is input to the access pipeline unit 26, and executes a store access or a load access through a pipeline cycle.

That is, a control signal obtained in a predetermined cycle of the access pipeline section 26 is supplied to the main storage device 10 via the main storage address interface section 28. And store data to the access address.

On the other hand, in the case of load access, an access address of the main storage device 10 is designated and the load data unit 34 is specified.
, And sends the load data to either the CPU 12A or the processing devices 12B to 12C that issued the load access request.

The store access to the main storage device 10 includes a full store access and a partial store access. As shown in FIG. 18 , in the full store access, the store data is written to the access address of the main storage device 10 as it is. In the access, the data of the access address of the main storage device 10 is fetched into an internal register of the main storage device 10 and merged with the store data, and the store data obtained by the merge is written into the main storage device 10. Become like The merge at the time of the partial store access is different from the store merge control of the present invention, and is a merge process naturally performed in the partial store access.

2. Configuration of Store Merge Control FIG. 4 is a configuration diagram of an embodiment in which a circuit unit for store merge control of the present invention provided in the main storage control device 12 of FIG. 3 is extracted and shown. In the embodiment shown in FIG.
The circuit system of store access from U12A is shown as a representative.

In FIG. 4, the request pre-port section 16 is provided with a request input register 36 for storing a request from the CPU 12A. A request by the store access from the CPU 12A to the request input register 36 has a format configuration shown in FIG.

In FIG. 5, V is a request valid, which indicates that the request is valid. Next AD
R is an access address of the main storage device 10. For example, if the main storage device 10 is 1 GB,
The address data is obtained by adding 4 bits P0 to P3 to the bits.

The next OPC is an operation code. In the store merge control of the present invention, the operation code 0100 indicates full store access, and 0101 indicates partial store access. Further, CFLG is a control flag.

Referring again to FIG. 4, following the request input register 36, a pre-port register 38 is provided. A pre-port request queue 4 is provided between the request input register 36 and the pre-port register 38.
0 is provided. The pre-request queue 40 is divided into eight storage areas in this embodiment.
When the preceding request is stored in the pre-port register 38, the succeeding request is stored in the pre-port request queue 40.

The storage location of the report request queue 40 is specified by an in-queue counter. That is, after storing the request in the report request queue 40, the in-queue counter is incremented by one, and the request is stored in the storage position of the report request queue 40 specified by the in-queue counter. Further, the preceding request of the pre-port register 38 is output to the priority circuit unit 20 side, and the pre-request request queue 4
When outputting the subsequent request that is held from 0,
This is performed by incrementing the out queue counter by one after the output of the request.

The pre-port register 38 stores the output of the request input register 36 and the pre-port request queue 4
0 is input, and the output of the input port register and the output of the pre-port request queue from the other processing devices are also given in the same manner. Therefore, the pre-port register 38 also provides the pre-port unit 16 with the function of determining and prioritizing requests. Have

C output from the pre-port register 38
The request from the PU 12A is sent to the priority circuit 2
0 is held in the port register 42. A request queue 44 is provided at a stage preceding the port register 42, and when a preceding request is held in the port register 42, a subsequent request is stored in the request queue 44.

When the priority of the request in the port register 42 is taken and output to the access pipeline 26, the subsequent request in the request queue 44 is sent to the port register 42, and waits for the acquisition of the next priority. In this embodiment, the access pipeline unit 26 is composed of, for example, seven cycles CYC1 to CYC7, and among these, the cycles CYC1, CYC2, and CYC
7 shows registers 46, 48, and 108 for three cycles. The next main memory address interface 28 is provided with a store access register (SAR) 110, and the store access is executed in the eighth cycle after the priority circuit unit 20 acquires the priority of the request.

Referring again to the pre-port section 16, in order to realize the store merge control of the present invention, a preceding access address register 50 for storing an access address of the preceding access is provided. When the request is transferred from the request input register 36 to the pre-port register 38, the access address ADR in the request shown in FIG. 5 is set in the preceding access address register 50.

The preceding access address register 50 is provided with a valid bit V. If the valid bit V is 1, the access address ADR stored in the preceding access address register 50 is effective in the store merge control of the present invention. If the valid bit V is 0, it means that it is ignored as the preceding access address of the store merge.

Subsequent to the preceding access address register 50, a comparison section 52 is provided. The comparing unit 52 compares the access address ADR1 of the preceding access stored in the preceding access address register 50 with the access address ADR2 given by the subsequent access request held in the request input register 36, and compares the two access addresses ADR1. When ADR2 and ADR2 match, a match output is given to the store merge activation unit 54.

Here, the preceding address access register 5
The address coincidence detection unit 1 shown in FIG. In addition, the report unit 1
6 is provided with an operation code register 56 and an access judgment unit 58 as a circuit unit for judging the continuity relation between the partial store and the full store for performing the store merge of the present invention.

The operation code register 56 sets the operation code in the request shown in FIG. 5 in synchronization with the timing at which the request is transferred from the request input register 36 to the pre-port register 38, ie, in synchronization with the set timing of the preceding address access. Therefore, the access determination unit 58 sets the operation code OPC in the previous access request immediately before the operation code register 56 with the next request set in the request input register 36.
1 and the operation code OPC2 of the subsequent request.

3. Access Condition for Performing Store Merge The access determination unit 58 in FIG. 4 determines whether the store access is a partial store access or a full store access from the opcode OPC1 of the preceding access and the opcode OPC2 of the subsequent access, and determines the following four relationships. Is obtained, a determination signal for causing the store merge activation unit 54 to perform the store merge is output.

(1) preceding full store access + subsequent full store access; (2) preceding partial store access + subsequent partial store access; (3) preceding partial store access + subsequent full store access; (4) preceding full store access + Subsequent partial store access;

4. Specific Example of Store Merge First, the case where the change of the operation code in the preceding access request (1) to (4) does not need to be changed is shown in FIG.
This will be described with reference to FIGS. FIG. 6 shows the merging process in the case of (1) (preceding full store access) + (subsequent full store access).

In FIG. 6, preceding store data in which all bytes are valid is obtained by preceding full store access, and subsequent succeeding store data in which all bytes are also valid are obtained by subsequent full store access having the same access address. As shown in (1) and (2), merging is performed in such a manner that the preceding store data is masked by the subsequent store data, and the merged data is combined into one store data.

Here, it is only necessary to discard the succeeding request of the preceding request of the preceding store data and the succeeding request of the succeeding store data. Therefore, the preceding request is transmitted to the priority circuit unit 20 and the pipeline unit 26 and merged. The store data combined by the processing is written to the main storage device 10 as indicated by the full store access indicated by the operation code of the preceding request.

FIG. 7 is an explanatory diagram showing the merge processing in the case of (2) (preceding partial store access) + (successive partial store access). First, the preceding partial store access obtains the preceding store data in which some of the bytes are valid. Subsequently, the subsequent partial store access in which the access address is the same makes the subsequent store data in which some other bytes are valid. can get.

The two partial store data are combined into one store data by masking the preceding store data with the subsequent store data by the merge processing of the present invention. On the other hand, for request merging, the request for the preceding partial store access is propagated, and the request for the subsequent partial store access is discarded. Therefore, the access to the main storage device 10 of the merged store data is performed by the partial access specified by the operation code of the preceding partial store access request.

That is, when the merged store data is obtained, the fetch data is obtained by fetching the access address of the main storage device 10, and the fetch data is masked with the valid bytes of the store data. Merge in access is performed to combine into one store data, and is written to the access address of the main storage device 10.

FIG. 8 is an explanatory view showing the merge processing of (preceding partial store access) + (subsequent full store access) in (3). In FIG. The following store data having all the bytes valid is obtained by the subsequent full store access having the same access address, thereby satisfying the merge condition of the present invention. Preceding store data

Are combined into one store data in the form of masking. At this time, for the merge of the request of the preceding partial store access and the request of the subsequent full store access, the request of the preceding partial store access is propagated, and the subsequent full store access is discarded. Therefore, the store access to the main storage device 10 of the store data obtained by the merge is the partial access specified by the operation code of the preceding partial store access request.

That is, merge is performed by fetching the access address of the main storage device 10 to obtain fetch data, and combining the fetch data into one store data by masking the fetch data with the store data obtained by merging. Finally, the data is written to the access address of the main storage device 10. (3) (previous partial store access) + (subsequent full store access) in FIG.
After all, the subsequent store data in which all the bytes of the subsequent full store access are valid is written to the access address of the main storage device 10, so that both the preceding and succeeding data shown in FIG. It is.

In the case of FIG. 8, the store data itself is data by full store access, but store access is performed by partial store access of preceding store access. Therefore, the number of processes is larger than that of the full store access shown in FIG. 6 by the fetch processing, but it is easier to add the extra fetch than the processing of changing the opcode of the request of the preceding partial store access. Since it is the same as partial access, (previous partial store access) + (subsequent full store access) of (3) shown in FIG. 8 is a target of store merge of the present invention.

FIG. 9 is an explanatory diagram showing a merge process of (preceding full store access) + (subsequent partial store access). In FIG. 9, when the preceding full store access obtains the preceding store data in which all bytes are valid, and subsequently, the subsequent partial store access having the same access address obtains the subsequent store data in which some bytes are valid, As shown in (1), merging is performed in such a manner that the preceding store data is masked by the subsequent store data, and the merge is made into one store data.

Here, it is only necessary to discard the succeeding request of the preceding request of the preceding store data and the succeeding request of the succeeding store data. Therefore, the preceding request is transmitted to the priority circuit section 20 and the pipeline section 26 and merged. The store data combined by the processing is written to the main storage device 10 as indicated by the full store access indicated by the operation code of the preceding request.

5 . Conditions for Activating Store Merge Control of the valid bit V provided in the preceding access address register 50 of the pre-port unit 16 will be described again with reference to FIG. The valid bit V is a valid control unit 64 corresponding to the valid signal control unit 3 shown in the principle explanatory diagram of FIG.
It is performed by FIG. 10 is a block diagram of an embodiment showing an embodiment of the valid control unit of FIG. 4. The OR circuit 65 for producing a set signal and the OR circuit 6 for producing a reset signal are shown.
6 and the output of the OR circuit 65
RS flip-flop 6 reset by the output of 6
8 is provided. The output of the RS flip-flop 68 is a valid bit of the preceding access address register 50 of FIG.
That is, it becomes the preceding address valid signal V.

The set signal S of the valid control unit 64
The setting conditions of the preceding address valid signal V determined by 1 and S2 are as follows. (1) When the preceding address valid signal V is off and there is a store access; (2) When the preceding address valid signal V is on and there is a store access of a different address;

Next, the reset condition of the preceding address valid signal V determined by the reset signals R1 and R2 is as follows. (1) When the reset flag is input from the register 48 in cycle 2 of the pipeline unit 26; (2) When the fetch access of the same address as the address held in the preceding access address register 50 is received;

Here, (1) of the reset condition means the end of the effective period of the store merge. The reset condition (2) is to ensure that the preceding store access can be seen by the subsequent fetch access of the same address. In this case, the preceding address valid signal V is reset so that the store merge is not performed. To Further, the reset flag used in the reset condition (1) of the preceding address valid signal V will be described as follows.

In the valid control unit 64 shown in FIG. 4, the pre-port request queue 40 and the pre-port register 38 of the pre-port unit 16 through which a request by access propagates, the port register 42 and the request queue 44 of the priority circuit unit 20, Further, a flag register 70 for propagating a reset flag used for reset control of the preceding address valid signal V is provided for each of the registers 46 and 48 in cycles 1 and 2 until the store merge of the access pipeline 26 is completed. I have.

The flag register 70 propagates a reset flag for a request due to the preceding store access to be subjected to store merging, and detects the reset flag from the flag register 70 provided in the register 48 of the second cycle of the access pipeline 26. When it is determined that the store merge period has ended, the preceding address valid signal V
Reset control. There are the following two conditions for erasing the reset flag stored in the flag register 70.

(1) Preceding access address register 50
(2) When there is a fetch access of the same address as the address held in the preceding access address register 50; this reset flag erasing condition (1) Is a case where the access address of the preceding access is different from the access address of the subsequent access. In this case, the reset flag is erased because the store merge is not performed.
Even if this request propagates to the register 48 of the access pipeline unit 26, a reset flag is not obtained from the flag register 70.

The reset flag erasure condition (2) is as follows.
Reset condition of preceding address valid signal V (2)
In the reset condition (2), after resetting the preceding address valid signal V for the fetch access, the reset flag corresponding to the fetch access is erased in addition to the reset signal, and the reset is performed together with the fetch access request through the flag register 70. Flags are not propagated. That is, merge is not performed in a fetch access at the same address following the preceding store access.

The address match output from the comparing section 52 and the above-mentioned (1) to
When the three conditions of (3) the determination output of the combination of the full store and the partial store and the preceding address valid signal by turning on the valid bit are satisfied, the start signal is transmitted from the store merge start unit 54 to the preport unit 18 and the store data unit 22.
And the data is merged.

6 . Merging Process of Byte Mark and Store Data The merging process on the data side in the pre-portion section 18 and the store data section 22 is performed separately for the byte mark BM and the store data sent from the CPU 12A. The byte mark BM is obtained by a byte mark signal line 72 as shown in FIG . In this embodiment, the CPU
Since the store data, which is a full store of 8 bytes from 12A, is transmitted through the 8-byte bus 74, eight byte mark signal lines 72 are provided as shown in the figure corresponding to the number of bytes of eight. Actually, the number of signal lines is nine, which is one signal line for parity.

The byte mark BM from the CPU 12A is set in the data register 76, while the 8-byte store data is set in the data register 86. FIG.
FIG. 4 is an explanatory diagram showing the correspondence between byte marks and store data. First, in the full store shown in FIG.
Since all eight bytes B0 to B7 of the store data are valid data, b0 to b0 of the corresponding byte mark BM
The b7 bit is all 1s.

On the other hand, in the partial store shown in FIG. 12B , for example, if three bytes B5 to B7 of the stored data are valid bytes, the corresponding b5 to b7 bits of the byte mark are 1 and Bits b0 to b4
Becomes 0.

As described above, the byte mark indicates the position of the effective byte of the stored data, and it is possible to know whether the store is a full store or a partial store by looking at the byte mark. Since the store merge is activated, it is determined whether the store is a full store or a partial store from the operation code regardless of the byte mark.

Referring to FIG. 4 again, the byte mark side and the data side will be described first. After the byte mark from the CPU 12A is set in the byte mark input register 76,
The byte mark merge register 78 and the byte mark register 8 are synchronized with the propagation on the request side of the pre-portion section 16.
0, 82 and further to the data queue 84.

An activation signal is given from the store merge activation unit 54 to the byte mark merge register 78 provided in the second cycle of the preport unit 18. When the start signal is off, the byte mark merge register 78 transfers the input byte mark as it is. On the other hand, upon receiving a start signal from the store merge start unit 54, the store merge start unit 54 performs a merge process of adding the byte mark of the preceding store access to the byte mark of the subsequent store access to obtain logical sum data and outputs the result to the store data unit 22.

The byte mark register 80 of the store data section 22 is provided as a register in the T3 cycle following the processing cycle of the preport section 16, and the byte mark register 82 is provided as a register in the next T4 cycle. That is, the byte mark input register 76 and the data input register 86 are registers which are first input from a processing device such as a CPU, corresponding to the input register 36 on the request side. The byte mark merge register 78 and the byte mark registers 80, 82 are data registers 88, 90, 9
2 is supported. Therefore, the data and byte mark are 4
The data is input to the data queues 84 and 94 at a fixed timing of the cycle.

When the cycle of the access pipeline section 26 advances and access to the main storage device 10 is performed, the corresponding byte mark and data are stored in the data queue 8.
4, 94, the byte mark register 10
0, 102 and the data registers 96, 98 are written to the main storage device 10. The data queues 84 and 94 are provided with an in queue counter 104 and an out queue counter 106 in common. Writing control of the data queues 84 and 94 and control of the in queue counter 104 and the out queue counter 106 are performed by the data queue control unit 112. Done.

When the store merge activation signal is not obtained, the data queue control unit 112
04 after counting up
The byte data and the data are written to the respective positions of the data queues 84 and 94 designated by the value of 4. That is, for the byte mark, the write enable WE of all the bits of the byte mark is turned on, and the byte mark is stored in the data queue 84.
Write to. As for data, only the write enable WE corresponding to the valid bit 1 of the byte mark is turned on, and the data is written to the data queue 94. This is because data corresponding to other than the valid bit 1 of the byte mark is treated as invalid data in the main storage device 10.

On the other hand, when the store merge start signal is obtained, the data is written to the same position as the storage position of the preceding byte mark and the store data in the data queues 84 and 94 without counting up the in queue counter 104. In this case, writing of the byte mark to the data queue 84 is performed in the same manner as in the case where the merge start signal is not obtained.
Is turned on, and the byte mark is written into the data queue 84. This is because the byte mark has already been merged in the byte mark merge register 78 of the pre-portion section 18.

On the other hand, regarding the data queue 94,
Only the write enable WE of the data byte corresponding to the valid bit 1 of the byte mark is turned on, and the subsequent store data is written into the same storage position as the preceding store data to perform the merge processing. The output of the stored data stored in the data queues 84 and 94 is performed by setting the out queue counter to 1
After counting up, data will be extracted. This corresponds to inputting data after counting up by the inqueue counter 104.

As described above, according to the merge control of the present invention, it is possible to perform a merging process using a data queue by a special method of inputting data after counting up the in queue counter, which normally counts up after inputting data. This eliminates the need for a data merge circuit conventionally provided at the input stage of the data queue.

7 . FIG. 13 is a block diagram showing an embodiment of the data queue control unit 112 in FIG. In FIG. 13 , the inqueue counter 104
Signal + INQ for CTUP CO
PY indicates a latch circuit 114, an AND circuit 116, an inverter 118, an OP code register 36a, an OP code decoder 120, an OR circuit 122, and latch circuits 124 and 12.
6 is created in the circuit section.

The valid bit of the request is latched in the latch circuit 114 at the set timing T1 of the input register 36. The inverter 118 inverts the output of the store merge starting unit 54 in FIG. OP code register 3
Reference numeral 6a shows a set portion of the OP register of the input register 36 shown in FIG.

The AND circuit 116 outputs 1 when three conditions are satisfied: the valid bit is 1, the store merge start signal is off, and the access is partial store or full store.
And The output of the AND circuit 116 is a count-up signal + I by the latch in the T2 cycle of the latch circuit 124.
NQ CT UP, and the next latch circuit 126 becomes T3
Count-up signal + INQ to in queue counter 104 by latch in cycle CTUP COPY
After the inque counter 104 is counted up in the next T4 cycle, writing to the data queues 84 and 94 is performed in the next T5 cycle. When the store merge signal is obtained, the count-up signal + INQ CTUP COPY is 0, and the inque counter 104 does not count up.

The write enable signal + WE3 for the data queue 94 for store data is generated by the byte mark registers 128, 130 and 132. The byte mark held in the byte mark input register 76 is set in the byte mark register 128 in the T2 cycle,
Byte mark registers 130, 1 in T3, T4 cycles
32 and sequentially output to the data queue 94 as an enable signal + WE3 in which only the valid bit 1 of the byte mark is turned on.

Further, a byte mark data queue 84 is provided.
Write enable signal + WE13 for latch 1
The valid bits from 14 are latched 134, 136, 1
The common enable signal + WE13 for sequentially shifting at 38 and turning on the write enable of all the bits of the byte mark
Output as FIG. 14 shows the data queue control unit 1 of FIG.
12 is a block diagram of an embodiment of a control unit of the out queue counter 106 provided in the register 12; a register 140, an OP code decoder 142, an OR circuit 144, an AND circuit 146, and latch circuits 148 and 150 of the 3-cycle CYC3 of the access pipeline unit 26; It consists of. That is, store access is determined from the valid bit of the register 140 in the third cycle and the OP code, and the latch circuit 148 supplies the count-up signal + OUTQ which becomes bit 1 at the timing of the fourth cycle CYC4. CTUP is latched, latched by the latch circuit 150 in the next fifth cycle CYC5, and the count-up signal + OU is sent to the out queue counter 106.
TQ CTUP Output as COPY.

8 . Description of Store Merge Operation FIG. 15 is a timing chart showing the store merge operation of the present invention. In this timing chart, T1 to T11 of the clock cycle show store access without store merge, and T13 to T11.
Reference numeral 23 indicates an access when there is a store merge. First, store access in the clock cycles T1 to T11 without store merge will be described.

In the cycle T1, a request by store access, that is, a store request 1, is set to the input port 36, and then in the cycle T2, the pre-port register 3 is set.
8 In this cycle T1, the setting condition of the valid bit V is detected by the valid control unit 64 of FIG. 4, and the valid bit V of the preceding access address register 50 is set in the next T2 cycle.

On the other hand, the reset flag propagates together with the store request RQ1 from the T2 cycle, propagates to the priority port 42 in the T3 cycle, takes priority, and enters the pipeline cycle 1 in the T4 cycle. In the present invention, the pipeline cycle CY
Reset flags are provided for C1 and CYC2.
This reset flag corresponds to the store access request RQ1
The reset flag is set in the T4 cycle in synchronization with the reset flag. Pipeline cycle CYC2 of next T5 cycle
But the reset flag is set. If the reset flag is on in cycle CYC2 of this pipeline cycle, the valid control unit 64 turns off the preceding address valid signal V. That is, a period of four cycles from T2 to T5 in which the preceding address valid signal is on is a store merge valid period. If no subsequent store access of the same address comes during this valid period, the store merge is not performed.

On the other hand, the byte mark BM is set in the byte mark input register 76 simultaneously with the store request RQ1 in the T1 cycle. In the T2 cycle, since the valid bit of the preceding access address register 50 is off, the store merge start signal is turned off, and the input byte mark BM1 is stored in the byte mark merge circuit 78.
Is set and held as is. Further, in the T3 cycle, the data is shifted to the byte mark register 80, and in the T4 cycle, the data is shifted to the byte mark register 84. In the T4 cycle, one data queue inqueue counter is counted up, and at the same time, all the bits of the byte mark BM1 are written in the data queue by turning on the write enable WE1.

Next, the store data is finally stored in the data queue 94 via the data registers 86 to 92 through the processing of the T1 to T4 cycles, similarly to the byte mark BM1. Also in this case, the data queue 94
Before the store data D1 is written into the memory, the in queue counter is incremented by one. On the other hand, the request queue input to the pipeline is cycle 6 of the pipeline.
At the timing of, the out queue counter OUTQ of the data queues 84 and 94 is counted up, and at the timing of the next cycle 7, the byte mark BM1 and the stored data D1 stored in the data queues 84 and 94 are read, and T11 Store execution is performed on the main storage device in a cycle.

Next, the store merge process will be described. In this store merge, the store request RQ2 of the preceding store access is obtained in the T13 cycle, and the store request valid signal V is turned on by the preceding store request RQ2 during the store merge valid period from the T14 to T17 cycles. Shows a state in which a store request RQ3 by a store access having the same access address has been obtained in the T17 cycle. The preceding store request RQ2 is the same as the case without store merge, but when a subsequent store request RQ3 of the same address is obtained in the cycle T17, a store merge start signal is output from the store merge start unit 54, and the byte mark Then, a merge process of the store data is performed. Also,
As for the store request RQ3, the merge of the store request RQ3 discards the store request RQ3 so as not to propagate it.

The byte mark side receiving the store merge activation signal in cycle T17 is the byte mark B of the preceding store request RQ2 held in cycle T14.
A byte mark for adding the byte mark BM3 of the store request RQ3 following the M2 is merged, that is, a merge process for obtaining a logical sum of the held byte mark BM2 and the newly input byte mark BM3 is performed. The performed byte mark propagates in T19 and T20 cycles, and is stored in the data queue 84 at T21.

On the other hand, for the store data, the preceding store data D2 is stored in the data queue 94 in the cycle T17.
Is stored in The storage position at this time is specified by the in queue counter INQ = 2, which is counted up from 1 to 2 when shifting from T15 cycle to T16. The succeeding store data D3 is stored in the data queue 94 in the cycle T21.
For the 9th cycle, since the store merge activation signal was obtained in the T17 cycle, the in queue counter IN
Merging of store data is performed by writing to the storage location of the preceding store data D2 without incrementing Q and keeping INQ = 2.

When cycle 7 of the pipeline is completed, T23
The store is executed in the cycle and the out queue counter O
By counting up one UTQ, the data queue 8
4 and the store data output from the data queue 94 are written to the main storage device 10.

9 . FIG. 16 is a block diagram showing another embodiment of the byte mark merging circuit unit in the embodiment shown in FIG. 4. In this embodiment, the byte mark merging process is performed. It is characterized in that it is performed in the data queue 84.

In FIG . 16 , the T2 cycle is changed from the byte mark merge register 78 in FIG. 4 to a simple byte mark register 78a in this embodiment. The data queue 84 performs byte mark merging in the same manner as the store data data queue 94 in FIG. Therefore, when store merge is activated,
As a write enable signal from the data queue control unit 112, a write enable signal in which only the valid bit 1 of the byte mark is turned on is given.

[0102] Specifically, if the store merge in the embodiment of FIG. 13 is not activated, than latches 138 +
When store merge is started using WE13,
The write enable signal + WE3 from the byte mark register 132 is also used for the data queue 84. That is, a + WE signal in which + WE13 and + WE3 are switched by the control signal generated by the store merge activation signal is supplied.

In the above embodiment, the store merge control for 8-byte store data is taken as an example. However, the number of data bytes can be determined as needed.

[0103]

As described above, according to the present invention, hardware for merging store data can be reduced, and a store merge opportunity can be reduced by increasing the number of combinations of a full store and a partial store which is a store merge. , And the store merge timing can be extended to allow store merge until after the priority is taken. Frequent store merge improves the access performance to the main storage device. can do.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an information processing apparatus to which store merge control of the present invention is applied;

FIG. 3 is a configuration diagram of an embodiment of a main memory control device in FIG. 2;

FIG. 4 is a configuration diagram of an embodiment showing a circuit unit of a main storage control device that performs store merge control according to the present invention;

FIG. 5 is a diagram showing a format configuration of a request by store access.

FIG. 6 is an explanatory diagram of (preceding full store) + (subsequent full store) in case (1).

FIG. 7 (Previous Partial Sure) + of Case (2)
(Successive partial store)

FIG. 8 (Previous Partial Sure) + of Case (3)
(Following full store) illustration

FIG. 9 is an explanatory diagram of (preceding furtosua) + (subsequent partial store) in case (4).

FIG. 10 is a configuration diagram of an embodiment of a valid control unit in FIG . 4;

FIG. 11 is an explanatory diagram of a byte mark sent from a CPU.

FIG. 12 is an explanatory diagram of correspondence between byte marks and store data.

FIG. 13 is a configuration diagram of an embodiment of a data queue control unit in FIG . 4;

FIG. 14 is an out queue in the data queue control unit of FIG . 4;
Example configuration diagram of a counter control part

FIG. 15 is a timing diagram showing the store merge control of the present invention .
Gchart

FIG. 16 shows another embodiment of the byte mark merging process of FIG . 4;
Example configuration diagram showing an example

FIG. 17 is a main note in which a conventional store merge control method is performed;
Illustration of memory control device

FIG. 18 is an explanatory diagram of a full store and a partial store.

[Explanation of symbols]

 1: Address match detection unit 2: Store access discrimination unit 3: Valid signal control unit 4: Store merge start unit 5: Byte mark merge unit 6: Store data merge unit 10: Main storage unit (MSU) 12: Main storage control unit (MCU) 14, 14B to 14D: Processing unit 14A: CPU 16: Preport unit (for request) 18: Preport unit (for data) 20: Priority circuit unit 22: Store data unit 26: Access pipeline unit 28: Main storage Address interface unit 34: Load data unit 36: Request input register 38: Preport register 40: Preport request queue 42: Priority port register 44: Request queue 46, 48, 108, 140: Register 50: Preceding access address register 52: Comparison section 54: Store merge activation unit 56: Opcode register 58: Access discrimination unit 60: In queue counter 62: Out queue counter 64: Valid control unit 65, 66: OR circuit 68: RS flip-flop 70: Flag register 72: Byte mark signal Line 74: 8-byte data bus 76: Byte mark input register 78: Byte mark merge register 80, 82, 100, 102: Byte mark register 86, 88, 90, 92, 96, 98: Data register 84, 94: Data queue 104: In queue counter 106: Out queue counter 110: Store access register (SAR) 112, 112a: Data queue control unit 114, 124, 126, 134, 136, 138, 148, 150: Latch circuit 116, 146: AND circuit 118: Inverter 120 , 142: OP code decoder 122, 144: OR circuit

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-275546 (JP, A) JP-A-2-234242 (JP, A) JP-A 1-222245 (JP, A) JP-A 64-64 31238 (JP, A) JP-A-63-103342 (JP, A) JP-A-63-91756 (JP, A) JP-A-62-38953 (JP, A) JP-A-61-80447 (JP, A) JP-A-56-54558 (JP, A)

Claims (8)

(57) [Claims] In an information processing apparatus including a main storage device, a main storage control device, and a plurality of processing devices, an access address of a preceding store access is stored in the main storage control device.
An address match detection unit 1 for detecting an address match by comparing with an access address of a subsequent store access; and a store access, a full store for rewriting all data of the main memory access address or a partial access for rewriting a part of the main memory access address. The first condition that the preceding store access is the full store and the subsequent store access is also the full store between the preceding store access and the subsequent store access, the preceding store access is the partial store and the subsequent store access is also the partial store the second condition, the third condition preceding store access subsequent store access is full store partial store, and a fourth condition that the previous line store access is subsequent store access is a partial store full store, either has been established In case A store access judging unit 2 for judging that a continuous relationship of store accesses for performing store merge is obtained, and an access address of a preceding store access held in the address match detecting unit 1 is set to be valid for a succeeding store access. A valid signal control unit 3 for outputting a preceding address valid signal to be compared with an address; a coincidence of the access address when a subsequent store access is received; a predetermined continuous relationship between full store and partial store; A store merge activation unit 4 that activates a store merge operation when a condition is satisfied.
And a byte mark merging unit 5 for merging byte marks indicating valid bytes of respective store data of a preceding store access and a subsequent store access in response to a store merge start; A store data merging unit 6 for merging each store data of the store access to be performed, and a byte mark and the store data merged at a predetermined timing after the priority of the preceding store access is taken by the priority circuit unit 26. And an access execution unit 9 for writing to the storage device. 2. The store merge control method according to claim 1, wherein said store access determination unit 2 determines whether the store is a full store or a partial store from an operation code obtained from a store access request. Store merge control method. 3. The store merge control method according to claim 1, wherein said valid signal control section 3 sets a reset flag used for reset control of a preceding address valid signal to an access address obtained by a store access request, A store merge control method, wherein the store address is propagated together with an operation code and a control flag, and when the reset flag reaches a predetermined transfer position, the preceding address valid signal is reset to end a valid period for merging with the preceding store access. 4. The store merge control method according to claim 1, wherein said byte mark merge unit holds the input data after outputting the currently held data if there is no merge start signal, and outputs a merge start signal. When receiving the data queue, an input stage of the data queue is provided with a byte mark merge circuit 78 which outputs the current held data and simultaneously holds the logical sum data obtained by calculating the logical sum of the current held data and the input data. A store merge control method that eliminates the need for merging. 5. The store merge control method according to claim 4 , wherein said byte mark merging section counts up by one each time a byte mark is input and designates a byte data storage position in a data queue. Includes a queue counter, if there is no merge start signal, counts up the in queue counter and then inputs and writes all the bits of the byte mark.If a merge start signal is received, the byte mark is counted up without counting up the in queue counter. A store merge control method characterized in that all the bits of the data are input and written. 6. The store merge control method according to claim 1, wherein said byte mark merging section counts up by one each time a byte mark is input, and designates a storage position of byte data in a data queue. A queue counter is provided.If there is no merge start signal, the byte mark is input and written to the data queue after counting up the in queue counter, and when the merge start signal is received, the in queue counter is not counted up. A store merge control method characterized in that only valid bits of a byte mark are input to and written in a data queue, and a byte mark is merged in the data queue. 7. The store merge control method according to claim 1, wherein the store data merge unit 6 counts up by one each time the store data is received and a data queue for temporarily storing the store data. An in queue counter that specifies the storage location of the store data in the data queue
If there is no merge start signal, count up the in queue counter and then input and write all the byte data to the data queue.When the merge start signal is received, the byte mark is valid without counting up the in queue counter. A store merge control method wherein two consecutive store data are merged by inputting and writing only byte data specified by bits. 8. The method of claim 5, in the store merge control method according to claim 6 and claim 7, wherein the data queue includes an out queue counter, the data stored in the data queue after counting up the Out queue counter A store merge control method, wherein