JP3215192B2 - Memory access device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for directly accessing a memory constituting a part of a computer system without passing through a central processing unit. More specifically, the present invention relates to a buffer storage means such as a cache memory, a central processing unit, and a main storage. The present invention relates to a memory access device that is connected to a bus connecting the devices and that accesses a memory independently of a central processing unit while maintaining consistency between a cache memory and a main storage device.

[0002]

2. Description of the Related Art As means for improving the performance of a computer system, a central processing unit (hereinafter abbreviated as CPU) is used.
A configuration in which a primary cache memory composed of a memory that can be accessed at high speed is connected and connected, and a secondary cache memory is further connected to a main storage device is commonly used for improving system performance. Method. Here, the primary cache memory is a very high-speed, expensive and relatively small-capacity memory, and the secondary cache memory is a much cheaper and slower memory but is more expensive and faster than the main storage device.

FIG. 20 is a system configuration diagram of a computer system having a primary cache memory and a secondary cache memory. The system in FIG. 20 includes a CPU 2 having a primary cache memory 3, a secondary cache memory 4, a main storage device 5, and an input / output device 6 (hereinafter abbreviated as an I / O device). The CPU 2 and the secondary cache memory 4 are connected by a processor bus 8 (hereinafter abbreviated as a P bus), and the secondary cache memory 4, the main storage device 5, and the I / O device 6 are connected to a memory bus 9 (hereinafter, referred to as a P bus). M bus). It should be noted that the I / O device 6 transmits data (DMA) (direct data) with the main storage device 5 via the M bus 9.
Memory Access) Transfer is possible.

[0004] The primary cache memory 3 and the secondary cache memory 4 used in such a system configuration have a write control method of write-through control.
Further, even in the case of copy-back control, it is necessary to maintain logical consistency with the main storage device 5. The write-through control means that, for example, when a block to be written is in the primary cache memory 3, the primary cache memory 3 writes the block to the secondary cache memory 4, and the secondary cache memory 4 Is written in the primary cache memory 3 or the secondary cache memory 4,
In this method, when an updated block becomes a replacement target, the block data is transferred to the main storage device 5 to update the contents of the main storage device 5. Although there is a difference between the write-through control and the copy-back control, data consistency between the cache memory and the main storage device when writing to the cache memory is maintained in this way.

When the main storage device 5 is rewritten, data consistency between the main storage device and the cache memory must be maintained. For this reason, for example, the secondary cache memory 4 monitors the address and the like on the M bus 9, and when a part of the contents of the main storage device 5 is rewritten by the I / O device 6 connected to the M bus 9, If data of the rewritten address of the main storage device 5 has been entered in the secondary cache memory 4, these cache memory entries are immediately invalidated and the secondary cache memory 4 and the main storage device 5 Keeps the nature.

At this time, the secondary cache memory 4 must also notify the primary cache memory 3 that the contents of the main memory have been rewritten. Therefore, the secondary cache memory 4 outputs a monitor request signal for invalidating the cache memory entry to the primary cache memory 3 and outputs the rewritten address of the main storage device 5. Primary cache memory 3
Receives the monitor request signal and the address information, and if the data of the rewritten address of the main storage device 5 is entered in the primary cache memory 3, immediately invalidates these cache memory entries. Thus, consistency between the primary cache memory 3 and the main storage device 5 is maintained.

On the other hand, there is a computer system having the above-mentioned primary cache memory 3 and secondary cache memory 4 in which a memory access device for accessing a secondary cache memory and a main storage device independently of the CPU 2 is provided.

FIG. 21 is a configuration diagram of a computer system having the memory access device 1. The memory access device 1 includes, for example, a vector process unit (VP)
U) and the like, in which the primary cache memory accesses the secondary cache memory and processes the vector operation at high speed instead of the operation of the CPU 2.

The memory access device 1 requests a bus right of the P bus 8 by a bus right request signal 31 in response to a calculation instruction under the control of the CPU 2. In response to this request, the bus right response signal 32 from the CPU 2 is asserted, and the memory access device 1 acquires the bus right. Thereafter, the memory is directly accessed, and the target vector operation is performed by pipeline processing.

[0010]

In a computer system having such a memory access device, the memory access device 1 obtains a bus right on the P bus 8 to obtain a first cache memory or a second cache memory. While accessing the cache memory of
When the main storage device 5 is rewritten by the O device 6 or the like, the cache memory entry is invalidated and the consistency between the secondary cache memory 4 and the main storage device 5 is maintained as in the case of FIG. I have. However, for example, when the memory access device 1 has acquired the bus right of the P bus 8 connecting the secondary cache memory 4 and the primary cache memory 3 in the CPU 2, the secondary cache memory 4 Therefore, if the use of the bus is not managed, the address conflicts with the address output from the memory access device on the P bus 8 unless the use of the bus is managed. For this reason, the primary cache memory 3 cannot be notified that the contents in the main storage device 5 have been rewritten, and there has been a problem that consistency cannot be maintained.

There is a method in which the secondary cache memory 4 controls the bus right of the memory access device 1 so that such bus contention on the P bus 8 does not occur. This method does not cause contention on the P bus, but has a problem that it takes time for bus arbitration (adjustment of the bus right). For example, if the memory access device 1 is a vector processor that performs a pipeline process, there is a problem that a complicated sequence is required to interrupt the pipeline process.

Also, since the CPU 2 accesses the primary cache memory 3 and performs processing while waiting for the end of the access by the memory access device 1, consistency with the main storage device 5 is maintained. There is a problem that meaningless processing is performed by using the contents of the primary cache memory 3 without performing the above processing.

According to the present invention, in order to maintain consistency between the cache memory and the main storage device, the first cache
When requesting invalidation of a cache memory entry to the secondary cache memory, consistency of the primary cache memory with the main storage device can be maintained without causing bus contention, and bus arbitration is required. It is an object of the present invention to provide a memory access device for constructing a high-performance system.

[0014]

FIG. 1 is a diagram illustrating the principle of the present invention. The memory access device 21 of the present invention includes a central processing unit 22 having a first buffer storage unit 23 and a second
The first buffer storage means 23 or the second buffer storage means 24.
The buffer storage means 24 is accessed independently of the central processing unit 22. The central processing unit 22 is provided with an arithmetic processing means 22-1 for decoding an instruction and performing a target operation. The arithmetic processing means 22-1 executes the instruction in the first buffer storage means 23, Performs the specified operation.

The first buffer storage means 23 performs address monitoring by monitoring that the memory access device 21 accesses the second buffer storage means 24, and the monitor is stored in the first buffer storage means 23. Then invalidate that data.

The address generation means 11 generates an address for accessing the second buffer storage means 24 and outputs it to the first bus 28. The generated address is an address at which data for the memory access device 21 to perform the arithmetic processing is stored or an address at which the result of the arithmetic processing is stored. For example, the memory access device 21 is provided in a vector processor unit (VPU).

When the memory access device 21 has acquired the bus right of the first bus 28, the output control means 12 outputs the first buffer from the second buffer storage means 24.
When an access request to the buffer storage means 23 occurs, the address output to the first bus 28 is set to an idle state, for example, a high impedance state.

The control means 13 controls the memory access device 2
1 and the address generating means 1
A strobe signal AS # indicating whether or not the output of No. 1 is valid is generated.

The first buffer storage means 23 and the second buffer
The buffer storage unit 24 operates as a cache memory of the central processing unit 22. The access request signal of the second buffer storage unit 24 to the first buffer storage unit 23 is consistent with the main storage unit 25. Is a signal MREQ # for invalidating a cache memory entry so as to maintain the same.

[0020]

In the memory access device of the present invention, when the memory access device has acquired the bus right of the first bus, the access of the second buffer storage device to the first buffer storage device is performed. When a request occurs, the output control means 12 sets the output to the first bus 28 to an idle state, for example, a high impedance state.

For example, the first buffer storage means 23 is a first cache memory, the second buffer storage means 24 is a second cache memory, and the main storage device 25
Is rewritten by the access of the I / O 26 such as DMA, the second buffer storage means 24 detects the rewrite, and the first and second buffer storage means 23 and 24 and the main storage 25 In order to maintain consistency, the second buffer storage unit 24 requests the first buffer storage unit 23 to invalidate the cache memory entry. In this case, even if the bus right is in the memory access device 21, the address output of the output control means 12 of the memory access device 21 is in a high impedance state, so that the second buffer storage means 24 However, even if an address for invalidating a cache memory entry is output onto the first bus 28, the first buffer storage unit 23 and the second buffer storage unit can be operated at high speed without causing bus contention. 24 can be kept consistent with the main storage device 25.

Further, since the second buffer storage means 24 performs the operation of invalidating the cache memory entry with respect to the first buffer storage means 23 without releasing the bus right, the central processing unit 22 acquires the bus right. In addition, a bus arbitration of releasing the bus right of the memory access device 21 is not required, and as a result, a high-performance system can be constructed.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 2 is a system configuration diagram of the embodiment of the present invention. The central processing unit 22 has a primary cache memory 23 'for storing instructions and the like, and executes processing. This execution is performed by the arithmetic processing means 22-1 in the central processing unit 22.
As shown in FIG. 2, the arithmetic processing means 22-1 is connected to the P bus 28 and the primary cache memory 23 ', and performs various arithmetic operations. Further, it also stores various types of control information in a control register of the arithmetic processing unit 27 described later and reads out status information. In the system shown in FIG. 2, the primary cache memory 23 'of the central processing unit 22 and the central processing unit 22 are connected via the P bus 28 to the secondary cache memory 24'.
And the arithmetic processing unit 27.

The primary cache memory 23 'stores an instruction to be executed by the central processing unit 22 and has a high response speed, so that the central processing unit 22 can process the instruction at a high speed. On the other hand, the secondary cache memory 24 'has a larger capacity and a lower speed than the primary cache memory 23', and if the contents of the target address are not stored in the primary cache memory 23 ', the secondary cache memory 24' The data is read from the memory 24 ', stored in the primary cache memory 23', and executed. Not only instructions but also data and the like are stored in the primary cache memory 23 'and further in the secondary cache memory 24'. Further, the secondary cache memory 24 'is connected to the main storage device 25 via the M bus 29. The I / O device 26 is also connected to the M bus 29.

The aforementioned P bus 28 and M bus 29 are composed of an address bus and a data bus, and a control bus (not shown). The main storage device 2 is connected via these buses.
5 are accessed and data and commands are transferred.

The programs and commands that are the basis of the execution of the central processing unit 22 are stored in the main storage device 25. When an address of data or a command not stored in the primary cache memory 23 'or the secondary cache memory 24' occurs, the data in the main storage device 25 is stored in the secondary cache memory 24 ', and thereafter the primary cache memory is stored. It is stored in the memory 23 '. When the storage capacity of the secondary cache memory 24 'is larger than the storage capacity of the primary cache memory 23', the secondary cache memory 24 'stores the secondary cache when data and commands of the target address are stored. The data is read from the memory 24 'and stored in the primary cache memory 23'. These primary cache memory 23 'and secondary cache memory 24' are cache memories based on write-through control and copy-back control as in the above-described conventional case.

The central processing unit 22 accesses the primary cache memory 23 'and the secondary cache memory 24' to execute a target program.
Is executed to execute each processing. At this time, of course, the primary cache memory 23 '
In addition, the execution is performed while maintaining the consistency of the data in the secondary cache memory 24 ', and the speed is increased.

Further, in the case where a high-level calculation or the like that cannot be processed by the central processing unit 22 occurs, a processing unit 27 for performing the calculation is provided in the system shown in FIG. The arithmetic processing unit 27 is, for example, a vector processor unit (VPU).
In this case, the memory is directly accessed without going through the step 2 and the vector operation is performed by pipeline processing. Therefore, a memory access device 21 for directly accessing a memory is provided in the arithmetic processing device 27. Central processing unit 2
2 to instruct the arithmetic processing unit 27 to execute, P
Instructions are written to a register (not shown) of the arithmetic processing unit 27 via the bus 28, and the memory access unit 21 operates to read and write data in the primary cache memory 23 'from the results. That is, the arithmetic processing unit 27 directly accesses the primary cache memory 23 'when executing processing corresponding to the command instructed from the central processing unit 22. At this time, if the bus is released to the central processing unit 22, in other words, the right to use the bus in the arithmetic processing unit 27 is acquired. That is, a bus right request 31 is output to the central processing unit 22 to acquire the bus right.

The central processing unit 22 releases the P bus 28 at a timing when the P bus 28 can be released, and inputs the bus right response signal 32 to the control circuit 13 in the arithmetic processing unit 27.
When the bus right response signal 32 is input, the control circuit 13 recognizes the acquisition of the bus right, controls the output control circuit 12, and outputs an address signal corresponding to the address generated by the address generation circuit 11 to the address bus. The arithmetic processing unit 27 outputs data to be written to the primary cache memory 23 ′ to the P bus 28, and takes in data input from the primary cache memory 23 ′ into the arithmetic processing unit 27. The arithmetic processing unit 27 performs a vector operation using the data stored in the primary cache memory 23 'by accessing the address and the data bus, that is, the P bus 28.

It is assumed that data is rewritten from the I / O device 26 to the main storage device 25 during the operation. The secondary cache memory 24 'constantly monitors which area in the main storage device 25 has been accessed in order to maintain data consistency, and the data in the accessed area is stored in the secondary cache memory 24'. If so, invalidate the data. Further, the address to be invalidated is stored in the input address latch circuit 30 to indicate the input address to the primary cache memory 23 '.

Then, MREQ # (monitor request)
The signal is sent to the control circuit 13 and the output control circuit 1 in the memory access device 21 of the central processing unit 22 and the arithmetic processing unit 27.
Output to 2. For example, when the arithmetic processing device 27 is performing the above-described operation, the control circuit 13 in the memory access device 21 recognizes this, issues an instruction to set the output of the output control circuit 12 to high impedance, and outputs the address strobe signal AS. # Is output to the secondary cache memory 24 '. The address strobe signal AS # is applied to the output enable terminal of the latch circuit 30, and the input address latch circuit 30 outputs the address value to the address bus of the P bus 28 when the address strobe signal AS # goes low. . Thus, if data corresponding to the address output from the input address latch circuit 30 has been entered, the primary cache memory 23 'invalidates that area.

The device which outputs the address strobe AS # signal is a device which has obtained the right to use the bus. In the above case, the processing unit 27 has obtained the right to use the bus. When the right is acquired, the central processing unit 22 outputs the address strobe signal AS #.

In order to control the timing at which each of these signals is output, the state machine 13 'converts the states into T1 to T
5 and T1W to T5W states. Each state will be described later (see FIGS. 11 to 15).

The memory access device 21 of the present invention is configured such that the primary cache memory 2
A monitor request signal (MREQ #) for invalidating the cache memory entry to 3 'is fetched, and if this monitor request signal MREQ # is asserted,
Address output ADDRESS of memory access device 21
(O) is brought into a high impedance state. Hereinafter, (O) after the symbol means output, and (I) means input. Assert indicates active and negate indicates inactive.

However, the address output ADDRES
There are the following conditions for bringing S (O) into a high impedance state. All the devices that directly output an address and perform direct memory access output a strobe signal AS # indicating whether the output address is invalid or valid. While the strobe signal is asserted, the output address is recognized as valid, and the external circuit uses the output address at that time.

The address strobe signal AS #
When (O) is asserted, the address ADDRES
S (O) is not brought into a high impedance state. This is because, when the address strobe signal AS # is asserted, the output address ADDRESS is output only under the condition that the monitor request signal MREQ # is asserted.
If (O) is set to the high impedance state, the external circuit recognizes the address in the high impedance state as a valid address, which causes a malfunction of the system. This problem is the same in the configuration of the computer system in which only the CPU 22 is connected to the P bus 8, and the address strobe signal AS # (O)
Is asserted, the secondary cache memory 24 'does not output the monitor request signal MREQ #.

In the system configuration shown in FIG. 2, the memory access device 21 is of a synchronous type operating at the same clock as the central processing unit 22 and often requires high speed. (O) is output as soon as the bus access starts.

However, there are cases where the change in which these address strobe signals AS # (O) are asserted cannot be recognized by the secondary cache memory 24 '. For example, when the memory access device 21 acquires a bus right of the P bus 28 and performs memory access, the monitor strobe signal AS # (O) is immediately asserted after the monitor request signal MREQ # is asserted. This is the case.

Only when the monitor request signal MREQ # is asserted, the output address ADDRESS
If (O) is in a high impedance state, the address ADDRESS (O) will be in a high impedance state while the address strobe signal AS # (O) is asserted, and the system will malfunction.

That is, when the monitor request signal MREQ # is detected in the cycle in which the address strobe signal AS # (O) is to be output, it means that the state transits to the next state, that is, the T1 state described later. In such a case, the access completion signal DC # (I)
Is returned and the state transits to the next T1 state, or when the bus right is acquired and the state transits to the T1 state, which is a bus break. In this case, the memory access device 21
When the monitor request signal MREQ # is detected, the bus right is acquired and the next bus access is not performed. In the Ti state, the memory access device 21
Since RESS (O) is not being output, that is, in a high impedance state, the secondary cache memory 24
There is no need to worry about conflicting with the address output by the bus. The continuation of the cycle of the state Ti state is canceled by negating the monitor request signal MREQ #, and if negated, the state transits to the cycle of the T1 state. The Ti state and T1 state will be described later in detail.

When the monitor request signal MREQ # is detected in the middle of a memory access bus cycle, an address strobe signal AS # (O) is output and an access completion signal DC #, which is a bus access response signal, is output.
This means that (I) has not been returned. In this case, since the address strobe signal AS # (O) has already been output, the output address ADDRESS is output.
(O) may be in a high impedance state. Therefore, the memory access device 21 sends the monitor request signal M
When REQ # is detected, control is performed to set only the output address to a high impedance state.

The operation of the output control circuit 12 and the control circuit 13 in the memory access device 21 has been described above, that is, the operation of the buffer control unit 12 'and the state machine 13'. However, the operation will be described in more detail below.

FIG. 3 is a block diagram of a memory access device according to an embodiment of the present invention. FIG.
FIG. 4 is a detailed configuration diagram of a 4, 3-state buffer 15 and a buffer control unit 12 '. The output control circuit 12 includes an output latch unit 14, a buffer control unit 12 'and a three-state buffer 15, and the control circuit 13 includes a state machine 13' and an output circuit 13 "for a strobe signal AS #. The output address CK1 is a D-type flip-flop DFF-1 to DFF-1 in the output latch unit 14.
DFF-n is input for one bit. For example, in the case of a vector processor unit, a 64-bit address is stored in the output latch unit 14.

A clock CLK is input to the output latch section 14, and D-type flip-flops DFF1 to DF
Fn takes in data in synchronization with this clock. still,
An address output enable signal is added to the output latch unit 14. When this signal is at the H level, it corresponds to the clock and takes in the address signal CK1 output from the address generation circuit 11. When the output address enable is at a low level, a hold state is set.

The output of the output latch unit 14 is input to a three-state buffer 15. The three-state buffer 15 has three output states, that is, a high impedance state, an L level state, and an H level state.
At the time of the level, it is in a high impedance state (high-Z). When the three-state control signal is at the H level, signals output from the D-type flip-flops DFF1 to DFFn of the output latch unit 14 are output.

The operation of the three-state buffer 15 will be described below. The output of the output latch unit 14 is a NAND gate NA
ND1 and NOR gate NOR1. When the three-state control signal is at the H level, the NAND gate NAND1 is turned on, and since the L level is applied to the OR gate via the inverter IN1, the NOR gate NO1 is turned ON.
R1 is also turned on. The output of the NAND gate NAND1 is supplied to the output FET F1 via the inverters IN2 and IN3, and the output of the NOR gate NOR1 is supplied to the inverters IN4 and IN5.
To the output FET F2 via As a result, the transistors F1 and F2 are turned on / off in accordance with the H level and the low level output from the output latch unit 14 according to the level. That is, when the H level is applied, the transistor F1 turns on and the transistor F2 turns off. Conversely, when the signal is at the L level, the transistor F1 is turned off and the transistor F2 is turned on. The address CK output from the address generation circuit 11 under the above conditions
1 is a three-state buffer 1 via the output latch unit 14.
5 outputs the address to the P bus.

When the L level is output as a three-state control signal from the buffer control unit 12 ', the L level is input to the NAND gate NAND1, so that it is turned off and the H level is output. The NOR gate NOR1 outputs the inverter IN1. , The signal is turned off and an L level is output. These outputs are input to the FETs F1 and F2 via the two-stage inverters IN2 and IN3 and IN4 and IN5, respectively, so that their FE
T F1 and F2 are turned off. Therefore, at this time, the output becomes high impedance.

On the other hand, state signals T1 to T5, T2 are supplied to a buffer control 12 'from a state machine 13' described later.
Signals such as W, T5W, external input signals DC, MREQ, a bus access request, and a bus acquisition block transfer request are input to the output control logic circuit 12-1. The output control logic circuit 12-1 includes T1W to T1W applied from the state machine 13 '.
A signal for controlling the three-state buffer 15 is generated by detecting a state in which the bus is to be accessed based on T5W and signals such as a DC signal, an MREQ signal, a bus access request, and a bus acquisition block transfer request, which are external input signals. The buffer controller 12 'includes an output control logic circuit 12-1, a D-type flip-flop 12-2, a set / reset flip-flop 12-3, an inverter IN6, a NAND gate NAND2, and inverters IN7 and IN8.

FIG. 5 is a detailed configuration diagram of the output control logic circuit. The MREQ signal, which is an external input signal, is supplied to AND gates AND1, AND3, and AND gate A.
AND gate AND via inverter ND4 and inverter IN10
Enter 2 An access completion signal, that is, a DC signal, which is an external input signal, is supplied to AND gates AND3 to AND5.
To enter. The t1 signal from the state machine 13 'is input to the AND gate AND1 via the inverter IN9.
Input to AND gate AND2. The AND gate AND2 also receives a bus right acquisition signal and a bus access request signal. Further, the t2 signal and the t2W signal are input to the AND gate AND3 via the OR gate OR1, and further, a signal indicating that there is no block transfer request is input. AND gate 4
, The t5 signal and the t5W signal are input via the OR gate OR2. Further, the t2 signal, the t5 signal, the t2W signal, and the t5W signal are supplied to the AND gate AND5.
To enter through.

[0050] When the above-described output control logic circuit 12-1 by a signal from the state machine 13 'that is MREQ signal is not a T1 state a asserted (t ₁ is H),
The H level is stored in the D-type flip-flop 12-2. This H level becomes the L level via the inverter IN6 and is applied to the NAND gate NAND2, forcing the output to the H level. Its output is the inverter IN
7 and a three-state control signal via IN8. As a result, the three-state control signal becomes H
Level.

The outputs of the AND gates AND3 to AND5 are ORed by the OR gate OR4, and the output is input to the reset terminal of the RS flip-flop 12-3, so that the AND gates AND3 and AND3 are output.
When any one of 4 and AND5 is at the H level, the RS flip-flop 12-3 is reset and its output goes to the L level. The reset condition is the T2 state or T2W state, and the DC signal is asserted,
When the MREQ signal is asserted and there is no block transfer request, or when the DC is asserted in the T5 state or the T5W state, or when the MREQ signal is asserted, or when the T2 state, or the T2W state, the T5W state, or the T5 state, the bus access request is issued by the DC assertion. When there is no output, an H level is output from each AND gate AND3-5. In such a state, resetting is performed and the output is set to L level. As a result, the three-state control signal becomes H level as described above.

On the other hand, when the access state is in the Ti state, ie, the idle state, the access completion signal, ie, the DC signal is not asserted, and when the bus right is acquired and the bus access is requested, the RS flip-flop 12-3
Is set to H level. Also, T1 state and MR
D-type flip-flop 12 when EQ is not asserted
-2 stores the L level. According to these states, the L level changes to the H level via the inverter IN6, the H level of the RS flip-flop 12 # 3 is applied to the NAND gate NANA2, and the L level is output as a three-state control signal via the inverters IN7 and IN8.

In FIG. 3, the address output circuit 11 of the memory access device 21 includes an output address generation circuit 11, an output latch unit 14, a three-state buffer 15, a state machine 13 ', and a buffer control unit 1 as described above.
2 'and a monitor request signal MRE.
An input terminal for Q # is provided and supplied to the state machine 13 'and the buffer controller 12.

The bus timing of the memory access device 21 is managed by the state machine 13 '. FIG. 6 is a circuit diagram of the inside of the state machine 13 '. In the figure, LTi, LT1 to LT5, and LT2W to LT5W
Are latches for holding the Ti state, T1 to T5 states, and T2W to T5W states, respectively, ti and t1
To t5 and t2W to t5W are latch LT
i, output signals of LT1 to LT5, LT2W to LT5W,
CL1, CL2, CL3, CL4, CL5, ..., C
L10 and CL11 'are condition determination logic circuits, OR1 to OR
Reference numeral 10 denotes an OR circuit.

As described above, the state machine includes the latches LTi, LT1 to LT5 corresponding to the state of the bus timing.
LT2W to LT5W are provided, and their transition conditions are determined by the condition determination logic circuits CL1, CL2, CL3, CL4, CL5,.
, CL10 and CL11 ', and determines which state to transition to depending on whether a condition is satisfied or not. Therefore, control signals such as the access completion signal DC # (I) are transmitted to the condition determination logic circuits CL1, CL2, CL
, CL4, CL5,..., CL10, CL11, and becomes a factor for determining the next state.

For example, focusing on the T2 state,
The following four types of state transition from the T2 state can be considered. (1) When the access completion signal DC # (I) is asserted and the block transfer condition is satisfied, the state transits to the T3 state. (2) If the access completion signal DC # (I) is asserted, the block transfer condition is not satisfied, and there is a bus access request, the state transits to the T1 state. (3) If the access completion signal DC # (I) is asserted, the block transfer condition is not satisfied, and there is no bus access request, the state transits to the Ti state. (4) If the access completion signal DC # (I) is negated, the state transits to the T2W state.

Note that # in the access completion signal DC # (I) indicates negative logic, and (I) indicates an input. That is, when the t2 signal is asserted, the condition determination logic circuit CL2 determines that the access completion signal DC # (I) is asserted by the OR circuit OR.
5, the access completion signal DC # is asserted.
If (I) is negated, the condition is set to assert the output to the OR circuit OR4. In addition, when the output signal of the OR circuit OR5 is asserted, the condition determination logic circuit CL4 asserts the output to the latch LT3 when the block transfer condition is satisfied, and sets the logic when the block transfer condition is not satisfied and there is a bus access request. The output to the OR circuit OR2 is asserted, and if the block transfer condition is not satisfied and there is no bus access request, the output to the OR circuit OR1 is asserted.

The other condition determination logic circuits are configured in the same manner. Therefore, each state latch in the state machine always operates only with the clock signal CLK, and a certain latch Tj (j = 1,..., 5) , 2W, ..., 5
When the output tj of W) is asserted, it directly indicates that the bus is in the Tj state.

The condition determination logic circuits CL1 and CL11
Is a condition for asserting the OFF output when the monitor request signal MREQ # is negated, and the condition determination logic circuit CL4 is a condition for asserting the ON output to the OR circuit OR1 when the monitor request signal MREQ # is asserted. The state changes, that is, the direction in which the H level is output changes.

Returning to FIG. 3, the description will be continued. The timing of latching the address generated in the output latch unit 14 is controlled by a control signal CK3 from the state machine 13 '. The condition that the control signal CK3 is asserted is the timing of transition from the Ti state to the T1 state, the timing of transition from the T2 state to the T1 state, or the timing of transition from the T5 state to the T1 state. Latch L
This is the output signal t1 of T1.

Further, the buffer control unit 12 'asserts that the control signal CK4 is asserted and the monitor request signal MREQ #
Is negated, the output CK2 of the output latch unit 14 is passed through the three-state buffer 15 as it is to produce an address output ADDRESS (O), and the control signal CK5
Is asserted or the monitor request signal MREQ # is asserted, the output of the three-state buffer 15 is controlled to be in a high impedance state. The state machine will be described in more detail. 7 and 8 are detailed configuration diagrams of the state machine. The latches Ti, T1 to T5, TW2 to TW5 in FIGS.
Use to set the input data.

In the idle state, the latch LTi is set to the H level, and this output becomes the ti signal to the output control logic circuit 12 '. Latch LTi
H level output is applied to the AND gate AND10 and t
When the signal i is at the H level and there is a bus access request and the bus is acquired, and when the MREQ signal is negated, the output of the AND gate AND10 goes to the H level, and the latch TL1 is set to the H level via the OR gate OR14. If any one of the above-mentioned ones, that is, there is no bus access request, the bus right is not acquired, or MREQ is not negated, the AND gate AND
The output of 10 becomes L level, and inputs H level to the latch LTi through the inverter IN11 and the OR gate OR15. That is, unless the condition is satisfied, the latch LTi
Is always at the H level.

When the above condition is satisfied, the OR gate O
The H level is input to the latch LT1 via R14, and the H level is taken in by the subsequent clock CLK. Subsequently, at the next clock, the latch LT2 goes high. At this time, following the first idle state, the state is unconditionally changed from the T1 state to the T2 state. These latches LT
1, LT2 outputs t1 and t2 are also output to the output control logic circuit as described above.

Subsequently, the H level of the output of the latch LT2 is input to the AND gate AND11. At this time, if the DC signal which is the access completion signal is negated, the output is at the H level. To set the latch LT2W to the H level via the OR gate OR15. When the DC signal is negated in the latch LT2W, the H level is always applied to the input of the latch LT2W via the AND gate AND12, and this state is maintained. The output t2W of the latch LT2W
Is also input to the output control logic circuit as a state signal.

The t2W signal and the t2 signal are OR gate OR1.
6 to OR19. These OR gates OR16
ＯＲOR19 is a logic circuit for obtaining the T2 state or the T2W state, and when at least one of the t2W signal and the t2 signal is at the H level, the H level is changed to the AND gate AN.
D13 to AND16.

In the T2 state or T2W state, the DC signal is asserted, the MREQ signal is negated, there is a bus access request, and a signal without a block transfer request is input to the AND gate AND13, and all of those inputs are at the H level. At this time, the output of the AND gate 13 goes to the H level and is again input to the latch LT1 via the OR gate OR14. That is, at this time, the T1 state is set again. When the DC signal is asserted, the MREQ signal is asserted, and the block transfer request is not issued and the T2 state or the T2W state is entered, the output of the AND gate AND14 to which those signals are input sets the latch LTi through the OR gate OR15. That is, in this state, the state becomes an idle state. Further, when the DC signal is asserted, there is no bus access request, and in the T2 state or the T2W state, the output of the AND gate AND15 becomes H level,
At this time, the state is set to the Ti state, that is, the idle state via the OR gate OR15.

Further, if the DC signal is asserted, a bus access request is made, a block transfer request is made, and the state is the T2 state or the T2W state, the output of the AND gate AND16 becomes H level and the latch LT3 becomes H level.
Level to enter. Symbols NT1, NT3, NTi in the figure
a and NTib represent connection terminals for connecting FIG. 7 and FIG.

Latch LT3 is set (output is at H level)
When done, it represents the T3 state. This T
In three states, when the DC signal is asserted, the AND gate AND17 goes to H level, and this H level is input to the latch LT4 via the OR gate OR20. If the DC signal is negated, the output of the AND gate AND18 goes high, and the high level is input to the latch LT3W via the OR gate OR21. Latch LT3W captures it at the next clock.

When the output of the latch LT3W is at the H level, the output of the AND gate AND19 becomes H if the DC signal is negated, and always outputs H to the latch LT3W via the OR gate OR21. This state is maintained while the DC signal is negated. When the DC signal is asserted, the output of the AND gate AND20 goes high, and the high level is input to the latch LT4 via the OR gate OR20. The latch LT3 and the latch LT
3W is input to the output control logic as a T3 state and a T3W state, respectively. That is, when the DC signal is asserted in the T3 state or T3W state, an H level is applied to the latch LT4, and the H level is applied by the clock CLK.
Capture levels.

The output side circuit of the latch LT4 has the same circuit structure as that in the state T3 described above. When the DC signal is negated, the state becomes the T4W state and the state becomes a wait state.
The latch LT4W is set to the H level, and when asserted, the next latch LT5 is set to the H level. These controls are performed by AND gates AND21 to AND24 and OR gates OR22 and OR22.
R23.

When the output of the latch LT5 becomes H level,
If the DC signal is negated, AND gate AND2
5 goes to the H level, the latch LT5W goes to the H level via the OR gate OR24, and enters the T5W state. DC
As long as the signal is negated, AND gate AND26 is at H level.
Therefore, the input of the latch LT5W is set to the H level. That is, the T5W state continues. Also, when the DC signal is asserted in the T5 state, the output of the AND gate 27 goes to H level.

In the T5 state or T5W state,
When the DC signal is asserted, the MREQ signal is negated, and there is a bus access request, the AND gate AND28 becomes H level, and the latch LT1 goes high through the OR gate OR14.
Add level. DC signal is asserted, MREQ
When the signal is asserted and in the T5 state or the T5W state, the AND gate AND29 goes high.
Further, when the bus is in the T5 state or the T5W state without the bus access request by the DC assertion, the AND gate AND30 becomes the H level, and the H level is applied to the latch LTi through the OR gate OR5 to be in the Ti state.

The state is stored in each latch according to the status condition as described above. In each of these states, a desired sequence control can be performed. FIG. 9 is an output circuit diagram of the strobe signal AS #. The set / reset flip-flop RSF10 is set at the time of transition to the state T1 of the state machine, and reset at the time of T1. That is, the set signal input to this set / reset flip-flop RSF10 is T
1 is an output of an OR gate OR14 that inputs an output to
Reset is the output of latch LT1. That is, when the bus right is acquired, H is stored in the three-state buffer TBF.
The level is input, and the output of the flip-flop RSF10 is output as an AS # signal.

FIG. 10 is a configuration diagram of the secondary cache memory. The circuit is divided into a P bus side circuit and an M bus side circuit around a memory 40 composed of a Tag section, a Data section, and a V bit section. The memory 40 is a dual port memory having two input / output ports and two address ports.

In addition, a control circuit as a cache memory is provided. Address input unit 4 on the P bus side
1 is connected to the P bus 28, all bits are input to the tag section of the memory 40, and data in the Data section is accessed via the Tag section. The tag section stores in which area the address corresponding to the memory area managed by the central processing unit 22 is stored, and from the address input from the address input section 41 to the address of the Data section in the memory 40. Convert and access the data section. As described above, the memory 4
0 is dual port memory, one port is Data
It is connected to the data bus of the P bus 28 via the control unit 42. The Data control unit 42 is a circuit that bidirectionally connects the P bus and the Data unit of the memory 40. Target data exists in the memory 40, and the data is Valid (the value of the V bit unit is 1). When connecting in both directions. A comparator (CMP) 43 and an AND gate 44 control this connection. One of the comparators 43 receives a plurality of high-order bits of the address input via the address input unit 41, and the other receives the output of the Tag unit in the memory 40. When an area storing data for accessing the Tag section is stored, the Tag section outputs its upper address, so that the comparator 43 outputs 1. At this time, if the data in the Data portion is Valid, 1 is output from the V bit portion, and the AND gate 44 to which those outputs are input also outputs 1. At this time, the Data control unit 42 performs bidirectional connection.

The other port of the memory 40 is provided with a circuit similar to the above-described configuration, that is, a circuit including a comparator 45, a data control unit 46, an address input unit 47, and an AND gate 48. On the other hand, the same operation is performed.

The output of the AND gate 48 is connected to the MREQ output section 49, and the comparator 45 always monitors the address on the M bus side in addition to the above-mentioned operation.
When the address is valid, that is, when the output of the AND gate 48 is 1, the value of the V bit portion corresponding to the area is set to 0 by a control circuit (not shown), and the MREQ output unit 49 outputs the MREQ signal. Although not shown, when the AS signal is further input, the address of the invalidated area is output to the address bus.

The memory access device 21 used in the system configuration of FIG. 2 performs a memory access to the secondary cache memory 24 '. In this case, the bus timing is usually the following two types. (1) When performing one bus access with one address output, (2) When performing a predetermined number of bus accesses with one address output, (1)
Is called a basic cycle, and (2) is called a block transfer cycle. (2) is a burst mode in which one line of the secondary cache memory 3 is continuously accessed by one address output.

FIGS. 11 and 12 show timing charts of these two bus timings. It should be noted that each of the bus timings in the figure indicates a data read cycle, and one bus access is performed in two machine cycles. In the block transfer in FIG. 12, four consecutive bus accesses are shown.

In the figure, Ti, T1 to T5, and T
1W to T5W indicate that each state of the memory access device has been entered. The Ti state indicates an idle state and indicates that no memory is accessed. CLK is a clock signal for driving the system.

ADDRESS (O) is an address output of the memory access device 21 and "High-Z"
Indicates that the address output is floating in a high impedance state, and "Valid" indicates that the address output is outputting a valid value. AS # (O) is a strobe signal indicating that the address on the P bus 28 is valid, and is a negative logic signal whose "L" level is a true value. As a signal notation, a signal with a # added to a signal name is a negative logic signal, and “I” in parentheses indicates an input signal, and “O” indicates an output signal.

DATA (I / O) is a data input / output of the memory access device 21, and DS # (O) is a strobe signal indicating that data on the P bus 28 is valid. DC # (I) is a signal output from the memory side, and indicates that data access is completed.
This is the C signal. Note that a circle in the drawing indicates the timing at which the signal is detected.

In the system configuration shown in FIG.
Since both memory access device 21 accesses the same secondary cache memory 24 ', address strobe signal A
The same applies to control signals such as S # (O) and data strobe signal DS # (O). That is, when another circuit has not acquired the bus right, the CPU 22 uses the bus and outputs the same signal, and sets the circuit to a high impedance state so that bus contention does not occur. Address ADD
RESS (O) and data DATA (O) are usually
Even if the bus right is acquired, if no address or data is output, it is in a high impedance state.

The bus timing changes with the access completion signal DC # (O) from the cache memory side. If the access completion signal DC # (O) is not asserted, as shown in the T2W state in FIG. Enter the wait state and repeat the same cycle. In FIG. 10, if the access completion signal DC # (O) is not asserted in the T2, T3, T4, and T5 states, the respective states T2W, T3W, T4W, and T5W are entered, and the access completion signal DC # (O) is entered. Repeat the same cycle until is asserted.

FIGS. 13 and 14 are bus timing charts when the memory access device acquires the bus right. FIG. 13 shows a timing chart in the case where the monitor request signal MREQ # is detected in a cycle in which the address strobe signal AS # (O) is to be output from now on in the basic cycle. FIG. 14 shows a timing chart when the request level signal MREQ # is detected.

FIG. 13 shows a case where the monitor request signal MREQ # is detected when the basic cycle of the T1 state and the T2 state is completed and the next basic cycle is to be started. , The address output ADDRESS (O) is set to a high impedance state. This idle state, that is, the Ti state, continues until the monitor request signal MREQ # is negated.

FIG. 14 shows a case where the monitor request signal MREQ # is detected when an attempt is made to transition from the T2 state to the T3 state in the block transfer cycle. At this time, the access completion signal DC # (I) is asserted, the memory access device 21 receives the data accessed by the address output ADDRESS (O) in the T1 state from DATA (I / O), and outputs the address output ADDRESS ( O) is set to a high impedance state, and the state enters the T3 state. Next, at the end of the cycle of the T3 state, the access completion signal DC # (I) is negated, so that the processing enters the waiting state T3W. Further, when the monitor request signal MREQ # is negated, the address output ADDRESS (O) is set to a valid value and its T3W
At the end of the state cycle, the access completion signal DC
Since # (I) is asserted, the process proceeds to the next T4 state.

FIG. 15 shows a vector processor unit (V
FIG. 2 is a configuration diagram of a (PU). The vector processor unit (VPU) includes a vector unit (VU) 61, a command buffer unit (CBU) 62, a control unit (CU) 63, an address unit (AU) 64,
It comprises a bus control unit (BU) 65. still,
Control circuit 13 in memory access device 21 in FIG.
Are included in the vector unit 61, command buffer unit 62, control unit 63, and bus control unit 65 described above.

The address unit 64 is the output address generation circuit 11, output latch section 14, 3-state buffer 15, and buffer control section 12 'in FIG. The vector unit 61 is a unit that performs a vector operation, and includes a vector register (VR) 66 of 8 KB bytes,
A 64-byte mask register (MR) 67-1, a 128-byte scalar register (SR) 67-2, an adder, a multiplier, a divider, a graphic processor, a mask processor,
A vector pipeline 68 for load / store pipes for storing and reading out to / from registers;
7-3. The vector unit 61 is a main part of the vector processor unit.

The central processing unit 22, ie, CPU, and FIG.
Is connected to the vector processor unit VPU, which is the arithmetic processing unit 27, by a slave interface, and when the central processing unit 22 executes the vector operation or the like, the vector processor unit is accessed in the following procedure.

First, the central processing unit 22 initializes an internal register of the vector processor unit, for example, a register described later such as a vector length. Then, when the initialization is completed, the vector processor unit is activated, and the vector processor unit further executes a pipeline process in parallel with a target operation. At this time, the primary cache memory 23 'in the central processing unit 22 is accessed.

When the above operation is completed, the central processing unit 22 accesses the register in the vector processor unit, reads out the end state, and determines, for example, whether or not the operation has been completed normally.

FIG. 16 is a detailed configuration diagram of a portion related to vector calculation of the vector unit 61. Each of the banks B0, B1, B2, and B3 of the vector register (VR) 66 is composed of 8 bytes (64 bits) × 256 words, and the output is applied to the read bank selector 70. The read bank selector 70 has a 64-bit input terminal
8 64-bit output terminals, for example, 10 input terminals
This is a circuit having a matrix structure that has eight output terminals and eight output terminals and freely selects which input data is output to which output terminal. Furthermore, 1 concerning input and output of those data
The address of the next cache memory is output from the address unit 64 described above. That is, the input data selected by the read bank selector 70 in which the primary cache memory is accessed by the address output from the memory access device 21 is transmitted to the vector pipeline 68 every two ports in 64-bit units, that is, every 64 bits × 2 units. The data is input to the multiplier 72, the adder 71, and the divider 73 that are configured. The multiplier 71, the adder 72, and the divider 73 of the vector pipeline 68 are configured to operate by a pipeline.

Each result of each operation pipeline is input to the write bank selector 69. The write bank selector 69 has i 64-bit input terminals and j 64-bit output terminals, and some of the output terminals are input to the vector register 66. The write bank selector 69
Has a matrix structure, and can freely select and output data input to an input terminal to each output terminal.

For example, there are four input terminals and five output terminals.
Individual. With the above configuration, it is possible to execute the operation by inputting the value output from the vector register to each vector pipeline through the read bank selector and returning the operation result to the vector register again through the write bank selector.

Further, the load / store pipe is connected to the input section of the write bank selector and the output section of the read bank selector, and is connected to the bus control unit 65 to perform the operation from the external memory to the vector register and from the vector register to the external memory. Send and receive data.

The output terminal of the write bank selector 69 is input to a scalar register (SR) 67-2, and its output is connected to the input terminal of the read bank selector 70. One output terminal of the read bank selector 70, for example, 32 bits is output as an address index.

The loading and storing of the vector operation operands described above are transmitted and received via the bus control unit 65 connected to the load / store pipe. FIG. 17 is a configuration diagram of the bus control unit 65. The bus control unit 65 is a circuit that controls an interface with an external storage device. The address pipeline stage number determination unit 81 is a logic circuit that determines the number of address advance based on the 32 and 64 bit operand length, the stride value, and the number of banks B0 and B1. The address pipeline stage number determining unit 81 receives signals of the lower order of the stride value, the consecutive address specifying bit for the number of banks, the 64/32 bit specification, and the indirect instruction, determines the number of advance addresses, and sends the value to the timing sequencer 82. Output.

The timing sequencer 82 is the same as the state machine 13 'described above, and controls the state of the bus. The number of bus states is determined by the number of pipelines output from the address pipeline stage number determining unit 81, and the bus state signal is sequentially converted by an external input signal and a timing signal applied via the external terminal control circuit 84.

The bus mode control unit 83 receives the decode output of the decode unit 86 of the control unit 63 and determines the mode of each bus cycle, such as load or store, from each instruction. Then, AV #, BS #, DS are transmitted from the timing sequencer 82 and the bus mode control unit 8.
#, R / W # and other external output terminals.

The external terminal control section 84 is a circuit for controlling the external input, output, input / output terminal direction and the like, and further controls the output timing and the like based on the bus state signal and the external input signal.

The bus right controller 85 controls the acquisition of the external bus right. The external terminal control unit 84 is a bus right control unit 85
When the right to use the bus is obtained by the above control, an external circuit such as a memory is controlled using the above-mentioned external bus. The transmission / reception of vector data is performed between the vector register and the external memory via the external terminal control unit 84 of the bus control unit 65.

When data is transmitted between the vector register and the external memory, that is, the primary cache memory 23 ', when the MREQ signal is added from the secondary cache memory 24', the timing sequencer 82
Controls the state of the bus, and outputs an address strobe signal AS #. The bus is temporarily released by the address strobe signal, and the secondary cache memory 24 'notifies the primary cache memory that the data is invalid.

FIG. 18 is a configuration diagram of the score boat 87 provided in the control unit 63. A set signal for setting the register number used for each instruction unit,
A decoder 91 for generating a reset signal for resetting after use release, a scoreboard 92 having a plurality of SR / FFs (Set Reset-Flip Flop) for storing the set and reset signal states, and a read register number are added. And a selector 93 that outputs the storage state of the scoreboard 92 corresponding to the register number to be stored. The scoreboard 87 checks register conflicts when each pipeline is executed in parallel. Prior to the execution of the instruction, the designation (set number) of the register used in the instruction is added, and the decoder 91 decodes whether the set number is the number of the own register. The decoder 91 decodes each register number, including set and clear. When the set number of the own register is added, a set signal corresponding to the register is output.

When the clear number of the own register is added, a reset signal corresponding to the register is output.
The state of the SR-FF changes according to the set signal and the reset signal, and the state of the register is stored. For example, when the register is used, the set number is added to the decoder 91, the set signal of the target register is output, and the SR-FF of the scoreboard 92 is set. This state indicates that the currently executing instruction is using the register. Then, at the end of the instruction, the clear number is output, the decoder 91 decodes it, outputs a reset signal, and the SR-FF of the scoreboard 92 is reset. When this state, that is, the SR-FF is reset, it indicates that the corresponding register is not used.

FIG. 19 is a block diagram of the pipeline control unit 88. The pipeline control unit 88 transmits a start signal to each pipeline such as a multiplier (MLT) pipeline and an adder (ADD) pipeline, that is, a start instruction, and a vector length to be processed (the number of vector lengths, i). Then, an end signal to each pipeline, that is, an END signal, and a scoreboard clear signal when a register or the like conflicts are generated.

The vector conversion circuits 95-1 and 95-2 are logic circuits for converting a signal representing an input vector length into a signal having a format suitable for internal control timing. Outputs of the conversion circuits 95-1 and 95-2 are input to comparators 96-1 and 96-2.

On the other hand, the counter 97 determines the end timing (EN) of each pipeline from the vector length and the counter value.
D) and a signal having a scoreboard clear number. When a start signal is added, the counter 97 starts counting clocks from the start signal. The count value is calculated by comparators 96-1, 96-2.
The comparator 96-2 outputs a scoreboard clear signal when the value matches the value obtained by converting the vector length by the vector conversion circuit 95-2, and further counts. The comparator 96-1 outputs an END signal when the value matches the value obtained by converting the vector length. This END signal is also applied to the stop input terminal of the counter 97,
Thus, the counter 97 stops counting.

[0109]

As described above, according to the present invention,
When an access request to the first buffer storage unit of the second buffer storage unit occurs when the memory access unit has acquired the bus right of the first bus by the output control unit, the output of the address generation unit is output. Is controlled to be in a high impedance state. Therefore, in order to maintain consistency between the cache memory and the main storage device, when the secondary cache memory requests the primary cache memory to invalidate the cache memory entry, Even when the bus right is in the memory access device, since the address output of the memory access device is in a high impedance state, the secondary cache memory sends the address for invalidating the cache memory entry to the primary cache memory on the P bus. To the primary cache at high speed without bus contention Mori, it is possible to provide a memory access device capable of keeping consistency to the main storage device of the secondary cache memory.

Further, in the memory access device of the present invention,
Without releasing the bus right, the secondary cache memory becomes 1
Since the cache memory entry invalidation operation is performed for the next cache memory, the bus arbitration of acquiring the bus right of the central processing unit and releasing the bus right of the memory access unit is not required, and as a result, a high-performance system can be constructed.

Further, there is no possibility that the central processing unit performs meaningless processing using the contents of the primary cache memory while maintaining consistency with the main storage device.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of a computer system including a primary cache memory and a secondary cache memory according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a memory access device according to an embodiment of the present invention.

FIG. 4 is a detailed configuration diagram of an output latch, a three-state buffer, and a buffer control unit in the memory access device according to the embodiment of the present invention.

FIG. 5 is a detailed configuration diagram of an output control logic circuit.

FIG. 6 is a configuration diagram of a state machine in the memory access device according to the embodiment of the present invention.

FIG. 7 is a more detailed configuration diagram of a state machine in the memory access device according to the embodiment of the present invention.

FIG. 8 is a more detailed configuration diagram of a state machine in the memory access device according to the embodiment of the present invention.

FIG. 9 is an output circuit diagram of a strobe signal AS #.

FIG. 10 is a configuration diagram of a secondary cache memory block.

FIG. 11 is a timing chart of a basic cycle.

FIG. 12 is a timing chart of a block transfer cycle.

FIG. 13 is a timing chart of a basic cycle when MREQ # is detected in a cycle in which AS # is to be output.

FIG. 14 shows an MR in the middle of a memory access bus cycle.
It is a timing chart of a block transfer cycle when EQ # is detected.

FIG. 15 is a configuration diagram of a vector processor unit.

FIG. 16 is a configuration diagram of a vector unit.

FIG. 17 is a configuration diagram of a bus control unit.

FIG. 18 is a configuration diagram of a scoreboard.

FIG. 19 is a configuration diagram of a pipeline control unit.

FIG. 20 is a conventional configuration diagram of a computer system including primary and secondary cache memories.

FIG. 21 is a conventional configuration diagram of a computer system including primary and secondary cache memories.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Address generation means 12 Output control means 13 Control means 21 Memory access means 22 Central processing unit 23 First buffer storage means 24 Second buffer storage means 25 Main storage device 26 I / O device 28 First bus 29 Second Bus

Continuation of the front page (56) References JP-A-3-111951 (JP, A) JP-A-3-57056 (JP, A) JP-A-2-8951 (JP, A) JP-A-58-129564 (JP) JP-A-58-9790 (JP, A) JP-A-61-95469 (JP, A) JP-A-59-180774 (JP, A) JP-A-64-17136 (JP, A) JP-A-2-72450 (JP, A) JP-A-1-279342 (JP, A) JP-A-3-52066 (JP, A) JP-A-2-77858 (JP, A) JP-A-1-222376 (JP, A A) JP-A-3-244065 (JP, A) JP-A-2-48749 (JP, A) JP-A-64-13650 (JP, A) JP-A-1-126758 (JP, A) JP-A-3 -135641 (JP, A) JP-A-3-263245 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 12/08 G06F 15/177 G06F 17/16

Claims (9)

(57) [Claims] 1. A first buffer storage means (23) which a central processing unit (22) has and which is at least accessed from a first bus (28) and connects a second buffer storage means (24). A memory access device (21) connected to the first bus (28) and accessed independently of the second buffer storage means (24) and the central processing unit (22); ) Or an address generating means (11) for generating an address for accessing at least one of the second buffer storage means (24), and the first bus (28) when the bus right of the first bus (28) is acquired. The address is output to a bus (28), and when an access request to the first buffer storage means (23) occurs from the second buffer storage means (24), the first buffer is output. Output control means for the idle output to (28) (12) and a memory access device characterized in that it comprises a. 2. The method according to claim 1, wherein the idle state is the first bus (2).
2. The memory access device according to claim 1, wherein an output to said 8) is in a high impedance state. 3. A latch (14) for temporarily storing an address output by said address generating means (11), and an output of said latch to said first bus (28). A three-state buffer (15) for outputting or high impedance state; controlling the three-state buffer (15) to output an address temporarily stored in the latch (14) during normal access; 3. The memory access device according to claim 2, further comprising: a buffer control unit (12 ') which sets a high impedance state in an idle state. 4. The memory access device (21) further includes a state machine (13 ') for performing state transition control of the memory access device (21) and the address generating means (1).
The strobe signal (AS) indicating whether the output of 1) is valid or not
2. The memory access device according to claim 1, further comprising control means (13) comprising strobe signal output means (13 '') for generating #). 5. The first buffer storage unit (23) and the second buffer storage unit (24) operate as a cache memory of a central processing unit (22), and the second buffer storage unit (24). The access request to the first buffer storage means (23) is sent to the main storage device (2
2. The memory access device according to claim 1, wherein the signal is a signal (MREQ #) for invalidating a cache memory entry so as to maintain consistency with (5). 6. The control means (13) generates a bus right request signal for exclusively using the bus to the central processing unit (22) when a bus use request is issued, and 2. The memory access device according to claim 1, wherein the use of the bus is started by a bus right response signal indicating that the use of the bus is permitted from (22). 7. An arithmetic unit (2) for performing an arithmetic operation without passing through the central processing unit (22).
And generating at least one of an address of read data necessary for performing the operation and an address for storing a result of the operation.
A memory access device according to any of the preceding claims. 8. The memory access device according to claim 7, wherein said arithmetic unit is a vector processor unit. 9. The memory access device according to claim 8, wherein said vector processor unit executes a vector operation by pipeline processing.