JP3799451B2 - Electronic computer system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic computer system, and more particularly to an electronic computer system in which overhead for reading from a storage device is reduced.
[0002]
[Prior art]
With the recent development of electronic technology, the operation speed of arithmetic processing units constituting electronic computers has been greatly improved. However, the operation speed of the storage device that stores the calculation data of the electronic computer has not improved much. For this reason, the overhead for reading out the data required by the arithmetic processing unit of the electronic computer from the storage device tends to increase relatively.
[0003]
FIG. 8 shows a conventional electronic computer system for reducing the overhead of reading data from a storage device. The electronic computer system 101 includes a processing device 102 that executes various arithmetic processes, a main bus line 103 connected to the processing device 102, a memory request bus line 104 connected to the main bus line 103, Main storage device 105 connected to memory request bus line 104, buffer storage device 106 connected to memory request bus line 104, and main storage data read bus line connecting main storage device 105 and buffer storage device 106 108, and a buffer data read bus line 109 connecting the buffer storage device 106 and the main bus line 103.
[0004]
In this electronic computer system 101, the main storage data is stored in the buffer storage device 106 via the main storage data read bus line 108 from the main storage device 105, thereby placing a copy of the main storage data in the buffer storage device 106. By copying a copy of the main storage data from the buffer storage device 106 to the processing device 102 via the buffer data read bus line 109 and the main bus line 103, the average read time is shortened. However, due to the increased speed of the processing device 102 in an electronic computer, the overhead when the buffer storage device 106 does not replicate the main storage data in the main storage device 105 has become an increasingly problematic problem.
[0005]
As a conventional technique for reducing the overhead when the buffer storage device 106 does not replicate the main storage data of the main storage device 105, the following has been proposed.
[0006]
(1) A method in which an instruction for prefetching data stored in the main storage device 105 is prepared in the buffer storage device 106 (first prior art).
[0007]
(2) A method in which the reference pattern of the main storage device 105 is predicted and the buffer storage device 106 is prefetched by hardware (second prior art).
[0008]
(3) A hidden register is prepared from the instruction processing, and an instruction for which main storage data from the main storage device 105 has not arrived is stored from the storage device by changing the order of the instructions assigned to the hidden register. A method in which the delay time for reading data is supplemented by another instruction (third prior art).
[0009]
(4) A method in which a large number of registers are prepared in an instruction set, and reading to the registers is realized by explicit instruction processing (fourth prior art).
[0010]
[Problems to be solved by the invention]
However, in the first conventional technique, it is necessary to verify the conflict with the area of the storage device that is the prefetch target issued by the instruction to read and prefetch data from the buffer storage device. In such a case, it is necessary to use an associative memory device that is difficult to realize. In addition, since there is no standard for determining when the program should pre-read, there is a disadvantage that it cannot be fully utilized.
[0011]
In the second prior art, although it is effective in special cases such as repetitive processing, the timing for performing prefetch determination is slow after the appearance of the reference pattern, so the number of repetitions of the repetitive part of the program is large. However, there is a drawback that the reading overhead of the storage device cannot be sufficiently eliminated when the operating speed of the processing device of the electronic computer becomes high.
[0012]
Further, the third prior art has a drawback that when the speed of the processing unit of the electronic computer is improved, the number of registers necessary for eliminating the overhead is remarkably increased, which causes a heavy burden at the time of instruction decoding. .
[0013]
Furthermore, in the fourth prior art, when the processing speed of the electronic computer is improved, it is necessary to modify the instruction set for the increase in the number of registers necessary for eliminating the overhead. In addition to the disadvantage of compromising compatibility, there is also the disadvantage of reducing the instruction processing performance by forcing a heavy burden at the time of instruction decoding by increasing the number of registers.
[0014]
In addition, there are demands for models with various performances depending on their use and budget, but all of the above conventional technologies provide consistent technology to reduce overhead for models with different performances. Not what you want.
[0015]
SUMMARY OF THE INVENTION Accordingly, a first object of the present invention is to provide an electronic computer system capable of reducing the read overhead of a storage device in which the same program can be applied to each of electronic computers with various performances. A second object of the present invention is to provide a high-performance electronic computer system that does not place a heavy burden on instruction decoding even when a technique capable of reducing the read overhead of the storage device is applied.
[0016]
[Means for Solving the Problems]
In order to achieve such an object, the invention described in claim 1 is a processing device that executes various processes, a main storage device that stores predetermined data and a processing program, and a copy of the main storage data of the main storage device. An electronic computer system comprising a first buffer storage device for storing data and having reduced data read overhead from the main storage device, wherein a storage entry capable of storing a valid bit indicating the validity of entry data and a copy of the main storage data The second buffer storage device allocated to a part of the address of the main storage device, and the allocation address, the number of storage entries, and the size of each storage entry of the second buffer storage device are read. And a processing unit that determines the number of data that can be stored in the second buffer storage device based on each piece of information read by the configuration reading unit. Then, based on the determination result, a data read command from the main storage device to the second buffer storage device is given to the main storage device and added to the memory read request to the main storage device. A request identifier for identifying the read request of the second buffer storage device and a valid bit indicating the validity of the entry data of the second buffer storage device, and the main storage device reads the request identifier and the read identifier. The processing device discriminates the identification information of the request identifier, and stores the read data in the first buffer storage device or the second buffer storage device according to the discrimination result. .
[0017]
In the case of this electronic computer system, the program processed by the processor of the electronic computer reads the number of storage entries in the second buffer storage and the size of each storage entry by the configuration reading means, and how many numerical values are stored in each storage entry. Determine whether it can be stored. In accordance with the information, prior to the operation, a data read instruction is issued to the second buffer storage device by issuing a data read instruction to the second buffer storage device. The number of read instructions is determined by the number of data required by the program and the configuration of the second buffer storage read by the configuration reading means.
[0018]
When the data read instruction is issued, the processor of the electronic computer issues a main memory read request to which the request identifier including the entry number of the second buffer storage device to be read is added to the main storage device. At the same time, the valid bit of the corresponding storage entry of the second buffer storage device is set to “0” to invalidate the entry.
[0019]
The main storage device sends an acceptance confirmation signal to the processing device of the electronic computer in response to a read instruction that can be processed simultaneously among the plurality of read instructions. The read instructions that can be processed simultaneously are stored in the main storage device together with their respective request identifiers. The main storage device sends the request identifier together with the read data designated by the read instruction that allows the read data to be sent.
[0020]
The processing device of the electronic computer discriminates the identification information of the request identifier sent from the main storage device, writes it to the corresponding storage entry if it is read data to the second buffer storage device, and the storage entry Is set to “1”. On the other hand, when it is determined that the discrimination result of the request identifier is reading to the first buffer storage device, the read data is written to the first buffer storage device.
[0021]
The program processed by the processing device of the electronic computer obtains information on which address in the address space of the program the information stored in the second buffer storage device corresponds from the operating system, and sends a response to the read instruction. This information is used by using a memory read instruction to the address. If the response is not obtained from the main memory, the valid bit of the corresponding memory entry in the second buffer memory remains “0”, execution of the program is stopped and a response from the main memory is received. .
[0022]
On the other hand, when the valid bit of the corresponding storage entry of the second buffer storage device is “1”, the memory read request is changed to a read request of the corresponding address of the second buffer storage device, and Read data from the second buffer storage device is sent to the processing device.
[0023]
Here, the configuration reading means may read information relating to the approximate time required for reading from the main storage device and information relating to the number of read instructions that can be processed simultaneously by the main storage device. Further, the processing device discriminates the identification information of the request identifier sent from the main storage device, and if the read data is read data to the second buffer storage device, the read data is stored in the second buffer storage device. If the valid bit of the storage entry is set to “1” along with writing to the corresponding storage entry, and the discrimination result of the request identifier is read data to the first buffer storage device, the read data is set to the first You may make it write in a buffer memory | storage device. Further, the processing device changes the memory read request to a read request of the corresponding address of the second buffer storage device when the valid bit of the corresponding storage entry of the second buffer storage device is “1”. The read data read from the second buffer storage device may be fetched by this read request.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0025]
FIG. 1 shows an embodiment of an electronic computer according to the present invention. The electronic computer system 1 includes a processing device 2 that executes various arithmetic processes, a main bus line 3 connected to the processing device 2, a memory request bus line 4 connected to the main bus line 3, A main storage device 5 connected to the memory request bus line 4, a first buffer storage device 6 connected to the memory request bus line 4 and used conventionally, and connected to the memory request bus line 4 A main memory data read bus line 8 for connecting the second buffer memory device 7 to the main memory device 5, the first buffer memory device 6 and the second buffer memory device 7, and the buffer memory device 6 and the main bus; Reads the buffer data read bus line 9 connecting the line 3 and the information of the allocation address, the number of storage entries and the size of each storage entry of the second buffer storage device 7. And a configure readout means 10.
[0026]
The first buffer storage device 6 is composed of a plurality of storage entries 61, 61, 61 as shown in FIG. As shown in FIG. 1, each storage entry 61, 61, 61 is composed of a valid bit V indicating the validity of entry data, an ADR ADR, and data DATA stored in the storage entries 61, 61, 61. .
[0027]
As shown in FIG. 1, the second buffer storage device 7 has a plurality of storage entries 71,. As shown in FIG. 1, each storage entry 71,..., 71 of the second buffer storage device 7 includes a valid bit V indicating the validity of the storage entry data, and data DATA stored in the storage entries 71,. It is composed of
[0028]
The processing device 2 can refer to the content of data sent from the main storage device 5 to the main storage data read bus line 8.
[0029]
The operation of the electronic computer configured as described above will be described with reference to FIGS. Here, FIGS. 2 to 5 show examples of flowcharts of processing executed by the above-described electronic computer. FIG. 6 shows a time chart for explaining the operation of the electronic computer described above. In FIG. 6, the processing device 2, the configuration reading means 10, the second buffer storage device 7 and the main storage device 5 are arranged on the horizontal axis, and the time is on the vertical axis. FIG. 7 shows the configuration of the main memory read request and request identifier. Of the 128 requests that can be expressed using 7 bits, for example, 120 of the request identifiers are allocated to the storage entries of the second buffer storage device 7, and the remaining 8 are stored in the first buffer storage device 6. Shall be used for request.
[0030]
In the electronic computer system 1, the configuration reading unit 10 reads out information including the number of storage entries in the second buffer storage device 7 and the size of each storage entry and gives the information to the processing device 2 (STP 101 in FIG. 2, FIG. 6). Time t1).
[0031]
A program to be processed by the processing device 2 of the electronic computer system 1 determines how many numerical values can be stored in each storage entry 71,..., 71 of the second buffer storage device 7 based on the above information (STP102, Time t′1 to time t2).
[0032]
Based on the information determined as described above, the processing device 2 reads out the necessary data prior to the calculation to the second buffer storage device 7 by a data read command to the second buffer storage device 7. Is supplied to the main memory 5 via the memory request bus line 4 (STP 103, time t2). Here, the number of instructions to be read is determined by the number of data required by the program and the configuration of the second buffer storage device 7 read by the configuration reading means 10.
[0033]
When the data read command is issued, the processing device 2 of the electronic computer system 1 adds the request identifier 501 including the storage entry number of the second buffer storage device 7 to be read to the main storage read request 502 (FIG. 7). Is issued to the main memory 5 via the memory request bus line 4 (STP 104, time t3).
[0034]
At the same time, the processing device 2 invalidates the storage entry by setting the valid bit V of the corresponding storage entry 71 of the second buffer storage device 7 to “0” (STP 104, time t3).
[0035]
Note that the processing device 2 does not execute the next processing until the reception confirmation signal is received (STP 105: NO). This prevents further reading instructions from being issued from the processing device 2. Further, when the processing device 2 of the electronic computer system 1 receives the reception confirmation signal, the processing device 2 proceeds to the next processing (STP 105: YES).
[0036]
The main storage device 5 determines whether or not it is a read instruction that can be processed simultaneously among a plurality of read instructions. If it is a readout instruction that can be processed simultaneously (STP201; YES), an acceptance confirmation signal is sent to the processing device 2 of the computer system 1 (STP202, time t4). Further, when a read instruction is received exceeding the number that can be processed simultaneously (STP201; NO), a process that does not send an acceptance confirmation signal is executed (STP203).
[0037]
Further, if the read instruction can be processed at the same time, it is stored in the main storage device 5 together with the request identifiers (STP 204). The main storage device 5 sends the request identifier 501 to the main memory data read bus line 8 together with the read data instructed by the read instruction to enable the read data to be sent (STP 205, time t5).
[0038]
When the main storage device 5 sends the request identifier 501 to the main storage data read bus line 8 together with the read data instructed by the read instruction to enable the read data to be sent (STP 205, time t5), the flowchart of FIG. Enter the process.
[0039]
When the processing device 2 enters the processing of the flowchart shown in FIG. 4, the identification information of the request identifier sent from the main storage device 5 to the main storage data read bus line 8 is discriminated (STP 110, time t6).
[0040]
Here, if the data is read data to the second buffer storage device 7 (STP111; YES), write processing is performed on the data area DATA of the corresponding storage entry 71 of the second buffer storage device 7 (STP112, time t7). ), The effective bit V of the storage entry 71 is set to “1” (STP 113, times t8 and t9).
[0041]
Further, if the discrimination result of the request identifier 501 is read to the first buffer storage device 6 (STP 111; NO in FIG. 4), the processing device 2 writes the read data to the first buffer storage device 6 ( STP 114).
[0042]
The program processed by the processing device 2 of the electronic computer system 1 executes the flowchart shown in FIG. 5 at an appropriate timing. That is, the program obtains information indicating which address in the address space of the program the information stored in the second buffer storage device 7 is from the operating system (STP 121), and issues a memory read instruction to the address to the memory request. Issued via the bus line 4 (STP122).
[0043]
The program then goes to see the valid bit V of the corresponding storage entry 71 of the second buffer storage device 7. When the processing device 2 has not received the reception confirmation signal from the main storage device 5, the valid bit V of the corresponding storage entry 71 of the second buffer storage device 7 remains “0”. The program is not executed and is in a state of waiting for a response from the main storage device 5 (STP123).
[0044]
On the other hand, as a result of the program looking at the valid bit V of the corresponding storage entry 71 of the second buffer storage device 7, the valid bit V of the corresponding storage entry 71 of the second buffer storage device 7 is "1". If there is, the data read instruction is changed to a read request for the corresponding address of the second buffer storage device 7, and the read data is transferred from the second buffer storage device 7 via the buffer data read bus line 9 to the electronic computer system 1. To the main bus line 3 (STP123).
[0045]
Therefore, according to the electronic computer system 1 of the present embodiment, it is possible to easily configure electronic computers having different performances in combination with a plurality of main storage devices having different numbers of read requests that can be processed simultaneously. In addition, since the program can determine the configuration and control the optimal instruction issuance, it is possible to achieve the optimal performance with the same program for different performance computers, and the construction of the program library is easy It becomes. Furthermore, in the configuration of a high-performance electronic computer that reads data stored in a storage element that is slower than the processing speed of the electronic computer prior to the calculation, the electronic computer can issue a number of read instructions with a simple circuit configuration. Can be configured easily.
[0046]
The above-described embodiment is an example of a preferred embodiment of the present invention, but is not limited thereto, and various modifications can be made without departing from the scope of the present invention. For example, in the electronic computer system 1 of the present embodiment, the request identifier is assigned to the storage entries of the second buffer storage device 7 out of 128 requests that can be expressed using 7 bits, for example, and the rest. Eight were used for the request of the first buffer storage device 6, but 1-bit information is separately provided for request identification of the first buffer storage device 6 and the second buffer storage device 7. Also good.
[0047]
Further, the configuration reading unit 10 may read information on the approximate time required for reading from the main storage device and information on the number of read instructions that can be processed simultaneously by the main storage device.
[0048]
In addition, as still another embodiment, the first buffer storage device and the second buffer storage device may be allocated to different addresses of the same storage device, or the first buffer storage device and the first buffer storage device Two buffer storage devices may be allocated to separate storage devices.
[0049]
In still another embodiment, in a command for instructing transfer, a data read command instructing transfer of main memory information of the main memory device to the second buffer memory device is used in the second buffer memory device. The transfer destination can be indicated by the storage entry number of the second buffer storage device, can be indicated by a relative address in the address space in which the second buffer storage device is arranged, or the second buffer storage device It can also be indicated by a logical address in the address space arranged in
[0050]
【The invention's effect】
As is apparent from the above description, according to the electronic computer system of the present invention, the processing device determines the number of data that can be stored in the second buffer storage device based on each information read by the configuration reading means, A data read command from the main storage device to the second buffer storage device is given to the main storage device from the determination result, and a plurality of read requests to the main storage device added to the memory read request to the main storage device are identified. A request identifier to be issued to the main storage device, a predetermined value is set in the valid bit indicating the validity of the entry data of the second buffer storage device, and the main storage device transmits the request identifier and the read data by a data read command. The processing device discriminates the identification information of the request identifier, and stores the read data in the first buffer storage device or the second buffer storage device according to the discrimination result. Since the, in combination with co-processable number read request of different main storage, it can be easily configured the computer systems of different performance.
[0051]
In addition, since the program can determine the configuration of the second buffer storage device and control the optimum instruction issuance, it is possible to achieve optimum performance with the same program for electronic computers having different performances. Is easy to construct.
[0052]
Furthermore, there is a high-performance electronic computer configuration that reads out data stored in a storage element that is low in comparison with the processing speed of the electronic computer prior to the operation, and an electronic computer that can issue a number of read instructions with a simple circuit configuration. Easy to build.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of an electronic computer system of the present invention.
FIG. 2 is a flowchart for explaining the processing operation of the read instruction of the electronic computer in the embodiment.
FIG. 3 is a flowchart for explaining the operation of the main storage device of the electronic computer in the embodiment.
FIG. 4 is a flowchart for explaining the write processing operation of the buffer storage device of the electronic computer in the embodiment.
FIG. 5 is a flowchart for explaining processing operations such as acquisition of address information of the electronic computer in the embodiment;
FIG. 6 is a timing chart for explaining the operation of the embodiment;
FIG. 7 is a diagram showing a main memory read request and the like used in the embodiment.
FIG. 8 is a block diagram showing a conventional electronic computer system.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Electronic computer 2 Processor 3 Main bus line 4 Memory request bus line 5 Main memory 6 First buffer memory 7 Second buffer memory 8 Main memory data read bus line 9 Buffer data read bus line 10 Configuration reading means

Claims (4)

A processing device that executes various processes; a main storage device that stores predetermined data and a processing program; and a first buffer storage device that stores a copy of the main storage data of the main storage device. An electronic computer system with reduced data read overhead from the apparatus,
A second buffer storage device having a valid entry indicating the validity of the entry data and a storage entry capable of storing a copy of the main storage data and allocated to a part of the address of the main storage device;
A configuration reading means for reading each information of the allocation address, the number of storage entries, and the size of each storage entry of the second buffer storage device;
The processing device determines the number of data that can be stored in the second buffer storage device based on each information read by the configuration reading means,
From the determination result, a plurality of instructions to the main storage device are given to the main storage device by a data read command from the main storage device to the second buffer storage device, and added to the memory read request to the main storage device Issuing a request identifier for identifying the read request to the main storage device and setting a predetermined value to a valid bit indicating the validity of the entry data of the second buffer storage device,
The main storage device sends the request identifier and read data by a data read command,
The processing device discriminates the identification information of the request identifier, and stores the read data in the first buffer storage device or the second buffer storage device according to the discrimination result. Electronic computer system. The configuration reading means reads information on an estimated time required for reading from the main storage device and information on the number of read instructions that can be processed simultaneously by the main storage device. 1. An electronic computer system according to 1. The processing device discriminates the identification information of the request identifier sent from the main storage device, and if the read data is read data to the second buffer storage device, the read data is stored in the second buffer storage device. If the valid bit of the storage entry is set to “1” along with writing to the corresponding storage entry, and the discrimination result of the request identifier is read data to the first buffer storage device, the read data is set to the first 2. The electronic computer system according to claim 1, wherein the data is written in a buffer storage device. The processor changes the memory read request to a corresponding address read request of the second buffer storage device when the valid bit of the corresponding storage entry of the second buffer storage device is "1"; 2. An electronic computer system according to claim 1, wherein read data read from said second buffer storage device is fetched in response to the read request.

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