JP2588547B2 - Multi CPU system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-CPU system in which a plurality of processing units share at least one memory device. The present invention relates to a multi-CPU system having a cache memory held.

[Conventional technology]

In a multi-CPU system having a plurality of processing units, a cache memory unique to each processing unit is provided in order to access a memory device shared by the processing units at high speed. The data accessed once by the processing unit is held in the cache memory, and when the same data is read again, the data is read from the cache memory, not from the shared memory device, so that the shared memory is apparently high-speed. Equipment and processing units are accessible.

In such a system, when the data portion of the shared memory held in the cache memory by one processing device is rewritten by another processing device, the data portion of the shared memory device and the cache memory device may have the same address. There is a problem that causes inconsistency. An example of solving this problem is the system described in Japanese Patent Publication No. 49-12020. In this example, when one processing device rewrites data in the shared memory device, it sends the address of the update data written to the shared memory device and the valid bit invalidation signal to another processing device, and each processing device performs its own processing. It is determined whether or not the data of the address of the update data is held in the cache memory device. If the data is held, the valid bit corresponding to the address is cleared, and the corresponding data in the own cache is invalidated. I do. Thus, the data mismatch between the shared memory device and the cache memory device is eliminated.

[Problems to be solved by the invention]

In the conventional example, every time the data in the shared memory is updated, all the processing devices sharing the shared memory, other than the processing device that has updated the data in the shared memory, store the data of the corresponding address in the own cache memory. Must be determined whether or not is held. For this reason, even in a processing device that does not hold the corresponding data, this determination processing becomes an overhead, which is a factor that hinders speeding up of memory access.

An object of the present invention is to provide a multi-CPU system that solves the above problems and realizes high-speed access to a shared memory.

[Means for solving the problem]

The object of the present invention is to provide a port having a directory and a valid bit portion having the same configuration as a directory and a valid bit portion of a cache memory inside a processing device on the shared memory device side for the processing device, The bits are made to match the directory and the valid bit in the corresponding processing device, and when updating the data of the shared memory, the address of the updated data exists in the directory of each port in the shared memory device and the corresponding valid bit is present. It is determined whether the port is valid or not, and only the processing apparatus corresponding to the port for which the determination result is “established” is requested from the port to clear the corresponding valid bit of the cache memory in the apparatus. The receiving processor clears the valid bit and, at this time, caches the shared memory in the processor. The access to the memory is suppressed until the valid bit clear ends, and the next access to the shared memory from another processing device is suppressed while at least one processing device is performing the process of clearing the valid bit. This is achieved by:

[Action]

The port corresponding to the processing device provided in the shared memory device is:
Since the data update of the shared memory device can be monitored independently of the cache memory device in the processing device and the necessity of invalidating the data in the cache due to the data update can be determined,
This processing can be performed in parallel with the data processing inside the processing device, and the access to the shared memory can be speeded up. In addition, when the determination result is “established”, by preventing access to the shared memory cache of the corresponding processing device, inconsistency between the shared memory and the cache is prevented, and further, when the determination result is “established” Until the corresponding valid bit in the processing device is invalidated, the access to the shared memory from the processing device for which another determination result has not been established is prevented, so that the detection circuit can be prevented from being missed.

〔Example〕

Hereinafter, an embodiment of the present invention will be described. Figure 2 shows a multi
FIG. 3 is a diagram illustrating a configuration example of a CPU system, in which three processing devices (CPUs) 2 to 3 and a shared memory (GM) 1 are connected by interfaces 5 to 7.

FIG. 3 is an internal configuration diagram of the processing device 2. A basic processing unit (BPU) 22 is a unit for executing instructions, and reads a command to be executed, reads / writes data, and sends a request for the instruction through a bus 30 to a memory control unit (MCU) 23.
To do. The memory control unit 23 is connected to a connection port (GMP) 21, a main storage device (PM) 24, and an input / output control device (IOADPT) 25 of the shared memory through buses 31, 32, and 33, respectively. The input / output controller 25 is connected to a file control processor (FCP) 26 and an input / output processor (IOP) 28 through a bus 34. The file control processor 26 is connected to a file device 27 through a bus 35. Port 21 for shared memory connection
The device controls access to the shared memory 1 and is connected to the shared memory 1 through the interface 5.

FIG. 1 shows an embodiment of a multi-CPU system provided with interface ports (PORTs) 13 to 15 which are a feature of the present invention.
7 to ports 13 to 15 in the shared memory 1 respectively. The ports 13 to 15 perform read access / write access to the memories 110 to 112 through the memory bus 16. Port 13 to memory bus controller (MBCONT) 12
15 controls the exclusive right of the access requested through the memory bus 16.

The internal execution unit (EU) 50 of the processing device 2 is connected to the shared memory connection port 21 by the bus 31, and the shared memory connection port 21 is connected to the port 13 by the interface 5. The same applies between the processing devices 3 and 4 and the ports 14 and 15, but they are omitted in the figure.

Hereinafter, details of each unit will be described. FIG. 4 shows an example of the configuration of the shared memory connection port 21.
The connection bus 31 is connected to an address bus 2100, an access request signal from the unit 23, and a read / write identification signal 2101,
Access end response signal 2101, data bus 2 to unit 23
The interface 5 with the port 13 comprises an address bus 2100, a shared memory update address bus 2112, a data bus 2116, and the like. On the other hand, port 21
The data memory (DATA, cache memory) 213, directory (DIR) 211, valid bit (V) 212, and control unit (C
CNT) 214.

In this configuration, when reading data from the shared memory 1, a read access is input from the memory control unit 23 through the signal line 2101, and an address 2100 is input from the execution unit 50. Then first address 21
The directory 211, the valid bit 212, and the data memory 213 are accessed with the lower address of 00. The control unit 214 reads the data read from the data memory 213 if the data 2105 read from the directory 211 matches the upper bit of the address 2100 and the valid signal 2118 from the valid bit 212 is on. The signal is passed to the memory control unit 23 on the data bus 2103, and the access end response signal 2102 is turned on.

The valid signal 2118 from the valid bit 212 is off or the data 2105 read from the directory 211 is the address 2100
If the data does not match the upper bit, the control unit 214 issues a read access request to the shared memory 1 through the signal line 2114 because there is no valid data in the cache. Data bus 21
When the read data from the shared memory 1 is on-bus at 16, the access end response signal 2115 from the shared memory 1 is turned on. As a result, the control unit 214 takes in the data of the data bus 2116 into the data memory 213, writes the upper bit of the address 2100 into the directory 211, and outputs the signal line 2109
Is turned on, the corresponding bit of the effective bit 212 is turned on.

At the time of a write operation to the shared memory 1, a write access is input from the memory control unit 23 through the signal line 2101. The control unit 214 issues a write access request 2114 to the shared memory 1, and writes the write data through the data bus 2116 and the address through the address bus 2100.
Passed to The directory 211, the effective bit 212, and the data memory 213 are designated by the lower address of the address 2100, the upper address of the address 2100 is transferred to the directory 211, and the data of the data bus 2116 is transferred to the data memory 2
13, the signal line 2109 is turned on to turn on the corresponding bit of the effective bit 212. When the setting of the write data to the cache is completed in this way, the access end response 2102 is turned on to report the end of the write access to the memory control unit 23.

Next, when the invalidation request signal 2113 is inputted from the port 13 which is a feature of the present invention as described later, and the address 2112 of the data to be invalidated is inputted, the address is designated by the lower address of the update address 2112. The corresponding bit of the valid bit 212 is cleared by turning on the signal line 2108. Until this clearing is completed, the access completion response signal 2102 for the access from the memory control unit 23 is suppressed.

FIG. 5 is a diagram showing a configuration example of the port 13. This port comprises a directory (DIR) 131, a valid bit (V) 134, a control unit 132 and the like.
3, write access request signal 1306, read request signal 1307, memory bus occupation request signal 1308, memory bus occupation permission signal 13
09, an access end response signal 1300, a memory access inhibition signal 1310, read data 1305, and write data 1304.

When reading the shared memory 1, a read request is sent from the shared memory connection port 21 to the control unit 132 through the signal line 2114. The control unit 132 outputs a memory occupation request 1308 to the memory bus controller 12 (FIG. 1) from the controller 12 and waits for the memory occupation permission signal 1309 to be turned on. When the memory occupation permission signal 1309 is turned on, the control unit 132
Outputs the address 2100 to the address bus 1313, turns off the memory bus occupation request signal 1308, and
Turn on 1307. In this state, the access end response signal 1300
Turns on, the read request signal is turned off, and the read data 13
05 is output to the data bus 2116, and the access end response 2115 is turned on. When a read access request is made through the signal line 2114, the upper address of the address 2100 is set at the position of the directory 131 specified by the lower address of the address 2100, and the corresponding bit of the effective bit 134 specified in the same manner. Enable bit set signal 1
Turning on the switch 315 makes the connection valid, and makes the directory and the valid bit of the connection port 21 corresponding to the port 13 coincide.

Next, at the time of writing to the shared memory 1, a write access request from the shared memory connection port 21 is input to the control unit 132 through the signal line 2114. At this time, the control unit 132 turns on the memory bus occupation request signal 1308 and waits until the memory bus occupation permission signal 1309 turns on. Memory bus occupancy enable signal
When 1309 turns on, the memory bus occupancy request signal 1308 is turned off, the address 2100 is turned on on the address bus 1313, the write data is turned on on the write data bus 1304 via the bus 2116, and a write access request is issued to the memory bus controller 12. Through the signal lines 1312 and 1306.
When the access end signal 1300 is turned on, the write access request signal 1312, the write address 2100, and the write data 1304 are turned off, and an access end response signal 2115 is output to the connection port 21. At the same time as writing data to the shared memory, the address 2100 is stored in the corresponding position of the directory 131 addressed by the lower address of the write address 2100.
Write the upper address of
The corresponding bit of the valid bit 134 addressed by the lower address of the port 13 is set so that the directory and valid bit of the port 13 match those of the corresponding connection port 21 shown in FIG.

When there is no access request to the shared memory through the access request signal 2114, the control unit 132 writes, through the write request signal 1306, whether or not another processing device 3 or 4 is performing write access to the shared memory 1. This is input as an address determination request signal 1311. When the write address determination request signal 1311 is turned on in response to a write access to the shared memory from another processing device, the control unit 132 takes in the write address 2112 from the other processing device through the address bus 1313, and uses this lower address as a directory. 13
1. Access the valid bit 134 and select the appropriate directory.
An upper address 1301 of 131 and a valid bit valid signal 1302 are input to the control unit 132. The control unit 132 determines whether the input address 1301 and the upper address of the write address 2112 match and whether the input valid signal 1302 is on, and if the determination result is valid, the The bit clear signal 1303 is input to the valid bit 134 specified by the lower address of the write address to invalidate the corresponding bit, and the valid bit invalidation request signal 2113 and the update data address 2112 are output to the connection port 21. ,
A memory access control signal 13 is sent to the memory bus controller 12.
10 is output until the invalidation processing end 2119 is turned on after the invalidation processing of the valid bit 212 is completed, so that the control unit 132 can make a determination accompanying the next update of the shared memory.

FIG. 6 is a diagram showing a configuration example of the memory control unit 23.
It comprises a control unit (MCUCNT) 232 and a cache memory (PMCACHE) 231 for the main memory 24 in FIG. Basic processing unit 22
The read access to the control unit 232 is on-bus to the address 2100, and the read access request is
Control unit 232 decodes the input address, and outputs a read access request signal to any of the connection port 21, the cache memory 231 and the input / output control device 25 through 2101, 2305, or 2303. I do. When the cache memory 231 receives the read access request 2309, when the data of the corresponding address is in the cache memory, the cache memory 231 puts the read data on the data bus 2300 and outputs an access end response 2310 to the control unit 232. If the corresponding data does not exist in the cache memory 231, the read address is turned on on the address bus 2307, and
A read access request signal 2305 is output to the main memory 24.
The main memory 24 to which the read request signal 2305 and the read access 2307 have been input turns on the data 2308 and turns on the access end signal 2306. When the access end signal 2306 is turned on, the cache memory 231 turns off the read request signal 2305 and the data 23 read from the main memory 24.
08 is cache memory 23 corresponding to read address 2100
After setting to the address in 1 and further turning on the bus 2300, an access end response signal 2310 to the control unit 232 is returned.

When the read access request is made to the input / output control device 25 through the signal line 2303, the data corresponding to the address 2100 is turned on on the data bus 2300, and then the end response signal is output.
2304 turns on. Then, the control unit 232 turns off the read access request 2303. Similarly, port for connecting shared memory
If a read access is made to the
After on-bus access to 2300, the access end response 2102 is turned on, and the control unit 232 turns off the read access request signal 2101 when the access end response 2102 is turned on. The control unit 232
When any one of the access end response signals 2102, 2306, and 2304 is turned on, the access end response signal 2301 is turned on to report to the basic processing unit 22 that the read access has been completed.

An operation example of the above embodiment will be described next. FIG. 7 shows write access to the shared memory 1 in the order of the processing units 3 and 4, and the write-accessed address of the processing unit 3 is
This is a lime chart of each signal when hitting to the cache memory. Bus occupancy request signal from processing unit 3
When 600 is turned on, the bus occupation permission signal 602 of the memory bus controller 12 processing device 3 is turned on. The port 14 turns on the write address 605 to the memory bus 16. When the on-bus write address hits the directory 131 in the port 13 to which the processing device 2 is connected, the invalidation request signal 606 (corresponding to the signal 2113 in FIG. 4) is turned on and is input to another processing device. Memory access suppression signal 607
(Corresponding to the signal 1310 in FIG. 4) is turned on. When the cache invalidation end signal (signal 2119 in FIG. 4) in the processing device 2 is turned on, the memory access suppression signal 607 is turned off.
Turn on 603 to execute access to the shared memory.

FIG. 7 shows a time chart of each signal when neither write address hits any cache memory when write access is made to the shared memory in the order of the processors 3 and 4. When the bus occupation request signal 700 from the processing device 3 is turned on, the memory bus controller 12 turns on the bus occupation permission signal 702 of the processing device 3. Port 1
3 When the bus occupation permission signal is turned on, the write address 705 is turned on on the bus 16 and the bus occupation request signal 700 is turned off. When the write access ends, the access end response signal 704 turns on, and the bus occupation permission signal 702 of the processing device 3
Is turned off, and the bus occupancy request signal 70
1 is turned on, and write access is performed as in the case of the processing device 3.

According to the present embodiment, the directory and valid bits of the shared memory and the cache for the shared memory of the processing device are:
Set both when accessing the shared memory and clear the valid bits of the corresponding directory when writing to another processing device.Therefore, the directory and valid bits are always guaranteed to match, and therefore shared by other processing devices. The necessity of disabling the shared memory cache in its own processing device at the time of writing to the memory can be checked at the corresponding port on the shared memory side, so the self-processing can be performed regardless of whether the data in the shared memory is updated by another processing device. Memory access and data processing in the device can be executed at high speed.

Next, another embodiment of the present invention will be described. In the above-described embodiment, when a write address from another processing device to the shared memory is hit in the directory in the shared memory 1, the valid bit in the shared memory port and the corresponding valid bit in the cache memory for the shared memory in the processing device. By clearing the bit, data mismatch between the shared memory and the cache memory was prevented. In this case, when the read access to the data of the invalidated address is issued from the processing device, the cache memory is missed, so that it is necessary to access the shared memory in the shared memory device. Therefore, in this embodiment, the data itself in the cache memory is updated without clearing the valid bit performed in the above-described embodiment. That is, the data in the cache memory in the own processing device corresponding to the write address of the other processing device is updated to the write data to the shared memory. By this,
When there is a read request for this data, the read access operation to the shared memory is not required. The operation of this application example will be described below.

A write access request signal 1311 from another processing device is input to the control unit 132 of the port 13 shown in FIG. 5, and data 1301 and address 2112 of the directory 131 when accessed at a lower address of this address 2112 When the high-order address of the data matches and the corresponding bit of the valid bit 134 is input to the control unit 132 by the signal 1302, the control unit 132 transmits the write data to the shared memory to the data bus 130.
5, the data bus 2116 is turned on, and the signal line 2113 is turned on to notify the control unit 214 (fourth step) that the write address has hit the directory 131 in the shared memory 1.
(Fig.) When the signal line 2113 is turned on, the control unit 214 controls the data memory 213 specified by the address 2112.
(Shared memory cache) data bus
A data update end signal 2119 is transmitted to the control unit 132 of the port 13 as the update data on-bused to 2116. In this way, in this embodiment, data matching between the shared memory and the cache memory is guaranteed, and the processing can be speeded up as in the embodiment of FIG.

〔Example〕

According to the present invention, a cache memory mechanism for a shared memory that does not affect the data processing inside the processing device can be configured, so that high-speed access to the shared memory can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a multi-CPU system showing one embodiment of the present invention, FIG. 2 is a block diagram showing an overall configuration of the multi-CPU system, FIG.
FIG. 3 is a diagram showing a configuration example of a shared memory connection port in FIG. 3, FIG. 5 is a diagram showing a configuration example of an interface port in the shared memory device, and FIG. 6 is a diagram showing a configuration of a memory control unit. 7 and 8 are time charts when the processing devices 3 and 4 make a write access to the shared memory. 1 Shared memory, 2 to 4 Processing device, 13 to 15 Port, 21 Shared memory connection port, 131, 211 Directory, 213 Data memory, 134,212 Valid bit, 132,214 Control unit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Yoshiaki Takahashi 5-2-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi, Ltd. (72) Soichi Takaya 5-2-2 Omikacho, Hitachi City, Ibaraki Prefecture No. 1 Inside the Omika Plant, Hitachi, Ltd. (72) Koji Ozawa, Inventor 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Inside the Omika Plant, Hitachi, Ltd. No. 2 Hitachi Control Systems Co., Ltd. (56) References IBM Louvnal of reeving and developing tent Volume 26, Number 1 R, N, Gustafson F. J. Spavacio Ianiy av 1982 P12-21 "IBM 3081 Processor Vnit: Design Considation and Decision Process"

Claims (6)

(57) [Claims] 1. A shared memory, comprising: a plurality of processing devices each including an interface means for the shared memory; wherein each of the interface means stores a first address of a part of the shared memory; A directory, data corresponding to the address, and a first indicating validity of the data.
In a multi-CPU system having shared memory cache memory means having a valid bit, a shared memory is provided with a port corresponding to each processing device individually,
Each of the ports has a second directory and a second directory controlled to match the contents of the first directory and the first valid bit of the interface means in the corresponding processing device.
When a write to the shared memory occurs from any of the processing devices, the address on the bus in the shared memory is referred to, and the write address is held in the second directory in its own port, and When the second valid bit in the own port corresponding to the set position is in the valid state, the valid bit in the own port is invalidated, and a signal for invalidating the first valid bit is transmitted to the corresponding processing device, and the write address Is not held in the second directory in the own port, or when the second valid bit in the port corresponding to the held position is in an invalid state, invalidation of the valid bit in the own port and into the corresponding processing device A multi-CPU system characterized by having an invalidating means for not transmitting the invalidating signal of the first valid bit. 2. A method according to claim 1, wherein each of said ports is provided with means for suppressing access to the shared memory from each processing device until the invalidation processing of the first and second valid bits by the invalidation means is completed. 2. The multi-CPU system according to claim 1, wherein: 3. A method according to claim 2, wherein said second means is provided by a signal from said invalidating means.
3. The effective memory cache memory according to claim 2, wherein a means for inhibiting access to the effective memory cache memory is provided until the invalidation of the effective bit is completed. Multi CPU system. 4. A shared memory, comprising: a plurality of processing devices each including a built-in interface with the shared memory, wherein each of the interface means stores a partial address of the shared memory; A directory, data corresponding to the address, and a first indicating validity of the data.
In a multi-CPU system having shared memory cache memory means having a valid bit, a shared memory is provided with a port corresponding to each processing device individually,
Each of the ports has a second directory and a second directory controlled to match the contents of the first directory and the first valid bit of the interface means in the corresponding processing device.
When a write to the shared memory occurs from any of the processing devices, the address on the bus in the shared memory and the write data are referenced, and the write address is held in the second directory in the own port. When the second valid bit in the own port corresponding to the held position is valid, the corresponding data in the cache memory means for shared memory in the corresponding processing device is updated to data for writing to the shared memory, When the write address is not held in the second directory in the own port, or when the second valid bit in the port corresponding to the held position is in an invalid state, the corresponding address in the shared memory cache memory means in the corresponding processing device. Data update means for not updating data for writing data to the shared memory Multi-CPU system according to claim. 5. The apparatus according to claim 1, wherein a means for suppressing access from each processing device to a shared memory is provided in each of said ports until said data updating means finishes updating said data. The multi-CPU system according to item 4. 6. The shared memory cache memory means includes means for inhibiting access to the shared memory cache memory means until the data updating means finishes updating the data. The multi-CPU system according to claim 5.