JPH0511337B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-computer device in which a plurality of processing devices share one memory device, and in particular, the present invention relates to a multi-computer device in which a plurality of processing devices share one memory device. This article relates to a multi-computer device.

[Conventional technology]

Conventionally, in order to increase the speed of a memory device shared by a plurality of processing devices, each processing device may be provided with its own cache memory. In this case, there is a problem in that data held in the cache memory of a certain processing device as a copy of data in a shared memory device may become inconsistent due to writing to the shared memory device of another processing device. An example of solving this problem is the system described in Japanese Patent Laid-Open No. 12020/1983. In this example, when one processing device writes to a shared memory device, it sends an update address to the other processing devices. Each processing unit determines whether the data at the update address is held in its own cache memory,
If it is held, the relevant valid bit is cleared, the data at the update address is invalidated, and the data mismatch between the shared memory device and the cache memory is resolved. In addition, the literature on the cache memory mechanism of multi-CPU systems is ``Computer Architecture and Parallel Processing''.
(McGraw-Hill Publishing, 1984, see paragraphs 7, 3, 3) (Computer Architecture and Parallel
Processing).

[Problem that the invention seeks to solve]

In the conventional example, the following problems occur.

1. Each processing device receives the reported update address independently from multiple other processing devices, so
The signal line of the interface becomes large and the multiplicity of the processing device is extremely limited. In order to avoid this, it is possible to send update addresses from a shared memory device to each processing device, but if the address is sent to distributed processing devices using the same throughput of the shared memory device's internal bus, it would be difficult to send an update address to a shared memory device with a high throughput. cannot be configured.

2 Update addresses received by each processing unit are given at the same rate as the throughput of the shared memory unit,
It is necessary to read the cache memory each time and determine whether the data at the corresponding address is held.
Access to the cache memory for data processing inside the processing device is restricted (access to the cache memory for internal data processing must be inhibited while an update address is being determined).

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a multi-computer device that can be applied to a shared memory device with high throughput.

[Means for solving the problem] The above purpose is to enable a processing device equipped with a directory that monitors access from its own processing device and determines whether or not the relevant data is in its own cache memory, together with other processing devices. In a multi-computer device connected to a shared memory device, the processing device having the cache memory has means for inhibiting access to its own cache memory by internal data processing only when an invalidation request is received from the shared memory device. , further comprising means for invalidating data corresponding to the invalidation request in the cache memory, wherein the shared memory device is a directory having the same content as the directory of the cache memory, and the shared memory device is a process that includes the cache memory. A directory that monitors write access to the shared memory device by a processing device other than the device and determines whether or not to cache, and invalidates the corresponding data when the directory is determined to be cached. and means for requesting a processing device with a directory of contents.

[Effect]

The directory on the cache memory side only monitors access from its own processing device, and when another processing device updates data in the shared memory device, there is no need to judge whether to cache or not. Therefore, a processing device equipped with a cache memory can access its own cache memory even while the directory provided on the shared memory device side is determining the cache hit. In addition, since the shared memory device requests invalidation when cached, fewer signal lines are needed to connect the shared memory device and the processing device compared to the conventional case where all addresses are transferred to the processing device. . Furthermore, since the shared memory device is configured to perform cache hit determination, it is possible to accept the next write access without waiting for address transfer to the processing device or hit determination on the processing device side, which shortens the write cycle. , a system with high throughput can be constructed.

〔Example〕

FIG. 2 shows the overall configuration of the multi-computer device.
This multi-computer device consists of multiple processors (CPUs) 2, 3, and 4, and a shared memory device (GM).
1, and each CPU 2, 3, 4 and GM 1 are connected via interfaces 5, 6, 7. CPUs 2, 3, and 4 GM1 are shared and used in a time-sharing manner.

FIG. 3 shows the internal configuration of the CPU 2. other CPU
CPU 2 includes a shared memory interface (CMP) 21 and an arithmetic unit 50. GMPG 21 is provided between interface 5 and arithmetic unit 50. Arithmetic unit, memory control unit (MCU)
23, main memory device (PM) 24, I/O control device (IOADPT) 25, basic processing unit (BPU) 22,
File control processor (FCP) 26, I/O
Control processor (IOP) 28, internal common bus 3
4. It consists of a file device 27.

The BPU is a unit that executes instructions, and reads instructions and reads/writes data using the bus 30.
The request is made to the MCU 23 through.

MCU23 passes through buses 31, 32, 33,
Connected to GMP21, PM24, and IOADPT25, respectively. IOADPT is FCP through bus 34
26 and I/O control processor 26.

FCP 26 connects file device 2 via bus 35.
Connected to 7. GMP21 is a device that controls access to GM1, and is connected to GM1 through interface 5.

In this CPU 2, a calculation unit 50 performs predetermined calculations. At that time, the data in GMP 21 is also used for calculation. PM24 is used to store data and the like. Data is exchanged with the file device 27 and IOP28 using the bus 34, IOADPT25, and MCU2.
The BPU 22 performs the processing via 3. Furthermore, GMP21 intervenes and performs relay between GM1 and GM1. this
GMP21 has internal cache memory.

Figure 4 shows an example of the internal configuration of GM1. GPU2
-4 are connected to interface ports PORT13-15 through interfaces 5-7, respectively. PORT13-15 are memory bus 16
Read access and write access to the memories (M) 110 to 112 are performed through the memory (M) 110 to 112. Memory bus controller (MB CONT) 12 is PORT13-15
performs exclusive right control of accesses requested through the memory bus 16.

Now, FIG. 1 shows an embodiment of the present invention. This example is a combination of FIG. 3 and FIG. 4,
The feature in this figure is that a directory section 13a corresponding to the directory section 21a (conventionally known) in the GMP21 in the CPU2 is provided in the PORT13 in the GM1.

Further, the configuration will be explained.

In FIG. 1, the internal execution unit (EU) 50 of the processing unit (CPU) 2 is normally connected to a shared memory interface port (GMP 21).
Data processing is performed using the internal cache memory, and an interface port (PORT) 13 monitors data updates in the shared memory device from other processing devices CPU3 and CPU4.

The PORT 13 has an internal directory section 13a having the same contents as the cache memory in the GMP 21, and determines whether an update address to be placed on the memory bus 16 exists in the directory section 13a. Therefore, data processing within the processing device and data update monitoring of the shared memory device can be processed in parallel. Furthermore, when an update address exists in the directory section 13a (hereinafter referred to as a hit), the PORT 13 issues a memory access suppression request to the memory bus controller (MB CONT) 12 through the bus 16, and requests the CPU 2 to invalidate the cache memory. The request and the invalidation address are sent through the interface 5. The CPU 2 invalidates the data in the cache memory corresponding to the reported address. This ensures that the data in the shared memory device and the cache memory match. In addition, it is thought that the probability that an update address will hit the directory in PORT13 is low (normally, there are few processes in which multiple processing devices widely use the same area), so even if the transfer speed to the update address processing device is slowed down, The proportion of the period during which the memory bus 16 is inhibited is sufficiently small. This is true regardless of the throughput of the memory bus 16.
This means that the speed of update address transfer of the interface 5 can be determined. Furthermore, time-division transfer of updated addresses is also possible, and the number of interface signal lines can be reduced.

FIG. 5 shows details of an example of the internal configuration of the GMP 21. The contents of the connection bus 31 with the MCU 23 are shown below. 2100 is an address bus, 2103 is a read data bus, 2104 is a write data bus,
101 is an access request signal and a read or write identification signal, and 2102 is an access end response signal. When there is a read access from the MCU 23, the directory 211, valid bit section (V) 212, and data section 213 of the cache memory are accessed using the lower bits of the address 2100.
Comparator (COMP) 214 is directory 211
Data 2105 and address 21 read from
The upper bits of 00 are compared, and if they match, the signal line 2117 is turned on. V212 turns on the signal line 2118 if there is valid data. When 2117 and 2118 are ON, signal line 2110 is ON
Then, it reports to the control 216 that data corresponding to address 2100 is present in the cache memory. The controller 216 is connected to the signal line 2110
is turned ON, the signal line 2102 is turned ON, and the data read from the data section 213 is transferred to the signal line 2.
Pass it to MCU23 through 103. Also, signal line 2
If 110 is OFF, there is no valid data in the cache memory, so controller 216 sends a read access request to GM1 through signal line 2114. 2115 is the access end response from GM1, and when 2115 is ON, the read data from GM1 is transferred to the read data bus 2116.
The controller 216 takes the data into the read data register (RDR) 218 and then transfers the data to the data section 213 of the cache memory.
Write the output of the RDR 218 to the signal line 2107, and at the same time write the upper bits of the address 2100 to the directory 211,
Turn on bit 09 and turn on the corresponding bit of V212.
Further, when a write access request is received from the MCU 23 through the signal line 2101, the controller 216 sends the write access request to the GM 1 through the signal line 2114. At this time, the write data is transmitted through signal lines 2104 and 2116.
Sent to GM1. Also, if the cache memory is hit and the signal line 2110 is turned on,
Data on the signal line 2104 is written to the data section 213. A signal line 2113 is a data invalidation request signal from GM1, and a signal line 2112 is a block address (lower bits of the entire address) of the cache memory to be invalidated. Signal line 2113
When ON, the controller 216 stores the block address 2112 in the address register (AR) 217.
The address is specified using the output signal 2106 of the AR217, and the signal line 2108 is turned on to clear the corresponding valid bit. At this time, the MCU
Access end response 2 for access from 23
102 is suppressed.

Figure 6 shows the internal configuration of PORT13. CPU
2, when a read access request is input to the controller 133 through the signal line 2114, a memory bus occupancy request is input through the signal line 1308.
Output to MBCONT12. Bus occupancy permission signal 1
When 309 is turned on, the address signal 2100 from the CPU 2 is output to the address bus 1313, the signal line 1308 is turned off, and the read request signal 1307 is turned on. Furthermore, access end response 1
When 300 is turned ON, the completion response signal 2115 to CPU 2 is turned ON and read data is sent to CPU 1 through signal lines 1304 and 2116. Also, the upper part of the address is written in the directory 131, and the corresponding bit in the valid bit part is set. After that, connect signal lines 1308 and 2115 to
Turn off. Furthermore, when a write access request is input from the CPU 2 to the controller 133 through the signal line 2114, a memory bus occupancy request is output to the MBCONT 12 through the signal line 1308, and when the bus occupancy permission signal 1309 turns ON, the address signal 2100 from the CPU 2 is output. output to the address bus 1313, and output the write data signal 2116 from the CPU 2 to the write data bus 1304;
Turn off signal line 1308 and write request signal 13
12 and output as a write request signal 1306.
Furthermore, when the access end response 1300 turns ON, the access end is sent through the signal line 2115.
Report to CPU2.

Directory 131 and valid bit section (u) 134
are read at the lower address of the address signal 2112 of the memory bus 16, and the respective signal lines 130
1,1302. Comparator (COMP)
132 compares the upper address of the signal line 2112 and the directory output signal 1301, and when they match,
Turn on the signal line 1314. When both signal lines 1302 and 1314 are turned ON, this indicates that data at the address being accessed on the memory bus 16 exists in the cache memory of the CPU 2, and the signal line 1303 is turned ON. At this time, if the access on the memory bus is a write access, the signal line 1306,
Turn on 1311. The controller 133 sends out a data invalidation request signal 2113 when the signal lines 1303 and 1311 are both turned ON and the controller 133 is not currently accessing itself. At this time, the block address to be invalidated is sent to the CPU 2 via the signal line 2112.
passed to. At the same time, the memory access inhibit signal 1310 is turned on. Also, the corresponding bit of V134 is invalidated. As described above, the directories of the shared memory and the processing device are set together when data is read from the shared memory, and cleared together when data is written by another processing device, so that coincidence is always guaranteed.

FIG. 7 shows the configuration of the cache memory. This embodiment is a set associative cache memory with 4 bytes per entry, and a total of 10
It has a capacity of 24 entries (4KBytes). Also,
directory section 211, valid bit section (u) 212,
The data section 213 is located in the same RAM (Ranclom Access
(Memory) and lower address (AL)
As a result, the data in the directory section, valid bit section, and data section of the corresponding entry are read out.
The operation of the cache memory shown in FIG. 5 will be explained using FIG. 7.

In FIG. 5, when reading data from the cache, one of the entries is selected by the lower bit (AL) of address 2100 (consisting of AU and AL), and the upper address of the data stored in that entry is the directory. part 2
The COMP 214 compares the data of the upper address (AU) and 2105. When the comparison results match and the data 2118 read from the valid bit part (u) is "1",
2103 read from the data section is valid (referred to as cache).

When writing data to the cache, select the entry by the lower address (AL) of address 2100,
2100 upper (AU) in the directory part,
Input "1" to the valid bit part and write data to the data part (the valid bit part is connected to the signal line 210).
9 is turned ON, “1” is selected as input data).

When the signal line 2113 is ON, in order to invalidate the cache, select the entry using the address 2106 (this address is only the lower part of the 32-bit address) and set "0" to the input data in the valid bit section. Input and write (input data "0" is selected in the valid bit part by turning on the signal line 2108).

〔Effect of the invention〕

According to the present invention, it is possible to configure a shared memory cache memory that does not affect the internal data processing of a processing device, and it is also applicable to a shared memory device with high throughput.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the overall configuration of a shared computer device to which the present invention is applied, and FIG.
The figure shows an example of the internal configuration of CPU2, Figure 4 shows an example of the internal configuration of GM1, Figure 5 shows an example of GMP21, Figure 6 shows an example of PORT13, and Figure 7 shows a detailed example of cache memory. It is a diagram. 1...Shared memory device (GM), 2, 3, 4...
...Processor (CPU), 13, 14, 15... Port, 13a, 21a... Directory section.

Claims (1)

[Scope of Claims] 1. A processing device equipped with a directory that monitors access from its own processing device and determines whether or not the corresponding data is in its own cache memory has connectivity to a shared memory device together with other processing devices. In the multi-computer system, the processing device having the cache memory includes means for inhibiting access to its own cache memory by internal data processing only when an invalidation request is received from the shared memory device; The shared memory device includes means for invalidating data corresponding to the memory invalidation request, and the shared memory device is a directory with the same contents as the directory of the cache memory, and the shared memory device is a directory other than a processing device equipped with the cache memory. A directory that monitors write access to the shared memory device by the processing unit and determines whether or not to cache, and a directory that has the same content as the directory that invalidates the corresponding data when it is determined that the directory is cached. 1. A multi-computer device comprising: means for requesting a processing device provided therein. 2. The multi-computer device according to claim 1, wherein the invalidation request is made using an entry number of a cache memory. 3. The multi-computer device according to claim 1 or 2, wherein the shared memory device includes means for inhibiting memory access while outputting the invalidation request.