JP3219573B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a wiring layer using aluminum.

[0002]

2. Description of the Related Art Higher speed and higher integration of semiconductor devices are still in progress at present, and miniaturization of elements is actively introduced as a means for realizing this. With such miniaturization of elements, it has become difficult to connect (contact) wiring to a silicon substrate or another wiring.

An aluminum alloy is most frequently used as a wiring material for semiconductor devices (particularly LSIs). The wiring using the aluminum alloy is connected to a substrate or another wiring via a contact hole opened in the interlayer insulating film. However, when the aspect ratio of a contact hole (hole depth / hole diameter) increases with miniaturization, conventional aluminum alloy film forming techniques, such as sputtering, require sufficient step coverage (step coverage). ) Can not be obtained. as a result,
The aluminum alloy cannot be sufficiently buried in the contact hole, and a good contact cannot be obtained.

Therefore, various proposals have been made on a method of forming a wiring layer capable of improving the step coverage and obtaining a good contact. For example, a tungsten plug technology using a blanket tungsten-CVD method is being studied.

Further, a reflow sputtering method using an alloy of aluminum and germanium has been studied (K. Kikuta et al; Proc. Of 1991 Symp. On VLSI Tech.,
pp35-36.). Hereinafter, the outline of the manufacturing process of the wiring layer by the same method will be sequentially described with reference to the cross-sectional view shown in FIG.

Step 1 (see FIG. 2A): An element isolation region 22 and a MOS transistor 23 are formed on the surface of a single crystal silicon substrate 21. Note that MOS transistor 2
Reference numeral 3 denotes a gate oxide film 23a, a gate electrode 23b made of polysilicon, a source region and a drain region 23c. Next, an interlayer insulating film 24 of a silicon oxide film is deposited on the entire surface of the silicon substrate 21 including the element isolation region 22 and the MOS transistor 23. Then, a contact hole 25 is opened in the interlayer insulating film 24 on the source region and the drain region 23c.

Step 2 (see FIG. 2B): A titanium layer 26 and a titanium nitride (TiN) layer 27 are sequentially deposited on the entire surface of the silicon substrate 21 including the contact holes 25 by using magnetron sputtering. Let it. The titanium layer 26 and the titanium nitride layer 27 constitute a barrier metal layer.

Step 3 (see FIG. 2C): The silicon substrate 21 is heated so that the temperature thereof (hereinafter referred to as the substrate temperature) becomes about 300 ° C. Then, while heating, an aluminum alloy layer 28 is deposited on the titanium nitride layer 27 by a magnetron sputtering method using an aluminum-germanium alloy (Al-5% Ge) target. As a result, the source and drain regions 23c of MOS transistor 23 are in contact with aluminum alloy layer 28 via barrier metal layers (titanium layer 26 and titanium nitride layer 27) in contact hole 25.

At this time, the eutectic temperature of the alloy of aluminum and germanium is sufficiently lower than the melting point of aluminum alone. Therefore, even if the aluminum alloy layer 28 is formed by sputtering at a substrate temperature of about 300 ° C., the aluminum alloy layer 28 exhibits high fluidity and is sufficiently embedded in the fine contact holes 25. Therefore,
The step coverage of the aluminum alloy layer 28 in the contact hole 25 can be sufficiently ensured, and a good contact can be obtained.

The reason why the barrier metal layers (titanium layer 26 and titanium nitride layer 27) are provided is that the reaction between the aluminum alloy layer 28 and the silicon substrate 21 in the contact hole 25 is suppressed and the bonding layer is broken. This is to prevent Also, this is to prevent stress migration of the aluminum alloy layer 28 (a defect in which the aluminum alloy layer 28 moves and breaks due to stress (mainly thermal stress) exerted on the aluminum alloy layer 28 by the interlayer insulating film 24).

By the way, it is known that even in the reflow sputtering method using aluminum alone, a high fluidity is exhibited when a sputter film is formed at a substrate temperature of 500 ° C. or more. For example, titanium or titanium nitride is used as a barrier metal layer, and an alloy of aluminum and silicon (Al-1% Si) is formed by sputtering at a substrate temperature of about 500 ° C., so that the hole diameter is 0.25 μm and the aspect ratio is It has been reported that 3.2 contact holes are embedded (Koyama et al .; IEICE Technical Report SDM91-130, Vol.9)
1, No.332, pp1-6, 1991.). In this example, an aluminum alloy containing 1% silicon is used instead of aluminum alone, but silicon is added here to prevent the generation of alloy spikes. They may be considered equivalent.

[0012]

However, the conventional method has the following problems. In the tungsten plug technology using the blanket tungsten-CVD method, it is necessary to add a step of forming a tungsten layer, which complicates the process, and requires a CVD apparatus for tungsten, thus increasing the scale of manufacturing equipment. I do.

In the reflow sputtering method using an alloy of aluminum and germanium shown in FIG.
In order to realize filling in fine contact holes using fluidity, it is necessary to set the film formation rate as low as about 0.1 μm / min. Therefore, the throughput is deteriorated. For example, it takes 10 minutes to form the aluminum alloy layer 28 having a thickness of 1 μm, which is not practical. Further, since as much as 5% of germanium is added, the specific resistance of the entire wiring layer is increased by about 15% as compared with the case of using aluminum alone, which is disadvantageous for increasing the speed of the element.

Further, in the reflow sputtering method using aluminum alone (or an alloy of aluminum and silicon) to which germanium is not added, since the substrate temperature needs to be set to 500 ° C. or higher, alloy spikes are easily generated. . Therefore, as in the above example, it is conceivable to add silicon or provide a barrier metal layer. However, it is still impossible to completely suppress the generation of alloy spikes, which may cause a junction leak in a contact hole. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has good step coverage and low resistance.
Simple manufacturing that can form a simple wiring layer in a short time
It is to provide a method.

[0016]

[Means for Solving the Problems]

According to the first aspect of the present invention, the temperature at which a solid phase reaction with aluminum is caused by sputtering is 30 ° C.
Forming a metal layer is less than 0 ° C., the solid phase reaction
Forming a single aluminum layer or an aluminum alloy layer on the metal layer by a sputtering method using a temperature at which the solid phase reaction does not occur.
A step of forming an aluminum single layer or an aluminum alloy layer thicker than the wiring layer on the wiring layer obtained in the above step by the used sputtering method.

The invention according to claim 2 is the invention according to claim 1.
Forming the metal layer.
Prior to the step of forming a barrier metal layer
That is the gist.

[0019]

[0020]

[Action]

According to the first aspect of the present invention, in the step of forming an aluminum single layer (or an aluminum alloy layer) on the metal layer by a sputtering method, a solid phase reaction occurs between the metal layer and aluminum, An aluminum alloy layer having good step coverage is formed.

At this time, in order to improve the step coverage of the aluminum alloy layer, it is necessary to reduce the film forming speed. However, since the thickness of the aluminum alloy layer is small, the deposition time does not increase. Conversely, the aluminum alloy layer may be formed to have a minimum necessary film thickness for ensuring step coverage. Then, an aluminum single layer (or an aluminum alloy layer) is formed thick on the thin aluminum alloy layer, so that the entire wiring layer has a desired thickness. At this time, aluminum alone layer (or aluminum alloy layer)
Does not affect the step coverage, so that the film formation speed may be increased. Therefore, even if the thickness of the aluminum single layer (or aluminum alloy layer) is large, the film formation time does not become long. Therefore, the entire wiring layer can be formed in a short time.

[0023]

According to the second aspect of the present invention, the characteristics of the wiring layer can be further improved by adding a barrier metal layer.

[0025]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing a process of manufacturing a wiring layer according to an embodiment of the present invention. In this embodiment, the same components as those of the conventional example shown in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

Step 1 (see FIG. 1A): An element isolation region 22 and a MOS transistor 23 are formed on the surface of a single crystal silicon substrate 21. Note that MOS transistor 2
Reference numeral 3 denotes a gate oxide film 23a, a gate electrode 23b made of polysilicon, a source region and a drain region 23c. Next, the element isolation region 2 is formed using the CVD method.
Substrate 2 including MOS transistor 2 and MOS transistor 23
1, an interlayer insulating film 24 made of a silicon oxide film
(Thickness: 600 nm) is deposited. Then, a contact hole 25 is opened in the interlayer insulating film 24 on the source region and the drain region 23c. Subsequently, a titanium layer 26 (thickness: 50 nm) and a titanium nitride (TiN) layer 27 (thickness: 100 nm) are sequentially deposited on the entire surface of the silicon substrate 21 including the contact holes 25 by magnetron sputtering. . The titanium layer 26 and the titanium nitride layer 27 constitute a barrier metal layer.

Step 2 (see FIGS. 1B and 1C): A germanium layer 11 is deposited on the titanium nitride layer 27 by magnetron sputtering. Next, heating is performed so that the substrate temperature becomes about 300 ° C. Then, while heating, an alloy of aluminum, silicon and copper (Al-
An aluminum alloy layer 12 (film thickness 100 nm) was formed on the germanium layer 11 by a magnetron sputtering method using a 1% Si-0.5% Cu) target at a deposition rate of 0.1 μm /
Deposit about min.

At this time, in FIG. 1B, the germanium layer 11 and the aluminum alloy layer 12 are
It is shown as being stacked in a layered structure. However, actually, as shown in FIG. 1C, when the aluminum alloy layer 12 is formed, the deposition proceeds while the germanium in the germanium layer 11 reacts with the aluminum in the aluminum alloy layer 12, and the germanium is removed. A single aluminum alloy layer 13 is formed.

The aluminum alloy layer 13 is formed slowly (at a film forming rate of about 0.1 μm / min), exhibits high fluidity, and grows along the inner wall of the contact hole 25 while being migrated. Therefore, the aluminum alloy layer 13
Does not show any deterioration in step coverage as in the case where only the aluminum alloy layer 12 is deposited without providing the germanium layer 11. That is, the thickness of the aluminum alloy layer 13 becomes uniform regardless of the location, and the interlayer insulating film 2
The thickness of the aluminum alloy layer 13 formed on the substrate 4 is substantially equal to the thickness of the aluminum alloy layer 13 formed on the inner wall and the bottom of the contact hole 25.

Step 3 (see FIG. 1 (d));
Heat to about 50 ° C. (temperature at which no solid-state reaction between aluminum and germanium is observed). And
While heating, an alloy of aluminum, silicon and copper (A
An aluminum alloy layer 14 (thickness: 500 nm) is formed on the aluminum alloy layer 13 by a magnetron sputtering method using a (1-1% Si-0.5% Cu) target at a deposition rate of 1 μm / mi.
Deposit about n. Thereafter, patterning is performed by a normal photolithography process, and the wiring layers (titanium layer 26, titanium nitride layer 27, and aluminum alloy layers 13 and 14) formed in the above-described steps are etched to perform a wiring manufacturing process. finish. As a result, M
The source region and the drain region 23c of the OS transistor 23 are connected to the barrier metal layer (the titanium layer 26 and the titanium nitride layer 27) in the contact hole 25.
And an aluminum alloy layer 13 via the aluminum alloy layer 13.

As described above, in this embodiment, first, the germanium layer 11 (film thickness 50) is formed on the barrier metal layer.
nm). Next, a thin aluminum alloy layer 12 (Al-1% Si-0.5%) was formed on the germanium layer 11 by a high-temperature sputtering method at a substrate temperature of about 300 ° C.
(Cu, film thickness: 100 nm) is formed slowly (film formation rate: about 0.1 μm / min). At this time, the germanium layer 1
1 reacts with the aluminum alloy layer 12 to form the aluminum alloy layer 13 having high fluidity, so that the fine contact holes 25 are sufficiently filled. Subsequently, a thick aluminum alloy layer 14 is formed on the aluminum alloy layer 13 by a normal sputtering method at a substrate temperature of about 150 ° C.
(Al-1% Si-0.5% Cu, film thickness 500 nm) is rapidly formed (film formation speed is about 1 μm / min).

That is, in the present embodiment, although high fluidity is exhibited, the film formation rate is low, and a high-resistance aluminum alloy layer 13 containing germanium is formed thin beforehand, thereby ensuring sufficient step coverage. I have. Thereafter, the film thickness is high and the aluminum alloy layer 14 with low fluidity is low because of low resistance because it does not contain germanium, so that the film thickness of the wiring layer is sufficiently ensured.

As a result, according to this embodiment, the aluminum alloy layer 13 having a thickness of at least 120 nm can be deposited on the inner wall of the contact hole 25 having a hole diameter of 0.6 μm and an aspect ratio of 1. Of course, by changing the thickness of the germanium layer 11 and the aluminum alloy layer 12, the thickness of the aluminum alloy layer 13 on the inner wall of the contact hole 25 can be arbitrarily changed.

According to the present embodiment, the following effects can be obtained. By forming the aluminum alloy layer 14 having a high film forming speed to be thick, the production of the wiring layer can be completed in about 1/5 of the conventional method shown in FIG.

By forming the low-resistance aluminum alloy layer 14 thicker, the specific resistance of the entire wiring layer can be reduced by about 10% as compared with the conventional method shown in FIG. Becomes By the way, germanium layer 1
1 and the aluminum alloy layer 14 are omitted.
In comparison with the case where only the wiring layer is formed, the increase in the specific resistance according to the present embodiment is only about 3%, and there is no practical problem at all.

Each layer constituting the wiring layer (titanium layer 26,
(Titanium nitride layer 27, aluminum alloy layers 13, 14)
Can be formed by a sputtering method, so that the process is not complicated and the manufacturing equipment is not enlarged.

Since the substrate temperature is not set to 300 ° C. or higher, alloy spikes are less likely to occur. Therefore, silicon is added to aluminum (aluminum alloy layers 11, 1).
4) Only by providing the barrier metal layers (titanium layer 26 and titanium nitride layer 27), the generation of alloy spikes can be completely suppressed. Therefore, there is no possibility of causing a junction leak in the contact hole 25.

The present invention is not limited to the above embodiment, but may be implemented as follows. 1) One of the titanium layer 26 and the titanium nitride layer 27 constituting the barrier metal layer is omitted. In addition, another appropriate thin film (for example, titanium tungsten, molybdenum silicide, or the like) is appropriately combined and used as the barrier metal layer. In the above embodiment, the reason why the barrier metal layer is provided is that the reaction between the aluminum alloy layers 13 and 14 and the silicon substrate 21 in the contact hole 25 is suppressed,
This is for preventing the destruction of the bonding layer. Further, stress migration of the aluminum alloy layers 13 and 14 (a defect that the aluminum alloy layers 13 and 14 move due to stress (mainly thermal stress) exerted on the aluminum alloy layers 13 and 14 by the interlayer insulating film 24 and leads to disconnection) is prevented. That's why. Therefore, even if the barrier metal layer is omitted, it is possible to obtain the same effect as that of the above-described embodiment (a wiring layer having good step coverage and low resistance can be formed).

2) One of silicon and copper is omitted from the aluminum alloy layers 11 and 14. In the above embodiment, the reason why silicon is added to the aluminum alloy layers 11 and 14 is to suppress the generation of alloy spikes. The reason why copper is added to the aluminum alloy layers 11 and 14 is to improve resistance to electromigration and stress migration. Therefore, even if silicon and copper are omitted, the same effect as in the above embodiment can be obtained.

3) An appropriate substance (titanium, palladium, scandium, or the like) for improving the characteristics of the wiring layer is added to the aluminum alloy layers 11 and 14. Aluminum alloy layer 1
Replace 1,14 with aluminum alone.

4) The present invention is applied to a wiring layer at a step portion other than a contact hole. 5) The germanium layer 11 is replaced with an appropriate metal layer that causes a solid-phase reaction with aluminum at a low melting point and low resistance.

6) Germanium layer 11 and aluminum alloy layer 1
2 is not sequentially deposited, but is formed on the titanium nitride layer 27 by a reflow-sputtering method (substrate temperature: about 300 ° C.) using an alloy target of aluminum and germanium. The alloy layer 13 is slowly and thinly deposited. Thereafter, a thick aluminum alloy layer 14 is rapidly deposited on the aluminum alloy layer 13 as in the above embodiment. That is, FIG.
In the conventional example shown in FIG. 1, an aluminum alloy layer 28 is deposited thinly, and then a thick aluminum alloy layer 14 is rapidly deposited on the aluminum alloy layer 28. In this case, the same effect as in the above embodiment can be obtained.

7) The above-mentioned items 1) to 6) are appropriately combined.

[0044]

As described above in detail, according to the present invention, there is an excellent effect that a wiring layer having good step coverage and low resistance can be formed in a short time by a simple manufacturing method.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a conventional example.

[Explanation of symbols]

11 Germanium layer as metal layer which causes solid phase reaction with aluminum at low resistance and low melting point 12, 14 Aluminum alloy layer (Al-1% Si-0.5%
Cu) 13 Aluminum alloy layer containing germanium 26 Titanium layer forming barrier metal layer 27 Titanium nitride layer forming barrier metal layer

Claims (2)

(57) [Claims] 1. A step of forming a metal layer (11) having a temperature at which a solid phase reaction with aluminum is lower than 300 ° C. by a sputtering method, and forming the metal layer by a sputtering method using the temperature at which the solid phase reaction is caused. A step of forming an aluminum single layer or an aluminum alloy layer (12) on the layer (11), and a sputtering method using a temperature that does not cause the solid phase reaction, on the wiring layer obtained in the above step. Forming a single aluminum layer or an aluminum alloy layer (14) thicker than the wiring layer. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming barrier metal layers (26, 27) prior to the step of forming said metal layer (11). Semiconductor device manufacturing method.