JP3134530B2 - FSK receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to a mobile communication receiver.

[0002] The present invention relates to FSK (Frequency Shift Keyin).
g) Use for receivers. In particular, PLL (Phase Locked Lo)
op) The present invention relates to a technique for reducing current consumption of a quadrature detection receiver using a local oscillation circuit.

[0003] The present invention is used for a call waiting type receiving apparatus that performs battery saving.

[0004]

2. Description of the Related Art In recent years, receivers have been reduced in size due to advances in integrated circuit technology. However, taking the wireless unit as an example, the basic system of the circuit is the same, so that integration is impossible or the limit of miniaturization is approaching due to the presence of difficult elements. For example, in a superheterodyne receiver, a high-frequency or intermediate-frequency filter or the like requires a large area. Therefore, a quadrature detection reception system has been considered for reducing the size and weight.

In the quadrature detection reception system, the line frequency and the local oscillation frequency are equalized, the beat of the reception frequency and the local oscillation frequency are extracted by a mixer, only the baseband signal is extracted by a low-pass filter, and the beat is amplified by a limiter circuit. In this method, a demodulation signal is obtained by performing demodulation processing after restriction.

The quadrature detection receiving method is characterized in that the intermediate frequency becomes zero because the local oscillation frequency and the line frequency match, so that there is no image frequency.

This means that high-frequency amplifiers and intermediate-frequency amplifiers do not require any highly selective filters for attenuating image frequencies.

Further, a channel filter for attenuating adjacent channel interference waves can be constituted by a low-frequency active filter because the intermediate frequency is zero, and can be realized on an integrated circuit.

Further, as a conventional technique, an FSK using a PLL technique capable of handling many line frequencies with one crystal resonator is used.
There is a receiver.

When the line frequency is set according to the area as in the selective calling receiver, when the called party moves to another area, the selective calling receiver with the fixed local oscillation frequency cannot call. On the other hand, a selective calling receiver using a PLL for a local oscillation circuit can call without any problem. As described above, by using the quadrature detection reception method, it becomes possible to eliminate a high frequency filter, an intermediate frequency filter, and the like.
Weight reduction becomes feasible.

Since the use of the quadrature detection reception system eliminates the need for a high-frequency filter or the like, it is not necessary to change the high-frequency filter for each frequency, which is required in the single superheterodyne system.

[0012]

However, compared to a fixed crystal oscillation circuit, the PLL local oscillation circuit has a problem that current consumption increases due to PLL control. That is,
When the timing of the signal of the own station arrives according to the battery saving rule, it is necessary to start the PLL circuit slightly before the timing start time and to stabilize the oscillation frequency of the PLL circuit. Particularly in a selective calling receiver which is driven by a battery and has a small capacity of the battery, the battery life is shortened, which is a serious problem.

The present invention has been made in such a background, and an object of the present invention is to provide an FSK receiver that consumes low power even when a PLL local oscillation circuit is used.

[0014]

SUMMARY OF THE INVENTION The present invention provides a high-frequency amplifier for receiving and amplifying a modulated wave frequency-modulated by a binary digital signal, a PLL local oscillation circuit, and a line output from the PLL local oscillation circuit. A mixer circuit for generating a baseband signal from the same local oscillation frequency as the frequency and the modulated wave, a quadrature detection demodulation circuit for processing the baseband signal to obtain a demodulated signal, and performing bit synchronization and frame synchronization based on the demodulated signal. An FSK receiver includes a synchronization detection circuit for outputting a synchronization signal, and an intermittent reception circuit for stopping reception at timings of signals other than the own group in accordance with the battery saving rule.

Here, the feature of the present invention is that a frequency difference between the line frequency and the local oscillation frequency is detected from the baseband signal, and a detection signal is output when the frequency difference exceeds a preset value. A frequency detection circuit,
And a control circuit for outputting a control signal for controlling the operation of the PLL local oscillation circuit using the detection signal. The control circuit includes: Means for starting the operation of the PLL local oscillation circuit earlier by a preset time at the timing of (1).

The frequency detection circuit includes: means for outputting a frequency detection signal of the baseband signal; means for outputting an average voltage of the frequency detection signal; means for superimposing an offset voltage on the average voltage; It is preferable that the apparatus further comprises means for comparing the frequency detection signal with the output from the superimposing means and outputting the detection signal.

[0017]

The frequency detecting circuit monitors the carrier wave synchronization state, and when detecting that a slight loss of synchronization has occurred, sends a detection signal to the control circuit.

The control circuit controls the PLL operation. When no detection signal is sent from the frequency detection circuit, the PLL circuit operates.
Since there is no deviation in the oscillation frequency of the local oscillation circuit, it is determined that the PLL advance operation time is short, and the PLL advance operation time is reduced. Only when the out-of-synchronization is detected, the PLL preceding operation is performed earlier.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

The present invention provides a high-frequency amplifier 101 for receiving and amplifying a modulated wave frequency-modulated by a binary digital signal.
A PLL local oscillation circuit 109, a mixer circuit 102 for generating a baseband signal from the modulated local wave and the same local oscillation frequency as the line frequency output from the PLL local oscillation circuit 109, and a signal processing of the baseband signal. A quadrature detection demodulation circuit 105 that obtains a demodulated signal by performing a bit synchronization and a frame synchronization based on the demodulated signal, and a synchronization circuit 114 that outputs a synchronization signal. The FSK receiver includes an intermittent operation circuit 115 for stopping the operation.

Here, a feature of the present invention is that a frequency difference between the line frequency and the local oscillation frequency is detected from the baseband signal, and a detection signal is output when the frequency difference exceeds a preset value. Frequency detection circuit 11
0 and the PLL local oscillation circuit 109 using this detection signal.
And a control circuit 113 for outputting a control signal for controlling the operation of the control circuit 113. When the detection signal is input to the control circuit 113, the control circuit 113 outputs a control signal for a preset time at the timing of the next group signal to be received. Early PL
There is a means for starting the operation of the L local oscillation circuit.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a diagram illustrating a signal state when a modulated signal is detected. FIG. 3 is a diagram showing a demodulation circuit.

The received wave frequency-modulated by the binary digital signal is amplified by the high-frequency amplifier 101, divided into two, and input to the mixer circuit 102, respectively. Further, the local oscillation frequency is shifted by 90 degrees from the voltage-controlled oscillation circuit 111.
And the phases are rotated by +45 degrees and −45 degrees, respectively, and input to the mixer circuit 102. By adopting such a circuit configuration, a signal whose phase is shifted by 90 degrees is
02 is frequency-converted to baseband and output.
As described above, since the line frequency matches the local oscillation frequency, the baseband signal becomes the beat frequency. The low-pass filter 103 extracts only the baseband signal and limits the band of noise. Each of the baseband signals is input to the limiter circuit 104 to obtain binarized signals I and Q. This signal waveform is as shown in FIG. Here, the data indicates a modulation signal. Inputting the signals I and Q to the demodulation circuit 105 indicates that frequency detection is performed. Demodulation circuit 105
Is composed of D flip-flop flops as shown in FIG. When the clock input CL of the D flip-flop is a signal I and the data input D is a signal Q, when data is counted at the rising edge of the clock, the output becomes L and the phases of I and Q change by 90 degrees. Output L
Similarly, it can be seen that the data is demodulated by changing.
The demodulated signal thus demodulated passes through a low-pass filter 106 for removing noise, and is supplied to the comparator circuit 1
07 and is output as a binary digital signal.

The binary digital signal is synchronized in bit synchronization and frame synchronization by a synchronization circuit 114. Synchronous circuit 11
An intermittent operation signal BS for performing an intermittent operation of the entire receiver is output to the control circuit 113 in accordance with the synchronization signal output from the control circuit 113.

Next, the operation of the PLL local oscillation circuit 109 will be described with reference to FIG. FIG. 4 is a diagram showing the PLL local oscillation circuit 109.

The phase difference between the output signal of the variable frequency divider 20 for dividing the oscillation frequency of the voltage controlled oscillation circuit 111 and the output signal of the reference frequency divider 23 for dividing the oscillation frequency of the reference oscillator 21 is calculated by the phase comparator 22. And passes the error signal through a loop filter 112 to obtain an error voltage. The voltage controlled oscillation circuit 111 controls the oscillation frequency by using the error voltage as a control voltage, and the PLL local oscillation circuit 109 is always fed back so that the error signal is constant.
Further, the variable frequency divider 20 can change the frequency division ratio by the frequency designation signal given from the PLL control circuit 24, so that the oscillation frequency of the voltage controlled oscillation circuit 111 corresponding to the frequency designation signal can be obtained.

Next, the PLL control circuit 24 sets a frequency designation RO.
The frequency designation signal is read from M25. Here, if the oscillation frequency of the reference oscillator 21 is 10 kHz and the number of bits of the frequency designation signal is 14 bits, the maximum setting frequency is 32
7.67 MHz.

Next, the frequency detection circuit 110 will be described with reference to FIGS. FIG. 5 is a block diagram of the frequency detection circuit 110. FIG. 6 is a diagram showing a signal state of each unit of the frequency detection circuit 110.

The basic operation of this circuit is to detect the offset frequency with respect to the line frequency by frequency-detecting the output signal I or Q of the limiter circuit 104, and to stop the operation when the offset frequency exceeds a certain value. The local oscillation circuit 109 is activated to make the PLL local oscillation frequency follow the line frequency.

FIG. 6 shows the waveform of each part. The signal Q is an output of the limiter circuit 104, and is assumed to have an offset frequency ΔF. That is, the frequency of the signal Q is ± FD-ΔF with respect to the modulation frequency FD. The output of the demodulation circuit 10 is a pulse width T indicated by D.
Pulse wave. By integrating D with the low-pass filter 11, a voltage output O proportional to the frequency of the signal Q is obtained. The average value of O is the voltage output of FD, which is independent of ΔF. Because the frequency of the signal Q is FD−ΔF and |
−FD−ΔF |, the frequency average value is FD. The average value A of the signal O is obtained by the average value circuit 12. The time constant is set long enough.

Next, the average value A is input to the offset circuit 13 to obtain a voltage of ± ΔV.

VH = A + .DELTA.V, VL = A-.DELTA.V O, VH, O, V
L is input, and O and VH become high when O <VH.
In this embodiment, VL is set to be high when O <VL. O, VL, O, and VH are input to the NAND circuit 16, and the output FL of the NAND circuit 16 becomes low only when all of O, VL, O, and VH are high. This indicates that the FL signal is low when the signal O is within ΔV from the average value A. The above is shown with specific numerical values.

KD for determining the demodulation sensitivity in the demodulation circuit 10
(V / kHz), the signal O becomes O = KD · ΔF, and the FL signal becomes low when ΔV> KD · ΔF. KD = 10mV / kH
If z and ΔV = 10 mV, the FL signal becomes high when ΔF> 1 kHz.

Next, the intermittent operation of the PLL will be described with reference to FIG. FIG. 7 is a time chart showing the PLL intermittent operation. Generally, the pull-in time of the PLL tends to be shorter as the frequency error of the voltage-controlled oscillation circuit 111 in the free-run state is smaller. It is assumed that the system belongs to three groups in the case of a synchronous system as shown in FIG. In the conventional timing, the PLL for activating the PLL local oscillation circuit 109 as shown by a dotted line in consideration of the margin of the PLL pull-in time.
LBS signal, VC that activates voltage controlled oscillator circuit 111
The OBS signal rises T2 seconds earlier than the data capture timing and falls at the same time as the end of the group. Therefore, in the apparatus of the present invention, when synchronization is established, the PLLBS signal and the VCOBS signal are started at the timing of T1 seconds by using the fact that the frequency error of the voltage controlled oscillation circuit 111 is small and the pull-in time is short. Next, the PLLBS signal is turned off at the data fetch timing, and the voltage control oscillation circuit is made to run free. At this time, since the output of the phase comparator 22 of the PLL local oscillation circuit 109 is in a high resistance state, the control voltage of the voltage controlled oscillator 111 is held. With this control, the operating current at the time of reception is greatly reduced.

Next, a case where the control voltage is reduced due to a leak current, disturbance, or the like and the frequency of the voltage controlled oscillation circuit 111 is changed will be described with reference to FIG. FIG. 8 is a flowchart showing the PLL intermittent operation. When the frequency changes during reception, the FL signal of the frequency detection circuit 110 becomes low. The control circuit 113 sets P at the timing of the next own group.
By setting the rising timing of the LLBS signal and the VCOBS signal to be T0 seconds longer than T1 seconds, an operation for ensuring the phase pull-in of the PLL local oscillation circuit 109 is performed.

[0036]

As described above, according to the present invention,
PLL pre-operation time is shortened by carrier wave synchronization state PLL
Since the current consumption of the operation can be reduced at the time of reception without synchronization deviation, it is possible to greatly improve the battery life.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a signal state when a modulated signal is detected.

FIG. 3 illustrates a demodulation circuit.

FIG. 4 is a diagram showing a PLL local oscillation circuit.

FIG. 5 is a diagram illustrating a frequency detection circuit.

FIG. 6 is a diagram illustrating a signal state in the frequency detection circuit.

FIG. 7 is a time chart showing a PLL intermittent operation.

FIG. 8 is a flowchart showing a PLL intermittent operation.

[Explanation of symbols]

 Reference Signs List 10 demodulation circuit 11 low-pass filter 12 average value circuit 13 offset circuit 14, 15 comparator circuit 16 NAND circuit 17 sawtooth wave generation circuit 18 exclusive OR circuit 20 variable frequency divider 21 reference oscillator 22 phase comparator 23 reference frequency division Device 24 PLL control circuit 25 frequency designation ROM 101 high frequency amplifier 102 mixer circuit 103 low-pass filter 104 limiter circuit 105 demodulation circuit 106 low-pass filter 107 comparator circuit 108 90-degree phase shifter 109 PLL local oscillation circuit 110 frequency detection circuit 111 Voltage controlled oscillator circuit 112 Loop filter 113 Control circuit 114 Synchronous circuit 115 Intermittent operation circuit

Claims (2)

(57) [Claims] 1. A high-frequency amplifier for receiving and amplifying a modulated wave frequency-modulated by a binary digital signal, a PLL local oscillation circuit, and a local oscillation frequency equal to a line frequency output from the PLL local oscillation circuit. A mixer circuit for generating a baseband signal from the modulated wave, a quadrature detection demodulation circuit for performing signal processing of the baseband signal to obtain a demodulated signal, and a synchronization for outputting a synchronization signal by performing bit synchronization and frame synchronization from the demodulated signal An FSK receiver comprising: a detection circuit; and an intermittent reception circuit that stops reception at a timing of a signal other than the own group according to a battery saving rule. A frequency difference between the line frequency and the local oscillation frequency based on the baseband signal. A frequency detection circuit that detects a signal and outputs a detection signal when a preset value is exceeded, And a control circuit using the detection signal and outputs a control signal for controlling the operation of the PLL local oscillator circuit, the control circuit, when no detection signal from said frequency detection circuit, the self then receives Prior to the timing of the group signals, the PL
Delay the timing of starting the operation of the L local oscillation circuit
FSK characterized by comprising means for controlling
Receiving machine. 2. The frequency detection circuit includes: a unit that outputs a frequency detection signal of the baseband signal; a unit that outputs an average voltage of the frequency detection signal; and a unit that superimposes an offset voltage on the average voltage. And means for comparing the frequency detection signal with an output from the superimposing means and outputting the detection signal.
The FSK receiver as described.