JP3696636B2 - Receiver - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a receiving apparatus suitable for application to, for example, a portable radio telephone apparatus.
[0002]
[Prior art]
Conventionally, a radiotelephone device has been configured as shown in FIG. 4, for example. In FIG. 4, reference numeral 10 denotes a transmission circuit. The transmission circuit 10 supplies the baseband transmission data obtained at the terminal 11 to the transmission processing circuit 12, and the transmission processing circuit 12 performs transmission processing such as addition of synchronization data. The processed transmission data is supplied to the modulation circuit 13. The modulation circuit 13 modulates with a modulated wave having a predetermined frequency and supplies the modulated signal to the mixer 14. The mixer 14 mixes the frequency conversion frequency signal supplied from the PLL circuit (phase-locked loop circuit) 1 with a modulation signal for transmission to obtain a signal of a predetermined transmission frequency (transmission channel). The signal is supplied to the antenna 3 via the bandpass filter 15, the transmission amplifier 16, and the antenna switch 2, and is transmitted by radio from the antenna 3.
[0003]
Reference numeral 20 denotes a receiving circuit. The receiving circuit 20 supplies a signal received by the antenna 3 to the mixer 23 via the antenna switch 2, the band pass filter 21, and the receiving amplifier 22. In the mixer 23, the frequency conversion frequency signal supplied from the PLL circuit 1 is mixed with the reception signal, and the reception signal modulated to the transmission frequency (transmission channel) is converted into an intermediate frequency signal. Then, this intermediate frequency signal is supplied to the demodulation circuit 25 via the intermediate frequency circuit 24, and the demodulation circuit 25 performs demodulation to the baseband signal. Then, this baseband signal is supplied to the reception processing circuit 26, and reception processing such as extraction of synchronization data is performed to obtain reception data at the terminal 27.
[0004]
In the case of this circuit, it is a transmission / reception circuit applied to a so-called TDMA (time division multiple access) communication system that performs transmission and reception in a time division manner with the same transmission frequency and reception frequency. .
[0005]
[Problems to be solved by the invention]
Incidentally, thus configured transceiver circuit, a clock and its harmonics to process the baseband signal and a baseband signal obtained by receiving for transmission, against the transmission processing system and the receiving processing system that handles high-frequency signals May cause interference . For this reason, a strict shield is applied to the circuit that processes the baseband signal so that the interference wave does not reach other circuits.
[0006]
On the other hand, a radiotelephone device needs to be configured in a small size for portable use. However, if a strict shield is applied to a baseband signal processing system, the configuration of the device becomes so complicated that it prevents miniaturization and weight reduction. It was a factor. In addition, the clock frequency for processing the baseband signal is also demanding a sophisticated and complex audio codec, so the clock frequency is increasing. However, when the clock frequency increases in this way, the amount of interference wave The radiation level increases, requiring more stringent shielding.
[0007]
In view of the above, an object of the present invention is to provide a receiving apparatus that can perform a good reception process with a simple configuration without being affected by an interference wave such as a baseband signal.
[0008]
[Means for Solving the Problems]
The present invention includes a demodulating means for obtaining a demodulated signal by mixing a demodulated frequency signal with a received signal, a detecting means for detecting a synchronization signal included in the signal demodulated by the demodulating means, and a clock generating means for processing the demodulated signal. A PLL circuit that generates a demodulation frequency signal, and supplies a clock output from the clock generation means to the PLL circuit to generate a demodulation frequency signal, and the frequency division ratio in the PLL circuit is changed to a change in the clock frequency. The demodulating frequency signal is kept at a substantially constant frequency by changing the interlocking change .
[0010]
[Action]
According to the present invention, when a clock for processing a baseband signal or a baseband signal obtained by reception and its harmonics interfere with demodulation of the received signal, a synchronization signal included in the demodulated signal is detected. Although it becomes impossible, the synchronization signal can be detected by changing the frequency of the clock slightly so as not to cause interference, and reception processing can be satisfactorily performed without the influence of the interference wave.
[0011]
In this case, when the demodulation frequency signal is created from this clock by slightly changing the clock frequency, the frequency of this demodulation frequency signal also fluctuates, but the frequency division ratio in the PLL circuit is changed. By changing in conjunction with the frequency change, the demodulation frequency signal can be maintained at a constant frequency even if the clock frequency is changed in order to eliminate the influence of the interference wave.
[0012]
【Example】
An embodiment of the present invention will be described below with reference to FIGS.
[0013]
In this example, the present invention is applied to a demodulating circuit of a receiving system of a radiotelephone apparatus, and is configured as shown in FIG. In FIG. 1, reference numeral 31 denotes a terminal from which a reception signal obtained by converting the frequency from the transmission channel to obtain an intermediate frequency signal is obtained, and the reception signal obtained at this terminal 31 is supplied to the mixer 32. The mixer 32 mixes the demodulation frequency signal supplied from the PLL circuit (phase-locked loop circuit) 38 with the received signal, and performs demodulation processing to demodulate the baseband signal.
[0014]
Then, the baseband signal output from the mixer 32 is supplied to the data reproduction circuit 33 and the synchronization detection circuit 34. The synchronization detection circuit 34 is a circuit that detects a synchronization signal of a predetermined pattern included in the baseband signal obtained by reception. When the synchronization signal is detected by the detection circuit 34, the data of the detection timing is used as a data reproduction circuit. 33. Then, the data reproduction circuit 33 performs a process of reproducing the transmission data included in the baseband signal with reference to the detection timing of the synchronization signal, and the reproduced data is transmitted from the reception data output terminal 35 to the subsequent data processing circuit. (Not shown).
[0015]
When the synchronization detection circuit 34 can detect the synchronization signal, data indicating the detection is transmitted to a central control unit (CPU) 36 that controls the reception operation of the reception system.
[0016]
In the figure, reference numeral 37 denotes an oscillation circuit. The oscillation circuit 37 is a circuit that outputs an oscillation signal having a predetermined frequency based on the control of the central control unit 36. The telephone device uses the created oscillation signal as a transmission / reception processing clock. To each circuit in the circuit.
[0017]
Here, an example of the circuit configuration of the oscillation circuit 37 is shown in FIG. 2. In this example, the oscillation circuit 37 is composed of an oscillation circuit called a CMOS oscillation circuit, and capacitors C 1, C 2, etc. are connected to both ends of the crystal resonator 39. The oscillation signal is taken out by being connected, and this capacitor C1 is a variable capacitance diode. Then, a control signal having a predetermined potential is supplied from the central controller 36 side via the switch SW1 and the resistor R1 between the variable capacitance diode C1 and the crystal resonator 39, and a power source having a predetermined voltage is connected to the resistor R2. And supplied between the variable capacitance diode C1 and the crystal resonator 39.
[0018]
By configuring the oscillation circuit 37 in this way, when the switch SW1 is turned off and no control signal is supplied from the central controller 36 side, and when the switch SW2 is turned on and a control signal having a predetermined potential is supplied. The frequency of the extracted oscillation signal is slightly different. For example, when an oscillation signal of several tens to several hundreds of MHz is extracted from the oscillation circuit 37, the frequency is changed by about 50 kHz by turning on / off the switch SW1.
[0019]
The oscillation signal output from the oscillation circuit 37 is supplied to each circuit as a clock. Here, the reference signal of the phase loop is supplied to the PLL circuit 36 that forms the demodulation frequency signal. The frequency dividing ratio of a frequency divider (not shown) in the PLL circuit 38 is determined by control data supplied from the central controller 36. Then, a demodulation frequency signal is formed by the PLL circuit 36, this demodulation frequency signal is supplied to the mixing circuit 32, mixed with an intermediate frequency signal which is a reception signal, and demodulated into a baseband signal.
[0020]
In this case, in this example, when the frequency of the oscillation signal output from the oscillation circuit 37 is changed by the control of the switch SW1 in the oscillation circuit 37, the frequency is divided by the control data supplied from the central controller 36 to the PLL circuit 38. The ratio is slightly changed to keep the frequency of the demodulation frequency signal formed by the PLL circuit 36 substantially constant.
[0021]
Next, processing when reception is performed by the demodulation circuit of this example will be described with reference to the flowchart of FIG. First, in the demodulation circuit of this example, the synchronization detection circuit 34 performs synchronization signal detection processing of the baseband signal obtained by demodulation (step 101). At this time, the switch SW1 in the oscillation circuit 37 is turned off. Then, the synchronization detection process in the synchronization detection circuit 34 is started, and at the same time, the timer circuit in the central controller 36 is activated (step 102).
[0022]
In this state, it is determined whether or not the synchronization detection circuit 34 has detected a synchronization signal of a predetermined pattern (step 103). Here, when the synchronization signal can be detected, it is determined that the clock output from the oscillation circuit 37 has been correctly received without interfering with the receiving process, and the receiving state is maintained as it is (step 104). .
[0023]
If the synchronization signal cannot be detected in step 103, it is determined whether or not a predetermined time (for example, several seconds) has elapsed since the timer was started in step 102 (step 105). Until the predetermined time elapses, it is repeatedly determined whether or not the synchronization signal has been detected in step 103. When it is determined in step 105 that the predetermined time has elapsed, the switch SW1 is turned on, the control signal is supplied from the central controller 36 to the oscillation circuit 37, and the frequency of the oscillation signal (clock) output from the oscillation circuit 37 is reached. Is slightly changed (step 106). Then, with the frequency of the oscillation signal changed, the process returns to step 103 to determine whether or not the synchronization signal has been detected.
[0024]
Here, by changing the frequency of the oscillation signal, when the disturbance that the oscillation signal has given to the reception processing is avoided, the synchronization signal can be detected, and the process proceeds to step 104 and remains as it is. The reception state is maintained.
[0025]
As described above, according to the receiving circuit of this example, when the clock used for the reception signal processing or its harmonics interferes with the reception processing, the frequency of the clock slightly changes, and the influence of the interference wave is reduced. It works to avoid it so that it can receive well. Therefore, it is possible to avoid the influence of interference waves without strictly shielding the periphery of a circuit that requires a clock required for reception processing (particularly baseband signal processing). ) Can be simplified that much.
[0026]
If the frequency of the clock is changed to remove the influence of the interference wave, the processing state slightly changes when performing baseband signal processing. For example, for a clock of several tens to several hundreds of MHz A slight frequency change of about 50 KHz is in an allowable range as an error in each circuit, and does not adversely affect the processing state.
[0027]
However, in the PLL circuit 38, the demodulation frequency is obtained with reference to the clock. If the clock frequency varies, the demodulation frequency may vary accordingly, and accurate demodulation may not be possible. In this case, the frequency division ratio of the frequency divider in the PLL circuit is changed in conjunction with the fluctuation of the clock frequency so that the demodulation frequency signal has a substantially constant frequency. Even if it is made to receive, a receiving process can be performed correctly.
[0028]
In the above-described embodiment, the frequency division ratio of the PLL circuit that generates the demodulation frequency signal in the demodulation circuit that demodulates the intermediate frequency signal obtained by reception into the baseband signal is changed according to the clock frequency. However, the frequency division ratio of a PLL circuit (corresponding to the PLL circuit 1 in FIG. 4) that generates a demodulation frequency signal for selecting a reception frequency (reception channel) is changed according to the clock frequency, so that the reception channel is substantially constant. A frequency signal for selection may be generated.
[0029]
Also, in circuits other than these demodulation circuits, if the clock frequency fluctuation is not preferable (for example, a circuit that performs processing at the time obtained by counting the clock), a clock corrected by a PLL circuit or the like is supplied. You should do it.
[0030]
In the above-described embodiment, the present invention is applied to the receiving circuit of the radio telephone apparatus.
[0031]
【The invention's effect】
According to the present invention, when a clock for processing a demodulated signal such as a baseband signal interferes with demodulation of a received signal, processing is performed to change the frequency of the clock to a frequency that does not cause interference. Thus, the synchronization signal can be detected, and the reception process can be satisfactorily performed without the influence of the interference wave.
[0032]
In this case, when a demodulation frequency signal is created from this clock, the frequency of this demodulation frequency signal also varies by slightly changing the frequency of the clock, but the frequency division ratio in the PLL circuit is changed to the clock frequency. By changing the frequency in conjunction with the frequency change, the frequency signal for demodulation can be kept at a constant frequency even if the clock frequency is changed to eliminate the influence of the interference wave, and the reception frequency etc. can be kept constant accurately. Can be kept in a state.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an embodiment of the present invention.
FIG. 2 is a configuration diagram illustrating a configuration example of an oscillation circuit according to an embodiment;
FIG. 3 is a flowchart illustrating synchronization detection processing according to an embodiment.
FIG. 4 is a block diagram showing an example of a circuit configuration of a radiotelephone device.
[Explanation of symbols]
32 Mixer 34 Synchronization detection circuit 36 Central control unit (CPU)
37 Oscillator 38 PLL circuit (phase locked loop circuit)

Claims (1)

Demodulation means for obtaining a demodulated signal by mixing a demodulated frequency signal with the received signal;
A means for detecting a synchronization signal included in the signal demodulated by the demodulation means;
A PLL circuit for generating the demodulation frequency signal from a clock generation means for processing the demodulation signal;
Supplying a clock output from the clock generation means to the PLL circuit to generate the demodulation frequency signal;
The receiving apparatus characterized in that the frequency signal for demodulation is maintained at a substantially constant frequency by changing a frequency dividing ratio in the PLL circuit in conjunction with a change in the frequency of the clock. .

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