JP2967974B2 - Circuit pattern formation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure for a semiconductor manufacturing apparatus.
Equipment, especially on a board in a step-and-repeat fashion.
Method of forming a circuit pattern suitable for an apparatus that exposes a cut area
Method, especially with masks and reticles that serve as masters for exposure.
Regarding alignment with the semiconductor wafer etc. to be exposed
You. [0002] 2. Description of the Related Art In recent years, semiconductor devices such as ICs and LSIs have been rapidly increasing.
The miniaturization and high-density are rapidly progressing.
The mask or reticle circuit pattern onto a semiconductor wafer
Exposure equipment that transfers images by overlaying them on the formed circuit pattern
More and more high-precision devices are required. trout
Circuit pattern on the wafer and the circuit pattern on the wafer
It is required to overlap with an accuracy within 0.1 μm,
For this reason, at present, this type of exposure equipment is
To a local area (for example, one chip) on the wafer.
Then, step the wafer by a certain distance
Repeatedly exposing the circuit pattern of the mask
So-called step-and-repeat type device, especially reduction
Projection type exposure apparatuses (steppers) have become mainstream.
In this step and repeat method, the wafer is two-dimensionally
Place it on a moving stage and project the mask circuit pattern.
To position with respect to the image, the projected image and the wafer
Can be precisely overlapped with each chip. Ma
In the case of a reduction type exposure apparatus, a mask or reticle
Alignment mark and chip on wafer
And directly observe or detect the mark through the projection lens.
Through-the-lens alignment method
Method and the position provided at a certain distance from the projection lens.
Alignment of the entire wafer using a microscope for alignment
After that, the wafer is sent directly beneath the projection lens.
There are two methods, an alignment method of the cis system. [0003] SUMMARY OF THE INVENTION Generally, a through-the-lens
Is the method to align each chip on the wafer?
Therefore, although the overlay accuracy is high, the exposure of one wafer
There is a problem that the light processing time becomes long. Male Axis
In the case of the method, the alignment of the whole wafer is completed once
Step the wafer according to the chip arrangement
, The exposure processing time is reduced. But
Since the alignment of each chip is not performed,
Expansion and contraction, wafer rotation error on the stage,
Satisfactory overlay accuracy due to influence of orthogonality of movement
Was not obtained. On the other hand, through-the-lens alignment
As an alignment method using a projection exposure apparatus having a system,
For example, Japanese Patent Application Laid-Open No.
Some typical chip areas among multiple chip areas
Alignment with the mask in advance,
Results (detection of marks provided in the chip area)
Of the chip area arrangement on the wafer based on the
Direction) and then step-and-repeat wafer
A positioning method for moving the position has also been proposed. This one
Method, align each chip on the wafer during exposure.
Processing time for one wafer
Is not so long. [0005] According to the present invention, a plurality of chips formed on a substrate are provided.
For all of the shots (shot areas), the mask pattern
Step and step without alignment with projection position
The circuit pattern can be accurately formed by the repeat method.
The purpose is to provide a method that can be used. [0007] [MEANS FOR SOLVING THE PROBLEMS] To achieve this object
In addition, the present invention provides a method for forming a circuit element on a substrate (WA).
Duplicates formed in a regular array in advance according to the design position information
Number of shot areas (Cn), and
Relative alignment with the circuit pattern image
The circuit pattern image is sequentially transferred to each of the shot areas.
For forming a circuit pattern in a shot area by using
Applied to In the present invention, a plurality of shots on a substrate are provided.
N or more n shots that are not adjacent to each other
Set the alignment area as the alignment shot area,
Are associated with each of the n alignment shot regions.
By sequentially detecting the position information of the alignment mark,
Of each of the n alignment shot regions.
Determining the position measurement information Hn;
Arrangement characteristics of shot area are residual rotation error, orthogonality error,
Defined by an error parameter matrix A containing each component of the expansion error
, Each element in the error parameter matrix A
Design the elementary value of each of the n alignment shot areas
Approximate calculation using position information Dn and measured position information Hn
And calculating the value according to the logic. Further, in the present invention, the calculated error parameter
Based on the value of each element of the data matrix A
Relative alignment of each of the
To the correction position based on the design position information Dn.
Calculated at the corrected alignment position.
The step of performing the joining exposure is performed. [0010] According to the present invention, it is formed on a substrate such as a wafer.
Representative of multiple chip (shot) areas
Alignment associated with each of the n alignment shot areas
The position information of the alignment mark is detected and the n
When the measured position information of each of the
In both cases, the arrangement characteristics of the multiple shot areas on the substrate (remaining
(Including rotation error, orthogonality error, and expansion / contraction error)
The difference parameter A is set for each of the n alignment shot areas.
It is calculated using the design position information and the measured position information.
Multiple shot areas on the board based on the
Relative alignment of each circuit area with the circuit pattern image
Position, so that all the chips formed on the substrate
The positioning error is small on average for the
Circuit pattern on each shot area on the board.
Can be achieved. [0011] FIG. 1 shows a preferred embodiment for implementing the method of the present invention.
FIG. 2 is a perspective view illustrating a schematic configuration of a small projection type exposure apparatus.
The reticle R serving as a projection master has a projection center whose projection center is
Is positioned so that it passes through the optical axis of
It is. The projection lens 1 is a circuit pattern drawn on the reticle R.
Image is reduced to 1/5 or 1/10, and
Projected onto Wafer holder 2 vacuum sucks wafer WA
Stage that moves two-dimensionally in the x and y directions
3 is provided so as to be able to rotate minutely. Drive motor
4 is fixed on the stage 3 and rotates the wafer holder 2
Let it. The movement of the stage 3 in the x direction is
The movement in the y direction is performed by driving the motor 6.
This is done. Reflection on the two orthogonal sides of stage 3
The reflecting mirror 7 has a plane extending in the y direction, and the reflecting plane has an x direction.
The reflection mirrors 8 extending in the directions are fixedly provided. Leh
The lightwave interferometer (hereinafter simply referred to as laser interferometer) 9
The laser beam is projected on the reflection mirror 8 and the
Direction (or the amount of movement), the laser interferometer 10
The laser beam is projected on the reflection mirror 7 and the x direction of the stage 3 is projected.
Direction (or the amount of movement) is detected. The side of the projection lens 1
Detects alignment marks on wafer WA
(Or to observe)
Lighting microscopes (hereinafter referred to as WAMs) 20, 21
Is provided. The WAM 21 is a projection lens in FIG.
After 1 and not shown. WAM 20, 21
Each has an optical axis parallel to the optical axis AX of the projection lens 1,
a belt-like laser spot light YSP elongated in the x direction,
θSP is imaged on the wafer WA. (Spot light YS
P and θSP are not shown in FIG. ) These spot lights Y
SP and θSP are photosensitizers (photoresist
G) is light of a wavelength that does not expose
It vibrates in the y-direction with a large amplitude. And WAM 20, 2
1 is a photoelectric element that receives scattered light and diffracted light from the mark
Rectifies the photoelectric signal synchronously with the spot light oscillation cycle.
And the y-direction of the spot light θSP (YSP)
Corresponding to the amount of deviation of the mark from the vibration center in the y direction.
Output the alignment signal. Therefore, WAM 20, 21
The same configuration as the so-called spot light vibration scanning type photoelectric microscope
Things. By the way, the present apparatus is provided with a projection lens 1 through a projection lens 1.
Laser step alignment for detecting marks on wafers
(Hereinafter referred to as LSA) optical system. Unfortunate
An expander (not shown) generated from the laser light source shown
Laser beam L that has passed through a cylindrical lens, etc.
B is light of a wavelength that does not expose the photoresist,
The light enters the splitter 30 and is split into two light beams. So
One of the laser beams is reflected by the mirror 31 and
After passing through the pretter 32, the image forming lens group 33 crosses
After converging so that the surface becomes a strip-shaped spot light,
Projection optical path of a circuit pattern between the lens R and the projection lens 1
First folding mirror 34 arranged so as not to block light
Incident on. The first folding mirror 34 reflects the laser beam.
The light is reflected upward toward the tickle R. The laser beam is retic
Provided below the reticle R and parallel to the surface of the reticle R.
The light enters the mirror 35 having a reflection plane, and the projection lens 1
Is reflected toward the center of the entrance pupil of. From mirror 35
The laser beam is converged by the projection lens 1 and the wafer W
A strip-shaped spot light LYS elongated in the x direction on A
The image is formed. The spot light LYS is x on the wafer WA.
Runs the diffraction grating mark extending in the y direction relatively in the y direction.
To determine the position of the mark.
When the spot light LYS irradiates the mark, it turns from the mark.
Light folding occurs. The optical information is again stored in the projection lens 1, Mira
-35, mirror 34, imaging lens group 33, and beams
Returning to the splitter 32, the beam is reflected by the beam splitter 32.
Optical element 3 consisting of a condenser lens and a spatial filter
6 is incident. This optical element 36 is the diffracted light from the mark
(First-order diffracted light or second-order diffracted light), and specularly reflected light (0
Next diffracted light), and the diffracted light is
To focus the light on the light receiving surface of the photoelectric element 38. The photoelectric element 38 is a collection
A photoelectric signal corresponding to the amount of the emitted diffracted light is output. Less than
Top, mirror 31, beam splitter 32, imaging lens group
33, mirrors 34 and 35, optical element 36, mirror 37,
And the photoelectric element 38 is provided in the y direction of the mark on the wafer WA.
Through-the-lens type alignment optics to detect position
(Hereinafter referred to as Y-LSA system). On the other hand, the beam splitter 30
Another laser beam is emitted from the mark on the wafer WA in the x direction.
Through-the-lens type alignment optics to detect position
System (hereinafter referred to as X-LSA system). X-LSA
The mirror 41 and beam beam system are exactly the same as the Y-LSA system.
Pretitter 42, imaging lens group 43, mirrors 44, 4
5, from the optical element 46, the mirror 47, and the photoelectric element 48
And a belt-like shape elongated in the y-direction on the wafer WA.
An image of the spot light LXS is formed. The main control unit 50 receives signals from the photoelectric elements 38 and 48.
Photoelectric signal, alignment signal from WAM20, 21
And the position information from the laser interferometers 9 and 10
And perform various arithmetic processing for alignment.
Command to drive the motors 4, 5, 6
You. The main controller 50 is a microcomputer or mini
An arithmetic processing unit such as a computer is provided.
A plurality of chips CP formed on the wafer WA are
Total position information (chip array coordinate values on wafer WA, etc.) is recorded.
Remembered. FIG. 2 shows the WAMs 20, 21 and Y-LSA.
, SP-YSP, L-SPA
Image plane of projection lens 1 of YS, LXS (table of wafer WA)
FIG. 7 is a plan view showing an arrangement relationship in the same plane). FIG.
Defines a coordinate system xy with the optical axis AX as the origin.
And the x-axis and the y-axis respectively indicate the moving directions of the stage 3.
You. In FIG. 2, a circular area centered on the optical axis AX is an image.
And the inner rectangular area is a retic
It is a projection image Pr of the effective pattern area of the vehicle R. Spot
The light LYS of the projection image Pr in the image field if
Formed at an outer position and coincident on the x-axis,
Spot light LXS is also projected image in image field if
Formed outside of Pr and on y-axis
Is done. On the other hand, vibration of two spot lights θSP and YSP
Center is distance Y in x direction from x axis₀Line segment (x-axis
So as to match on LL and between its x-directions
So that the distance Dx is smaller than the diameter of the wafer WA.
Stipulated. In this device, the spot light θSP, YS
P is symmetrically arranged with respect to the y-axis,
The device 50 is a spot light θSP with respect to the projection point of the optical axis AX,
Information on the position of the YSP is stored. In addition,
The control device 50 controls the spot light L for the projection point of the optical axis AX.
YS x-direction center position (distance Xl) and spot light LX
Information about the center position (distance Yl) of S in the y direction is also stored.
doing. Next, the position according to the present invention using this device is described.
The flowchart of FIG.
This will be described with reference to the drawings. Note that this alignment is performed for the wafer WA.
Of the second and subsequent layers of the wafer W
Chip and alignment mark already formed on A
Have been. First, the wafer WA is unillustrated in Step 100.
Using the pre-alignment device shown, a straight line
Rough so that the notch (flat) faces in a certain direction
Positioned. The flat of the wafer WA is shown in FIG.
Thus, it is positioned so as to be parallel to the x-axis. Next, at step 101, the wafer WA is
Is transferred onto the wafer holder 2 of the page 3 and the flat is x
Placed on the wafer holder 2 so as to keep it parallel to the axis,
Vacuum adsorbed. FIG. 4 shows the wafer WA, for example.
So that a plurality of chips Cn are orthogonally arranged on the wafer WA.
It is formed in a matrix along the coordinates αβ. Arrangement
The α axis of the column coordinates αβ is almost parallel to the flat of the wafer WA.
is there. In FIG. 4, among the plurality of chips Cn, the arrangement is representative.
In a line on the α axis passing through the center of the wafer WA at the coordinates αβ
Lined chips C₀~ C₆Only is shown. Each chip C
₀~ C₆Has four alignment marks G each
Y, Gθ, SX, and SY are provided in association therewith. Now, chip C₀~ C₆Center chip C_Three
Is the origin of the array coordinates αβ, α
Grating SY extending linearly in the direction₀~ SY₆
But each chip C₀~ C₆It is provided on the right side of. Ma
The chip C_ThreeLinearly in the β direction on the β axis passing through the center of
Extended diffraction grating mark SX_ThreeIs chip C_ThreeBelow
Provided and another chip C₀, C₁, C_Two, C_Four, C_Five,
C₆Also goes through the center of the chip and is parallel to the β axis.
Mark SX on line segment₀~ SX_Two, SX_Four~ SX ₆Provided
Have been. These marks SY_n, SX_nAre each
Detected by the pot light LYS, LXS
You. Each chip C₀~ C₆Under the wafer
WA alignment (global alignment)
Mark GY used to do₀~ GY₆, Gθ₀~ G
θ₆Is provided. These marks GY_n, Gθ_nIs
On a diffraction grating linearly extending in the α direction on a line parallel to the α axis
The pattern is formed as follows. Furthermore, line up in the α direction
D Chip C₀~ C₆Among them, for example, the chip C at the left end₀
Mark GY₀And the rightmost tip C₆Mark Gθ₆With
The interval in the α direction is the spot light θ by the WAMs 20 and 21.
It is determined to match the distance DX between SP and YSP.
You. In other words, in this embodiment, two
GY₀And mark Gθ₆Off-axis using
Perform global alignment of wafer HA. Because of this
Other mark GY₁~ GY₆, Mark Gθ₀~ Gθ_FiveIs
It is essentially unnecessary and may not be necessary. In short, the α axis of the wafer WA
Elongate in the α direction on a line parallel to (or coincident with)
It is sufficient that the two marks are present at a distance DX. Now, main controller 50 performs pre-alignment.
Position of stage 3 when wafer WA is received from equipment
From the position, mark GY₀, Gθ₆Is W
AM21, 20 until it is located within the detection (observation) field of view
The information such as the direction and amount of movement of the stage 3 is determined by the device
It is stored in advance as a number. Therefore, the next step 102
, The main controller 50 first drives the motors 5 and 6
And mark GY₀Is located within the detection field of view of WAM21
So that the stage 3 is positioned. After that,
The center of vibration of light YSP is marked GY₀With the center in the y direction
Main controller 50 receives the address from WAM 21 so that they match.
Based on the alignment signal and the position information from the laser interferometer 9.
Then, the stage 3 is precisely positioned in the y direction. Sports
Center of vibration of light YSP and mark GY₀Coincides with the center of
Then, the main control device 50
Servo motor 6 with alignment signal from WAM 21
(Feedback) Mark Gθ while controlling₆Is WA
M20 so that it is detected by the spot light θSP of M20.
The data holder 4 is driven to rotate the wafer holder 2. Further
The main controller 50 determines the oscillation center of the spot light θSP and the marker.
Ku Gθ₆WAM2 so that the center of the
Servo control the motor 4 with the alignment signal from 0
You. By the above series of operations, the spot light YS
P and mark GY₀Coincides with the spot light θSP and marks
Gθ₆Coincide with each other, and the moving coordinate system of the stage 3, that is,
Rotational deviation of array coordinates αβ of wafer WA with respect to reference system xy
Is corrected, and y of the coordinate system xy and the array coordinates αβ
The association (regulation) regarding the position in the direction (β direction) is completed.
I do. Next, a chip located at the center of the wafer WA
Top C_ThreeMark SX_ThreeIs an X-LSA spot light L
Position stage 3 to be scanned by XS
Then, it is moved in the x direction. At this time, the main controller 50
Time-series photoelectric signal from photoelectric element 48 and laser interferometer
SX based on the position information from_ThreeIs sport
Position of the wafer WA in the x-direction when the position coincides with the cut light LXS.
Location is detected and stored. With this, the coordinate system xy and the
Correlation of column coordinates αβ with respect to position in x direction (α direction)
Is completed. Incidentally, the correspondence in the x direction is determined by the exposure operation.
This is unnecessary when the X-LSA system is used immediately before. By the above operation, the off-axis system arc
Global alignment of wafer WA mainly for liment
(The mapping of the array coordinates αβ to the coordinate system xy) is completed.
I do. In the case of the conventional method, each chip on the wafer WA is used.
Array design value (center of chip at array coordinates αβ
Based on the standard value, main controller 50 controls laser interferometer 9,
10 is read and the projected image P of the reticle R is read.
r so that r overlaps the chip
Positioning (addressing) by repeat method
After that, the chip is exposed (printed). However, the completion of global alignment
By the time, the accuracy of the alignment detection system and the setting of each spot light
Constant accuracy or optical and shape of each mark on wafer WA
Of position detection accuracy due to physical condition (effect of process)
Errors may occur due to fluctuations, etc.
Precise positioning (addressing) according to the reference system xy
Not always. Therefore, in the embodiment of the present invention,
The error (hereinafter referred to as shot address error) is
It is assumed to have arisen from four factors. (1) Rotation of wafer; this is, for example, wafer
When correcting the rotation of WA, there are two
Positional relationship between spot light YSP and θSP is not accurate
Array coordinates for the coordinate system xy
It is represented by the remaining rotation error amount θ of the target αβ. (2) the orthogonality of the coordinate system xy; this is the motor of stage 3
That the feed directions by 5 and 6 are not exactly orthogonal
And is represented by an orthogonality error amount w. (3) The x (α) direction and the y (β) direction of the wafer
Linear expansion and contraction; this depends on the processing process of the wafer WA.
The wafer WA may expand and contract as a whole. others
The actual chip relative to the array coordinates in the chip design.
The position will be shifted by a small amount in the α and β directions, especially
It becomes remarkable in the peripheral portion of the wafer WA. The extension of this whole wafer
The amount of reduction is in the α (x) direction and β (y) direction, respectively.
It is represented by Rx and Ry. However, Rx is on the wafer WA
The measured value of the distance between two points in the x direction (α direction) and the design value
The ratio, Ry, is between two points in the y direction (β direction) on the wafer WA.
It shall be expressed as the ratio between the measured value of the distance and the design value. Therefore,
When both Rx and Ry are 1, there is no expansion or contraction. (4) Off in x (α) direction and y (β) direction
Set; this is the alignment accuracy of the wafer holder
The wafer WA as a whole due to the positioning accuracy of the
It is caused by a slight shift in the x and y directions.
The offset amounts are represented by Ox and Oy. Now, FIG.
C The remaining rotation error θ of the WA and the orthogonality error of the stage 3
The quantity w is exaggerated. In this case, the rectangular coordinate system xy is actually very small.
An oblique coordinate system xy 'inclined by the amount w is obtained, and the wafer WA is
Rotated by θ with respect to the rectangular coordinate system xy. Up
When the error factors described in (1) to (4) are added,Design position
InformationSystem of coordinate position (Dxn, Dyn) in design
About gut (chip)When exposing a circuit pattern image
It will be the information actually usedThe show to actually position
Set position (Fxn, Fyn),Is represented as
You. Here, n is an integer and represents a shot (chip) number. [0030] (Equation 1)Here, w is originally a very small amount, and θ is also a group.
Driven to a very small amount by global alignment
Therefore, when a first-order approximation is performed, equation (1) is expressed by equation (2).
You. [0032] (Equation 2) From this equation (2), at each shot position
The displacement (εxn, εyn) from the designed value is given by Equation (3).
It is represented by [0034] (Equation 3) Now, equation (2) is rewritten as a matrix operation equation.
Is as follows. [0036] ## EQU4 ## Fn = A.Dn + O (4) However, [0037] (Equation 5) [0038] (Equation 6) [0039] (Equation 7) [0040] (Equation 8) Therefore, the actual shot (chip) position is
The actual measured value is detected as Hn.
When issued, the position with the shot position Fn to be positioned
The displacement, that is, the address error En (= Hn-Fn)
To minimize the error parameters A (transformation matrix), O
(Offset). Therefore, the minimum
Assuming a square error, the address error E is given by the equation
It is represented by (9). [0042] (Equation 9) In order to minimize the address error E,
, The error parameters A and O are determined. However, in equation (9)
m is the actually measured chip among the plurality of chips on the wafer WA.
Represents a number. Now, when obtaining the error parameters A and O,
If the least squares method is used, the computational complexity
Error parameter O (Ox, Oy)
It must be decided in advance. Offset amount (Ox, O
y) is the global offset value of the wafer WA.
Is set at several m from the actually measured chip position Hn on the wafer WA.
Averaging the address error with respect to the total value (Dxn, Dyn)
It is good to set the value. [0044] (Equation 10) [0045] [Equation 11] Incidentally, the shot position Fn to be positioned
Component Exn in the x direction among errors En between actual and measured values Hn
Is obtained from Expressions (4) to (8). [0047] (Equation 12) [0048]           Exn = Hxn-Fxn                 = Hxn-a₁₁Dxn-a₁₂Dyn-Ox (12) And the component Eyn of the error En in the y direction is [0049] (Equation 13)           Eyn = Hyn-Fyn                 = Hyn-a_{twenty one}Dxn-a_{twenty two}Dyn-Oy (13) Becomes Therefore, an error is made to minimize the error E in equation (9).
When the difference parameter A is determined, the element a₁₁, A₁₂, A_{twenty one},
a_{twenty two}Is as follows. [0050] [Equation 14] [0051] (Equation 15) [0052] (Equation 16) [0053] [Equation 17] Element a₁₁, A₁₂, A_{twenty one}, A_{twenty two}If you find
From the equation (6), the linear expansion and contraction amounts Rx and Ry, the remaining rotation error amount
θ and the orthogonality error amount w can be obtained immediately. Rx = a₁₁                        ... (18) Ry = a_{twenty two}                        ... (19) θ = a_{twenty one}/ Ry = a_{twenty one}/ A_{twenty two}      ... (20) w =-(a_{twenty one}/ Ry)-(a₁₂/ Rx) =-(A_{twenty one}/ A_{twenty two})-(A₁₂/ A₁₁) ・ ・ ・ (21) Therefore, to determine the error parameters A and O,
After the global alignment is completed, some (4
X-LSA, Y-LSA type
Is used to measure the position of the marks SXn and SYn
(Hxn, Hyn) is obtained, and the chip is actually measured.
Using the design values (Dxn, Dyn) of
The operations of (11) and (14) to (17) may be performed. So
Now, returning to the flowchart of FIG.
I can. Main controller 50 completes global alignment
After that, the positions of the plurality of chips on the wafer WA are measured.
First, in step 103, the main controller 50 controls the X-LSA system.
The spot light LXS is the tip C at the left end in FIG.₀Attached to
Mark SX₀So that they are aligned in parallel with the
After the stage 3 is positioned, the mark SX₀Is sport
The stage 3 in the x direction so as to cross the light beam LXS
Move (scan) by an amount. During this movement, the main control unit 50
The waveform of the 48 time-series photoelectric signals is compared with the laser interferometer 10
Stored in association with the position information in the x direction,
Ra mark SX₀And the spot light LXS in the x direction
Position x at the time of matching₀Is detected. Next, the main controller 5
0 is the spot light LYS of the Y-LSA system in step 104.
Is chip C₀Mark SY attached to₀Line up parallel to
The stage 3 is positioned based on the array design value. So
After the mark SY₀Cross the spot light LYS
The stage 3 is moved by a certain amount in the y direction. At this time, the main control device 50
The time-series waveform of the photoelectric signal is converted into the y direction from the laser interferometer 9.
Stored in association with the position information of the
SY ₀And the spot light LYS coincided in the y direction.
Time position y₀Is detected. Then, main controller 50
At step 105, similar position detection is performed for m chips.
It is determined whether or not the operation has been performed.
To another chip on the wafer WA based on the array design value.
And move stage 3 from step 103 again.
The same position detection operation is repeated. In this embodiment, for example, as shown in FIG.
Along each axis of the column coordinates αβ from the center of the wafer WA
Four chips C located at equal distances₀, C₆, C₇, C₈
And center chip C_ThreeFor each of the five chips
It is assumed that the positions of steps 103 and 104 are detected.
You. Therefore, when it is determined that m = 5 in step 105,
The main controller 50 has five measured values (Hxn, Hyn)
Will be stored. That is, (Hx₁, Hy₁) = (X₀, Y₀) ・ ・ ・ Chip C₀ (Hx_Two, Hy_Two) = (X_Three, Y_Three) ・ ・ ・ Chip C_Three (Hx_Three, Hy_Three) = (X₆, Y₆) ・ ・ ・ Chip C₆ (Hx_Four, Hy_Four) = (X₇, Y₇) ・ ・ ・ Chip C₇ (Hx_Five, Hy_Five) = (X₈, Y₈) ・ ・ ・ Chip C₈ Are sequentially detected. When detecting these five actually measured values,
The actual measurement value of a certain chip is the design value (Dxn, D
yn), the difference is large, for example,
Double positioning accuracy determined by global alignment
If the values are different as described above,
Ignore, for example, mark the chip next to it
Measure the position. This is the size of the chip
If the work happens to be deformed by the machining process,
If there is dust on the mark,
Low image contrast (intensity of diffracted light)
Degradation of position measurement accuracy caused by low S / N ratio of signal
In order to compensate for this, such additional actual measurement
It is performed as a characteristic procedure. As a method for compensating for the deterioration of the accuracy of the position measurement,
Are arranged in advance in six or more chips, for example, in FIG.
In addition to the chips located in each of the four representations of the coordinates αβ
To measure the position of a total of nine chips.
Design value (Dxn, Dy) of each chip
a method of selecting five measured values in the order closest to n), or
Is simply measured values that are significantly different from the design values (Dxn, Dyn).
Do not use the value (Hxn, Hyn) for subsequent arithmetic processing
And so on. Next, main controller 50 proceeds to step 107.
Equations (10) and (11) and Equations (14) to (1)
The error parameters A and O are determined based on 7). this
In deciding, main controller 50 calculates the above five measured values.
Five design values of each detected chip are selected in advance,
The design values (Dxn, Dyn) are stored as follows.
Shall be [0061] (Dx₁, Dy₁) = (X₀', Y₀') ・ ・ ・ Chip C₀ (Dx_Two, Dy_Two) = (X_Three', Y_Three') ・ ・ ・ Chip C_Three (Dx_Three, Dy_Three) = (X₆', Y₆') ・ ・ ・ Chip C₆ (Dx_Four, Dy_Four) = (X₇', Y₇') ・ ・ ・ Chip C₇ (Dx_Five, Dy_Five) = (X₈', Y₈') ・ ・ ・ Chip C₈ Before determining the actual error parameters A and O, 5
Position measurement of one chip (so-called step alignment
3), for example, at step 106 in FIG.
Equations (10), (11), (1)
4) To execute some operations of (17) simultaneously
Can be. That is, equations (10), (11), and (14)
~ (17) Data for each chip (actual measurement values, design
Value), the arithmetic element that represents the algebraic sum of
Every time the actual measurement (step alignment) is completed
to add. The operation elements are as follows. [0062] (Equation 22) Further, among these arithmetic elements, the wafer WA
The chip to be measured above is predetermined and there is no change
In the case, the operation element including only the design value (Dxn, Dyn)
Steps 103, 104, 105, 1 in FIG.
It may be calculated before the execution of step 06. in this way
Perform some calculations in parallel with the actual measurement
The overall alignment time should not be so long
No. When the five measured values are obtained, the main controller
50 is the expression (10), (1)
After calculating the offset amount (Ox, Oy) in 1),
Using the offset value and the result of the above operation element,
(14) to (17), the element a of the array₁₁, A₁₂, A_{twenty one}, A
_{twenty two}Is calculated. By the above operation, the error parameter
Since A and O are determined, the next step of main controller 50 is performed.
In step 108, each chip of the wafer WA is
Position to be positioned with respect to the
Address (Fxn, Fy) corrected by the
n) is calculated and the design value is stored in the storage means (semiconductor memory).
Chip array corrected for (Dxn, Dyn)
Create a shot (shot address table). This array map
For example, chip C₀For position (Fx₀, F
y₀), Chip C₁For position (Fx₁, F
y₁), ..., etc., correspond to the chip number
Then, each position data is stored. Next, main controller 50 executes step 10 in FIG.
In step 9, according to the stored sequence map,
Positioning Stage 3 by Repeat Method (Address
). This allows chips and reticles on wafer WA
The projected image Pr of the circle R is accurately overlapped, and the next step
Exposure (printing) of the projected image Pr on the chip in step 110
I do. Then, in step 111, all the data on the wafer WA
If the chip exposure has not been completed, repeat step 1
Repeat step and repeat operation from 09
You. In this step 111, the exposure of all chips on the wafer WA
If it is determined that the light has ended, the next step 112 is to
Unloads EHA WA and exposes one wafer
Processing ends. As described above, it is clear from the embodiments of the present invention.
First, the chip to be step-aligned on the wafer WA
The higher the number, the higher the measurement accuracy, but the longer the measurement time
Increase. As a result, measurement time is reduced and measurement accuracy is improved.
Step-aligned tip from the top
It is desirable to select five arrangements as shown in FIG.
No. However, the circuit pattern to be overlaid
The minimum line width is not so narrow (for example, 2-5 μm)
When it is not necessary to increase the measurement accuracy, the wafer W
Three chips separated from each other on A (eg, C₀, C₆,
C₇Step alignment (chip position meter)
Measurement) is sufficient, and the measurement time is further reduced. In step alignment, each chip
Instead of detecting both the x and y positions of the
With multiple chips for step alignment
Each of the marks SXn is converted to an X-LSA-based spot light LX.
Perform relative scan (stage scan) at once with S
After detecting only the position of the chip in the x direction, the mark of each chip
Each of SYn is batched with Y-LSA spot light LYS
Scan to detect the position of each chip in the y direction
Is also good. In this way, the same row or row on the chip arrangement
Is used when there are multiple chips to be measured on the same line.
Is to detect the position in the x and y directions for each chip.
It is expected that the position measurement will be faster than that performed at the same time. The main controller 50 is a keyboard (not shown).
From the equipment, step on which chip on the wafer WA
Enter data so that alignment can be selected arbitrarily.
Force, it changes depending on the processing conditions of the wafer WA.
More flexible to the surface condition (especially mark shape)
It is possible to cope with shiburu, and the accuracy of position measurement can be improved. The offset using equations (10) and (11)
In determining the cut amount (Ox, Oy), for example,
Measurement of the position of the chip within the specified range from the center of WA
Only fruits may be used. As its specified range
Is, for example, in a circle having half the diameter of the wafer WA.
Or the size of the range is marked on the wafer WA
Exposure equipment (reduction projection type,
Accuracy of injection, proximity, etc.)
It may be arbitrarily changed according to the characteristics. In this embodiment, all the chips of the wafer WA are used.
Applying equation (4) for step-and-repeat
Type addressing, but the wafer WA
Of the surface into several areas (blocks)
A so-called block that performs optimal alignment for each block
Equation (4) is applied to the alignment in the same manner.
Can be For example, in FIG. 5, each symbol of the array coordinates αβ
4 chips currently located and 5 chips C shown
₀, C_Three, C₆, C₇, C₈About 9 chips in total
And perform step alignment to determine the position of each chip.
After detecting the measured values, the expression (1) is obtained for each quadrant of the array coordinates αβ.
0), (11), and (14) to (17)
Determine the meters A and O, and use equation (4) to determine the position.
(Fxn, Fyn) is calculated. For example, the block of the first quadrant of the array coordinates αβ
For the chip, one chip in the first quadrant and chip C
_Three, C₆, C₇Using the actual measurement values of the four chips
(4) is determined, and the blocks in the second quadrant are
One chip and chip C in the phantom₀, C_Three, C₇With 4
Equation (4) is determined using the actual measurement values of one chip. Soshi
In the case of actual exposure, the expression determined for each block
Based on shot position (Fxn, Fyn) from (4)
To align the chip on the wafer WA with the projection image Pr.
You. In this way, the non-linear requirement on the wafer
Position detection and alignment defects
In addition, unlike conventional block alignment,
Since it is possible to block while leaving the element, within each block
That the overlay accuracy of each chip is almost average for all chips
There are advantages. In addition, dew other than the stepper
Large even when mixed with optical equipment, especially mirror projection exposure equipment
Advantages can be obtained. Generally, wafers burned by a mirror projection exposure apparatus
The chip arrangement of C is often curved. There
When superposition exposure is performed on the wafer using a taper
Mix (mix and match), as above
When block alignment is performed, the
Since the curvature of the top arrangement is so small that it can be ignored,
(C) Baking with extremely high overlay accuracy is possible over the entire surface
It works. The exposure apparatus suitable for the embodiment of the present invention has been described above.
In this case, the laser spot light is marked on the wafer WA.
To detect the position of the mark (chip).
Pot light is made to vibrate on the wafer WA by simple oscillation,
Alignment system or mask on reticle R
The mark on the wafer WA above the reticle R.
Observation (detection) via the placed microscope objective lens
A so-called die-by-die alignment light that performs alignment
The same can be implemented in an exposure apparatus using a scientific system. In this case, die-by-die alignment
Occasionally the reticle R is slightly moved in the x and y directions for alignment.
If not, the projected image of the mark on the reticle R
Correspond to the spot lights LXS and LYS of this embodiment.
And The reticle R is slightly moved.
First, set the reticle R to exactly match the home position.
You. Step alignment of multiple chips (actual
Measurement), the stage is stepped according to the array design value.
After marking, mark of reticle R and chip to be measured
The reticle R is positioned so that the mark
Moves slightly in the x and y directions from the origin of the reticle R
By detecting the actual position of the chip
(Hxn, Hyn) can be calculated. In this embodiment, the offset amounts (Ox, Ox
y) separately to simplify arithmetic processing.
It was determined that the address error E in equation (9) was minimized.
Error parameters A and O are calculated by strict arithmetic processing
Needless to say, this may be done. [0079] As described above, according to the present invention, on a substrate such as a wafer,
For all of the multiple chip patterns (shot areas)
And the alignment error is reduced on average.
The number of good chips that can be picked up increases, and semiconductor devices are produced
Performance can be improved. In addition, multiple screens on the board
Each of the print areas is aligned with the circuit pattern image
Use the actual position information of some shot areas.
Position of the substrate based on the alignment position calculated
Positioning is actually measured for each area on the substrate
Throughput is higher than the alignment method
There is such a feature. Also some shot areas
Calculation using actual measured position information and design position information
The actual exposure position (alignment position) of each shot area.
Parameter A that determines the relationship between the
Is determined, but mechanically generated at the time of actual measurement, or
That electrical random errors are averaged out by arithmetic
, The error parameter A is such a random
There is also an advantage that it is hardly affected by components. The present invention is limited to a reduction projection type exposure apparatus.
And step-and-repeat type exposure apparatus, such as
Double projection stepper and proximity type stepper
It can be widely applied to par (X-ray exposure apparatus) and the like.
In addition to the exposure equipment, semiconductor wafers and multiple chip patterns
Inspection equipment for photomasks with defects (defect detection)
Step and repeat for each chip
To the reference position such as the inspection field of view or the probe needle
The present invention can be implemented in
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a schematic configuration of a reduction projection type exposure apparatus suitable for an embodiment of the present invention. FIG. 2 is a diagram showing a position of each detection center of an alignment system in the apparatus of FIG. FIG. 3 is a plan view showing the relationship. FIG. 3 is a flowchart showing the overall operation procedure using the alignment method of the present invention. FIG. 4 is a wafer suitable for alignment and exposure using the apparatus of FIG. FIG. 5 is a plan view of a wafer showing positions of chips to be step-aligned. [Description of Signs of Main Parts] WA: Wafer, CP, Cn: Chip, αβ
· Arrangement coordinates, 103, 104 ··· Actual measurement step by step alignment, 107 ··· step to determine error parameter, 108, 109, 110, 111 ··· Step and along the corrected actual chip arrangement coordinates The step of positioning by the repeat method.

Claims (1)

(57) [Claims] Each of a plurality of shot regions formed in a regular arrangement in advance according to design position information on a substrate on which circuit elements are to be formed is relatively aligned with an image of a circuit pattern to be overlaid and exposed. A method of forming a circuit pattern in the shot area by sequentially transferring an image to each of the shot areas, comprising: (a) three or more n non-adjacent ones of a plurality of shot areas on the substrate Setting an area as an alignment shot area, and sequentially detecting position information of alignment marks associated with each of the n alignment shot areas, thereby determining measured position information of each of the n alignment shot areas. (B) relating to positions of a plurality of shot areas on the substrate;
Information and used when exposing the circuit pattern image.
Between the shot information and the design position information of the plurality of shot areas.
When the relationship is defined by an error parameter matrix including each component of the remaining rotation error, orthogonality error, and expansion / contraction error,
Calculating the value of each element in the error parameter matrix by an approximate calculation process using design position information and measured position information of each of the n alignment shot regions; and (c) calculating the calculated error parameter. A relative alignment position between each of the plurality of shot areas on the substrate and the circuit pattern image is calculated by a correction operation based on the design position information based on a value of each element of the matrix, and the corrected alignment is calculated. Performing the overlay exposure at a position. 2. The method according to claim 1, wherein the value of each element of the error parameter matrix is calculated by a least squares approximation. 3. 2. The method according to claim 1, wherein the transfer of the image of the circuit pattern to the substrate is performed by a proximity type X-ray exposure apparatus. 4. The method according to claim 1, wherein the image of the circuit pattern is a projection image of a pattern of a mask formed and projected through a projection optical system. 5. The actually measured position information of each of the n alignment shot regions is determined by a relative displacement amount with respect to the circuit pattern image generated when the substrate is positioned based on the design position information. 5. The method of claim 4, wherein 6. The detection of the alignment marks associated with each of the n alignment shot regions is performed by irradiating the alignment marks with light having a wavelength that does not expose the resist on the substrate via the projection optical system, and generating light generated from the alignment marks. The method according to claim 4, wherein the information is obtained by photoelectrically detecting information through the projection optical system.