JP2629659B2 - Circuit pattern forming method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit pattern forming method suitable for an exposure apparatus for a semiconductor manufacturing apparatus or an apparatus for exposing a shot area on a photosensitive substrate by a step-and-repeat method. The present invention relates to precise relative positioning between a mask or a reticle and a semiconductor wafer or the like to be exposed.

[0002]

2. Description of the Related Art In recent years, semiconductor devices such as ICs and LSIs have been rapidly miniaturized and densified, and devices for manufacturing such devices, particularly masks and reticle circuit patterns, are formed on circuit patterns formed on semiconductor wafers. Increasingly, high-precision exposure apparatuses are also required to be superimposed and transferred. It is required that the circuit pattern on the mask and the circuit pattern on the wafer are overlapped with an accuracy of, for example, within 0.1 μm,
Therefore, at present, such an exposure apparatus exposes the circuit pattern of the mask to a local area (for example, for one chip) on the wafer, and then steps (steps) the wafer by a predetermined distance, and then exposes the circuit pattern of the mask again. A so-called step-and-repeat type apparatus, in particular, a reduction projection type exposure apparatus (stepper) has become mainstream.
In this step-and-repeat method, the wafer is placed on a stage that moves two-dimensionally and positioned with respect to the projected image of the circuit pattern of the mask. Therefore, the projected image and each chip on the wafer can be precisely overlapped. it can. In the case of a reduction type exposure apparatus, a through-the-lens for directly observing or detecting the alignment mark provided on a mask or a reticle and a mark attached to a chip on a wafer via a projection lens to align the mark. And an off-axis alignment method in which the whole wafer is aligned using a positioning microscope provided at a fixed distance from the projection lens, and then the wafer is sent directly below the projection lens. There are two methods.

[0003]

Generally, in the through-the-lens method, since alignment is performed for each chip on a wafer, the overlay accuracy is high, but there is a problem that the exposure processing time for one wafer is long. . In the case of the male-axis method, once the alignment of the entire wafer is completed, the wafer is simply stepped in accordance with the chip arrangement, so that the exposure processing time is reduced. However, since alignment is not performed for each chip, satisfactory overlay accuracy cannot always be obtained due to the effects of expansion and contraction of the wafer, rotation error of the wafer on the stage, orthogonality of movement of the stage itself, and the like.

Accordingly, the present invention does not perform mark detection on all of a plurality of chips (shot areas) arranged on a substrate to be processed such as a wafer, but only performs mark detection on a representative shot area. An object of the present invention is to provide a circuit pattern forming method capable of precisely aligning a mask and each shot area on a photosensitive substrate.

[0005]

In order to achieve this object, according to the present invention, a mask (R) on which a circuit pattern is formed and a plurality of shot areas (Cn) on a sensitive substrate (WA) are sequentially arranged. Move the sensitive substrate so that it is aligned,
The present invention is applied to a circuit pattern forming method using an exposure apparatus for superposing and exposing a circuit pattern on each of the plurality of shot areas.

In the circuit pattern forming method of the present invention, the arrangement coordinate system (αβ) of a plurality of shot areas is different from the movement coordinate system (x, y) of the two-dimensional movement stage (2, 3) in the exposure apparatus. A first stage in which the sensitive substrate is placed on the stage so as to be roughly aligned, and, among the plurality of shot regions on the sensitive substrate, four or more non-adjacent shot regions are selected as specific shot regions, and each specific shot region is selected. The mark in the shot area is a mark detection system (9, 10, 30 to 3) in the exposure apparatus.
8, 41 to 48), the stage is moved so as to be sequentially detected, and the position information of each detected mark is sequentially measured, and the position information of each mark measured in the second stage is moved. When the accuracy is deteriorated with respect to a predetermined reference, the position information of the mark in the shot area located next to the specific shot area in which the accuracy has deteriorated is additionally measured by the movement of the stage and the mark detection system. A part of the operation formula for specifying the error characteristics of the shot area with respect to the moving coordinate system of the array coordinate system is calculated based on the position of the mark measured so far while the stage is moving for mark detection. A third step executed using the information, and a final error characteristic is determined based on a result calculated in the third step, and a movement position of the stage is controlled based on the determined error characteristic. The Rukoto, a fourth step of sequentially exposing a circuit pattern of the mask to each shot area is performed.

Further, in the circuit pattern forming method of the present invention, the sensitive substrate is placed on the stage such that the coordinate system of the shot area is roughly aligned with the moving coordinate system of the two-dimensional moving stage in the exposure apparatus. After that, the stage is moved so that marks associated with each of several specific shot areas that are not adjacent to each other on the sensitive substrate are sequentially detected by a mark detection system in the exposure apparatus, and the position of each detected mark is moved. The information is sequentially measured, and when the measured position information of the mark is degraded in accuracy compared to a predetermined reference, the position information of the mark in the adjacent shot region located next to the specific shot region in which the accuracy is degraded Stage by moving the stage and using the mark detection system, and a specific shot area or adjacent shot determined by the position information of each measured mark. Determining an error characteristic between the array coordinate system and the moving coordinate system of the shot area based on the actually measured coordinate information of the shot area and the design coordinate information of each actually measured shot area; When sequentially exposing each of the above shot areas with the circuit pattern of the mask, a step of correcting the movement position of the stage with respect to the design coordinate position of the shot area based on the determined error characteristics is executed.

[0008]

According to the present invention, some (for example, four or more) of a plurality of chip pattern (shot) regions formed on a sensitive substrate such as a wafer which are not adjacent to each other are selected as specific shot regions. When measuring the position information of a mark attached to each specific shot area, if the position information of the mark is degraded in accuracy, add the position information of the mark of the shot area located next to the specific shot area Measured.

For this reason, for example, the mark of the selected specific shot area is accidentally deformed by the influence of the processing process, or dust happens to be attached to the mark, and the original measurement accuracy cannot be obtained. Determining the characteristics of the shot array (linear expansion / contraction error, residual rotation error, orthogonality error, offset error) can be prevented, and the characteristics of the shot array can be determined using mark position information having higher reliability. . Further, in claim 1
According to the described invention, the mark of the specific shot area
Moving the stage on which the sensitive substrate is mounted for detection
In the meantime, the position information of the mark measured so far (actual measurement value
Hxn, Hyn) to determine the characteristics of the shot array
Part of the operation expression for performing the operation, for example, the operation expression (14)
Calculations in (17)

(Equation 23) So that it is only used for arithmetic
Time, reducing overall alignment time
can do.

[0010]

FIG. 1 is a perspective view showing a schematic configuration of a reduction projection type exposure apparatus suitable for carrying out the method of the present invention.
The reticle R serving as a projection master is positioned so that the projection center passes through the optical axis of the projection lens 1, and is mounted on the apparatus. The projection lens 1 reduces the circuit pattern image drawn on the reticle R to 1/5 or 1/10 and projects it on the wafer WA. The wafer holder 2 is provided so as to be capable of vacuum suction of the wafer WA and to be minutely rotatable with respect to the stage 3 which moves two-dimensionally in the x and y directions. The drive motor 4 is fixed on the stage 3 and rotates the wafer holder 2. The movement of the stage 3 in the x direction is performed by driving the motor 5, and the movement in the y direction is performed by driving the motor 6. On two orthogonal sides of the stage 3, a reflecting mirror 7 whose reflecting plane extends in the y direction and a reflecting mirror 8 whose reflecting plane extends in the x direction are fixedly provided. A laser interferometer (hereinafter simply referred to as a laser interferometer) 9 projects a laser beam onto a reflecting mirror 8 to detect a position (or an amount of movement) of the stage 3 in a y-direction. Laser light is projected onto the mirror 7 to detect the position (or the amount of movement) of the stage 3 in the x direction. On the side of the projection lens 1, off-axis type wafer alignment microscopes (hereinafter, referred to as WAMs) 20, 21 are provided for detecting (or observing) alignment marks on the wafer WA. . The WAM 21 is located after the projection lens 1 in FIG. 1 and is not shown. Each of the WAMs 20 and 21 has an optical axis parallel to the optical axis AX of the projection lens 1,
a belt-like laser spot light YSP elongated in the x direction,
θSP is imaged on the wafer WA. (Spot light YS
P and θSP are not shown in FIG. ) These spot lights Y
SP and θSP are light having a wavelength that does not expose a photosensitive agent (photoresist) on the wafer WA, and vibrates in the y direction with a small amplitude in this embodiment. And WAM 20, 2
1 includes a photoelectric element for receiving scattered light or diffracted light from the mark, and a circuit for synchronously rectifying the photoelectric signal with the oscillation cycle of the spot light, and a mark for the center of vibration of the spot light θSP (YSP) in the y direction. And outputs an alignment signal corresponding to the amount of displacement in the y direction. Therefore, the WAMs 20 and 21 have the same configuration as a so-called spot light vibration scanning type photoelectric microscope.

The present apparatus is provided with a laser step alignment (hereinafter referred to as LSA) optical system for detecting a mark on the wafer WA via the projection lens 1. A laser beam L generated from a laser light source (not shown) and passed through an expander (not shown), a cylindrical lens, or the like.
B denotes light having a wavelength that does not expose the photoresist, and is incident on the beam splitter 30 and split into two light beams. One of the laser beams is reflected by a mirror 31, passes through a beam splitter 32, and is converged by an imaging lens group 33 so that the cross section becomes a band-shaped spot light. And enters the first folding mirror 34 arranged so as not to shield the projection optical path of the circuit pattern. The first turning mirror 34 reflects the laser beam upward toward the reticle R. The laser beam is provided below the reticle R, enters a mirror 35 having a reflection plane parallel to the surface of the reticle R, and is reflected toward the center of the entrance pupil of the projection lens 1. The laser beam from the mirror 35 is converged by the projection lens 1, and the wafer WA
An image is formed as a strip-shaped spot light LYS elongated in the x direction upward. The spot light LYS is used to relatively scan the diffraction grating mark extending in the x direction on the wafer WA in the y direction to detect the position of the mark. When the spot light LYSW irradiates the mark, diffracted light is generated from the mark. The optical information returns to the projection lens 1, the mirror 35, the mirror 34, the imaging lens group 33, and the beam splitter 32 again, is reflected by the beam splitter 32, and is reflected by the optical element 3 including a condenser lens and a spatial filter.
6 is incident. The optical element 36 transmits the diffracted light (first-order diffracted light and second-order diffracted light) from the mark and transmits the specularly reflected light (0
Then, the diffracted light is condensed on the light receiving surface of the photoelectric element 38 via the mirror 37. The photoelectric element 38 outputs a photoelectric signal according to the amount of the collected diffracted light. As described above, the mirror 31, the beam splitter 32, the imaging lens group 33, the mirrors 34 and 35, the optical element 36, the mirror 37,
The photoelectric element 38 constitutes a through-the-lens type alignment optical system (hereinafter, referred to as a Y-LSA system) that detects the position of the mark on the wafer WA in the y direction.

On the other hand, another laser beam split by the beam splitter 30 enters a through-the-lens type alignment optical system (hereinafter, referred to as an X-LSA system) for detecting the position of the mark on the wafer WA in the x direction. I do. X-LSA
The mirror system, the beam splitter 42, the imaging lens group 43, and the mirrors 44 and 4 are exactly the same as the Y-LSA system.
5. An optical element 46, a mirror 47, and a photoelectric element 48 are formed to form a strip-shaped spot light LXS elongated in the y-direction on the wafer WA.

The main controller 50 receives the photoelectric signals from the photoelectric elements 38 and 48, the alignment signals from the WAMs 20 and 21, and the position information from the laser interferometers 9 and 10, and performs various calculations for position adjustment. In addition to performing the processing, it outputs a command for driving the motors 4, 5, and 6. The main controller 50 includes an arithmetic processing unit such as a microcomputer or a minicomputer. The arithmetic processing unit includes design position information of a plurality of chips CP formed on the wafer WA (chip arrangement coordinate values on the wafer WA). Etc.) are stored.

FIG. 2 shows the WAMs 20, 21 and Y-LSA.
, SP-YSP, L-SPA
FIG. 3 is a plan view showing an arrangement relationship of YS and LXS on an image forming plane (same as a surface of a wafer WA) of a projection lens 1. FIG.
In, when a coordinate system xy having the optical axis AX as the origin is defined, the x-axis and the y-axis represent the moving directions of the stage 3, respectively. In FIG. 2, a circular area centered on the optical axis AX is an image field if, and a rectangular area inside the area is a projection image Pr of an effective pattern area of the reticle R. The spot light LYS is formed at a position outside the projection image Pr in the image field if and coincides with the x-axis,
The spot light LXS is also formed at a position outside the projection image Pr in the image field if and coincident with the y-axis. On the other hand, the two spot beams? SP, the oscillation center of the YSP is (parallel to the x-axis) segment at a distance Y ₀ in the y direction from the x-axis to match on l, and the distance Dx of the x-direction wafer It is determined to be smaller than the diameter of the WA. In this device, the spot light θSP, YSP
Are arranged symmetrically with respect to the y-axis, and the main controller 50 controls the spot light θSP, Y with respect to the projection point of the optical axis AX.
Information on the position of the SP is stored. The main controller 50 also controls the spot light LY with respect to the projection point of the optical axis AX.
Center position (distance Xl) of S in the x direction and spot light LXS
The information on the center position (distance Yl) in the y direction is also stored.

Next, the position according to the present invention using this device is described.
The flowchart of FIG.
This will be described with reference to the drawings. Note that this alignment is performed for the wafer WA.
Of the second and subsequent layers of the wafer W
Chip and alignment mark already formed on A
Have been. First, the wafer WA is unillustrated in Step 100.
Using the pre-alignment device shown, a straight line
Rough so that the notch (flat) faces in a certain direction
Positioned. The flat of the wafer WA is shown in FIG.
Thus, it is positioned so as to be parallel to the x-axis. next
In step 101, the wafer WA is moved to the wafer
Is transported on the rudder 2 and the flat keeps parallel to the x-axis.
The wafer is placed on the wafer holder 2 and vacuum-sucked.
The wafer WA has a plurality of chips as shown in FIG.
Along the orthogonal array coordinates αβ on the wafer WA
It is formed in a matrix. Α axis of array coordinates αβ
Is substantially parallel to the flat of the wafer WA. In FIG.
Wafer of the array coordinates αβ as a representative of the number of chips Cn
Chips C arranged in a line on the α-axis passing almost through the center of WA₀
~ C₆Only is shown. Each chip C₀~ C₆In it
Four alignment marks GY, Gθ, SX, S
Y is provided along with it. Now, chip C₀~ C₆of
Central chip C_ThreeIs the origin of the array coordinates αβ
On the α-axis, a diffraction grating-like marker extending linearly in the α-direction.
SY₀~ SY₆But each chip C₀~ C₆On the right side of
Have been killed. In addition, chip C_ThreeOn the β axis passing through the center of
Is a diffraction grating mark SX linearly extending in the β direction._ThreeBut
Top C_ThreeAnd another chip C₀, C₁, C
_Two, C_Four, C _Five, C₆For the center of the chip
SX on a line segment parallel to the β axis ₀~ SX_Two, SX
_Four~ SX₆Is provided. These marks SY_n, S
X_nIs detected by spot light LYS and LXS, respectively.
Is what is done. Each chip C₀~ C₆Beneath
Overall alignment of wafer WA (Global Alignment
Mark GY used to perform₀~ GY₆, Gθ
₀~ Gθ₆Is provided. These marks GY_n, G
θ_nIs a diffraction that extends linearly in the α direction on a line parallel to the α axis.
It is formed in a pattern on a lattice. Further in the α direction
Chips C in a row₀~ C₆Among them, for example,
C₀Mark GY₀And the rightmost tip C₆Mark Gθ
₆The distance in the α direction between
光 SP and YSP are set to coincide with the distance DX.
Have been. That is, in this embodiment, two separate marks are used.
GY₀And mark Gθ₆Off-axis
C Perform global alignment of WA. Because of this
Other marks GY₁~ GY₆, Mark Gθ₀~ Gθ_FiveIs a book
It is unnecessary and unnecessary. In short, with the α axis of the wafer WA
Elongated in the α direction on parallel (or coincident) line segments
It suffices that the two marks be present at a distance DX.

The main controller 50 determines the marks GY ₀ and Gθ ₆ from the position information of the stage 3 when receiving the wafer WA from the pre-alignment device and the position thereof, respectively.
Information such as the direction and amount of movement of the stage 3 until it is located within the detection (observation) field of view of the AM 21 or 20 is stored in advance as a constant unique to the apparatus. Therefore, the next step 102
In, the main controller 50 first drives the motors 5 and 6 to position the stage 3 so that the mark GY ₀ is located within the detection field of view of the WAM 21. Thereafter, main controller 50 moves stage 3 based on the alignment signal from WAM 21 and the position information from laser interferometer 9 so that the center of vibration of spot light YSP coincides with the center of mark GY _{0 in} the y direction. Position precisely in the direction. When the center of oscillation center and marks GY ₀ spotlight YSP match, while servo (feedback) control by the alignment signal to the main controller 50 motor 6 so that the state is maintained from WAM21, mark Jishita ₆ Is WA
The motor 4 is driven to rotate the wafer holder 2 so as to be detected by the M20 spot light θSP. Furthermore the main control unit 50 so that the center of the y direction of the vibration center of the mark Jishita ₆ spotlight θSP match, WAM2
The motor 4 is servo-controlled by the alignment signal from 0. By the above series of operations, the spot light YSP and the mark GY ₀ match, the spot light θSP and the mark Gθ ₆ match, and the moving coordinate system of the stage 3, that is, the coordinate system xy
Of the arrangement coordinate αβ of the wafer WA with respect to the coordinate system xy and the y direction (β
The association (regulation) regarding the position of (direction) is completed. Next, as the mark SX ₃ chips C ₃ in the center portion on the wafer WA is scanned by the X-LSA system of the spot light LXS, after positioning the stage 3 is moved in the x direction. At this time, the main controller 50 determines, based on the time-series photoelectric signal from the photoelectric element 48 and the position information from the laser interferometer 10, when the mark SX ₃ matches the spot light LXS in the x direction of the wafer WA. The position is detected and stored. Thereby, the coordinate system xy and x of the array coordinates αβ
The association regarding the position in the direction (α direction) is completed.
It should be noted that the association in the x direction is performed by X-L immediately before the exposure operation.
This is unnecessary when using the SA system. Through the above operation, the global alignment of the wafer WA (correspondence of the array coordinates αβ to the coordinate system xy) mainly based on the off-axis alignment is completed. In the case of the conventional method, the main controller 50 based on the array design value of each chip on the wafer WA (the center coordinate value of the chip at the array coordinates αβ).
Reads the position information from the laser interferometers 9 and 10, performs positioning (addressing) of the stage 3 by the step-and-repeat method so that the projected image Pr of the reticle R overlaps the chip, and then exposes (prints) the chip. )I do.

However, by the time the global alignment is completed, the accuracy of the alignment detection system, the setting accuracy of each spot light, or the position detection accuracy due to the optical and geometrical state of each mark on the wafer WA (effect of the process). An error occurs due to variation or the like, and the chips of the wafer WA are precisely aligned (addressing) in accordance with the coordinate system xy.
Not always. Therefore, in the embodiment of the present invention, it is assumed that the error (hereinafter, referred to as a shot address error) is caused by the following four factors.

(1) Rotation of the wafer; this is caused, for example, when the rotation of the wafer WA is corrected, because the positional relationship between the two spot lights YSP and θSP serving as the alignment reference is not accurate. It is represented by the remaining rotation error amount θ of the array coordinates αβ with respect to the system xy. (2) Orthogonality in the coordinate system xy: This is caused by the fact that the feed directions are not exactly orthogonal by the motors 5 and 6 of the stage 3, and is represented by the orthogonality error amount w.

(3) Linear expansion and contraction of the wafer in the x (α) direction and the y (β) direction; this may cause the wafer WA to expand and contract as a whole due to the processing process of the wafer WA. For this reason, the actual chip position deviates by a very small amount in the α and β directions with respect to the designed array coordinate value of the chip, and is particularly remarkable in the peripheral portion of the wafer WA. The amount of expansion and contraction of the entire wafer is represented by Rx and Ry in the α (x) direction and the β (y) direction, respectively. Here, Rx is a ratio of a measured value of a distance between two points in the x direction (α direction) on the wafer WA to a design value, and Ry is a measured value of a distance between two points in the y direction (β direction) of the wafer WA. And the design value. Therefore,
When both Rx and Ry are 1, there is no expansion or contraction.

(4) Offsets in the x (α) direction and the y (β) direction; this is due to the detection accuracy of the alignment system and the positioning accuracy of the wafer holder 2, etc. The shift occurs by an amount, and is represented by offset amounts Ox and Oy. In FIG. 4, the remaining rotation error θ of the wafer WA and the orthogonality error w of the stage 3 are exaggerated.

In this case, the orthogonal coordinate system xy is actually an oblique coordinate system xy ′ inclined by a minute amount w, and the wafer WA is rotated by θ with respect to the orthogonal coordinate system xy. When the error factors (1) to (4) are added, the shot position (Fxn, Fy) to be actually positioned with respect to the shot (chip) at the coordinate position (Dxn, Dyn) in design.
n) is represented as follows, where n is an integer and represents a shot (chip) number.

[0022]

(Equation 1)

Here, w is originally a very small amount, and θ is also reduced to a very small amount by global alignment. Therefore, when first-order approximation is performed, Expression (1) is expressed by Expression (2).

[0024]

(Equation 2)

From this equation (2), the displacement (εxn, εyn) from the design value at each shot position can be calculated by equation (3).
It is represented by

[0026]

(Equation 3)

Now, when equation (2) is rewritten as a matrix operation equation, the following is obtained.

[0028]

Fn = A · Dn + O where

[0029]

(Equation 5)

[0030]

(Equation 6)

[0031]

(Equation 7)

[0032]

(Equation 8)

Therefore, the actual shot (chip) position is measured by detecting the mark, and when the actual measured value is detected as Hn, the positional deviation from the shot position Fn to be positioned, that is, the address error En (= Hn-Fn) ) To minimize the error parameters A (transformation matrix), O
(Offset). Therefore, assuming that the least square error is taken as the evaluation function, the address error E is expressed by equation (9).

[0034]

(Equation 9)

Therefore, the error parameters A and O are determined so as to minimize the address error E. In Equation (9), m represents the number of actually measured chips among the plurality of chips on the wafer WA. Now, when obtaining the error parameters A and O,
If the least-squares method is used, the amount of calculation is large as it is, so that the error parameter O (Ox, Oy) is separately determined in advance. Offset amount (Ox, O
Since y) is a global offset value of the wafer WA, the address error with respect to the design value (Dxn, Dyn) may be averaged by several m of the actually measured chip positions Hn on the wafer WA.

[0036]

(Equation 10)

[0037]

[Equation 11]

The shot position Fn to be positioned
Component Exn in the x direction among errors En between actual and measured values Hn
Is obtained from Expressions (4) to (8).

[0039]

[Expression 12] Exn = Hxn−Fxn = Hxn−
a ₁₁ Dxn−a ₁₂ Dyn−Ox, and the component Eyn of the error En in the y-direction is

[0040]

## EQU13 ## Eyn = Hyn-Fyn = Hyn-
become _{a 21 Dxn-a 22 Dyn-} Oy. Therefore, when the error parameter A is determined so as to minimize the error E in the equation (9), the elements a11, a12, a2
1, a22 is as follows.

[0041]

[Equation 14]

[0042]

(Equation 15)

[0043]

(Equation 16)

[0044]

[Equation 17]

When the elements a11, a12, a21, and a22 are obtained, the linear expansion / contraction amounts Rx and Ry, the remaining rotation error amount θ, and the orthogonality error amount w can be immediately obtained from Expression (6).

[0046]

Rx = a11

[0047]

[Equation 19] Ry = a22

[0048]

[Equation 20] θ = a21 / Ry = a21 / a
22

[0049]

[Mathematical formula-see original document] w =-(a21 / Ry)-(a
12 / Rx) = − (a21 / a22) − (a12 / a11) Therefore, in order to determine the error parameters A and O, for some (four or more) chips on the wafer WA after the global alignment is completed, X-LSA, Y-LS
Using the design value (Dxn, Dyn) of the chip in which the positions of the marks SXn and SYn were actually measured using the A system, the equation (1) was obtained.
0), (11) and (14) to (17).

Therefore, returning to the flowchart of FIG. 3, the description of the operation will be continued. After the global alignment is completed, main controller 50 measures the positions of a plurality of chips on wafer WA. First, in step 103, the main controller 50 positions the stage 3 based on the array design value so that the X-LSA spot light LXS is arranged in parallel with the mark SX0 attached to the chip C0 at the left end in FIG. Stage 3 so that the mark SX0 crosses the spot light LXS.
Is moved (scanned) by a fixed amount in the x direction. During this movement, main controller 50 stores the waveform of the time-series photoelectric signal of photoelectric element 48 in association with the position information in the x direction from laser interferometer 10, and stores mark SX0 and spot light LXS from the waveform state. And x0 at the time when x and x coincide with each other
Is detected. Next, main controller 50 determines in step 104 that Y
-Position the stage 3 based on the array design value so that the LSA system spot light LYS is arranged in parallel with the mark SY0 attached to the chip C0. Thereafter, the stage 3 is moved by a certain amount in the y direction so that the mark SY0 crosses the spot light LYS. At this time, the main controller 50 stores the time-series waveform of the photoelectric signal of the photoelectric element 38 in association with the position information in the y-direction from the laser interferometer 9, and determines from the waveform state that the mark SY0 and the spot light LYS are y. The position y0 at the time when the directions coincide with each other is detected. And the main controller 5
In step 105, it is determined whether or not the same position detection has been performed for m chips in step 105. If not, the process proceeds to step 106, where the stage 3 is moved to another chip on the wafer WA based on the array design value. Then, the same position detection operation is repeated from step 103 again. In this embodiment, for example, as shown in FIG. 5, a total of four chips C0, C6, C7, C8 and a central chip C3 located at substantially equal distances from the center of the wafer WA along each axis of the array coordinates αβ. It is assumed that the position detection in steps 103 and 104 is performed for each of the chips. Therefore, in step 105, m =
When it is determined that the value is 5, five actual measured values (Hxn, Hyn) are stored in main controller 50. That is, (Hx1, Hy1) = (x0, y0) chip C0 (Hx2, Hy2) = (x3, y3) chip C3 (Hx3, Hy3) = (x6, y6) ... chip C6 (Hx4, Hy4) = (x7, y7) Chip C7 (Hx5, Hy5) = (x8, y8) Chip C8 Five actually measured values are sequentially detected. When the five measured values are detected, if the measured value of a certain chip is significantly different from the design value (Dxn, Dyn) of the chip, for example, the positioning accuracy differs by more than twice the positioning accuracy determined by the global alignment. In such a case, the measured value of the chip may be ignored, and the mark position of the chip adjacent to the chip may be measured, for example. This is because when the mark of the chip to be measured is accidentally deformed by the processing process, when dust is attached to the mark, the contrast of the optical image of the mark (the generation intensity of diffracted light) is weak, and the S of the photoelectric signal is low. This is to compensate for the deterioration in accuracy of position measurement that occurs when the / N ratio is low, and such additional actual measurement is performed as a characteristic procedure of the present invention.

As a method of compensating for the deterioration of the accuracy of the position measurement, a total of nine or more chips, for example, chips in each of the four quadrants of αβ in the array coordinates in FIG. Measure the position of the chip.
Design value (Dxn, Dy) of each chip
n), a method of selecting five measured values in the order closest to n), a method of simply not using measured values (Hxn, Hyn) that are significantly different from the design values (Dxn, Dyn) in the subsequent arithmetic processing, and the like. .

Next, in step 107, the main controller 50 executes the above equations (10) and (11) and the equations (14) to (1).
The error parameters A and O are determined based on 7). In this determination, the main control device 50 has previously selected five design values of each chip for which the above five actually measured values have been detected,
It is assumed that the design values (Dxn, Dyn) are stored as follows.

(Dx1, Dy1) = (x0 ′, y0 ′) Chip C0 (Dx2, Dy2) = (x3 ′, y3 ′) Chip C3 (Dx3, Dy3) = (x6 ′, y6) ') Chip C6 (Dx4, Dy4) = (x7', y7 ') Chip C7 (Dx5, Dy5) = (x8', y8 ') Chip C8 Prior to the decision of O, 5
Each time the position measurement (so-called step alignment) of one chip is completed, for example, while moving the stage 3 in step 106 of FIG. 3, the equations (10), (11), (1)
Some of the operations 4) to (17) can be executed simultaneously. That is, equations (10), (11), and (14)
In (17), arithmetic elements representing the algebraic sum of data (actual measurement values, design values) for each chip are sequentially added each time actual measurement (step alignment) of one chip is completed. The operation elements are as follows.

[0054]

(Equation 22)

Further, among these arithmetic elements, the wafer WA
If the chip to be actually measured is determined in advance and there is no change, steps 103, 104, 105, and 1 in FIG. 3 are performed on the calculation elements including only the design values (Dxn, Dyn).
It may be calculated before the execution of step 06. As described above, if some calculations are performed in parallel with the actual measurement value measurement operation, the overall alignment time does not become very long. Then, at the stage when five measured values are obtained, main controller 50 uses the results of the arithmetic elements to obtain equations (10) and (1).
After calculating the offset amount (Ox, Oy) in 1), the elements a11, a12, a2 of the array are further calculated by the equations (14) to (17) using the offset value and the result of the operation element.
1, a22 is calculated. Since the error parameters A and O are determined by the above operation, in the next step 108 of the main controller 50, the wafer WA is obtained by using the above equation (4).
, The shot address (Fx) corrected by the error parameter.
n, Fyn) is calculated, and a chip arrangement map (shot address table) corrected for the design values (Dxn, Dyn) is created in the storage means (semiconductor memory). This array map is, for example, the position (Fx
0, Fy0) and position (Fx1, Fx1, Fx0) for chip C1.
y1),..., etc., each position data is stored corresponding to the chip number.

Next, main controller 50 executes step 10 in FIG.
In step 9, the stage 3 is positioned (addressed) in a step-and-repeat manner according to the stored array map. As a result, the chip on the wafer WA and the projected image Pr of the reticle R accurately overlap with each other, and in the next step 110, the projected image Pr is exposed (printed) on the chip.
I do. If the exposure of all the chips on the wafer WA is not completed in step 111, the step-and-repeat operation is repeated again from step 109. If it is determined in step 111 that the exposure of all chips on the wafer WA has been completed, then in the next step 112, the wafer WA
Is performed, and all the exposure processing for one wafer is completed.

As is clear from the embodiment of the present invention, as the number of chips to be step-aligned on the wafer WA increases, the measurement accuracy improves, but the measurement time increases accordingly. For this reason, it is desirable to select five chips to be step-aligned in the arrangement as shown in FIG. 5 from the viewpoint of shortening the measurement time and improving the measurement accuracy. However, when the minimum line width of the circuit pattern to be overlap-exposed is not so small (for example, 2 to 5 μm) and it is not necessary to increase the measurement accuracy, the wafer W
Three chips separated from each other on A (for example, C0, C6,
It is sufficient to perform step alignment (chip position measurement) for C7), and the measurement time is further reduced.
Also, at the time of step alignment, the marks SXn attached to a plurality of chips to be step-aligned are collectively detected by the X-LSA spot light LXS instead of detecting both the positions in the x direction and the y direction of each chip. After relative scanning (stage scanning) is performed to detect only the position of each chip in the x direction, each of the marks SYn of each chip is collectively scanned with the Y-LSA spot light LYS to perform the scanning in the y direction of each chip. The position may be detected. In this way, when there are a plurality of chips to be actually measured in the same column or the same row on the chip arrangement, a position measurement at a higher speed can be performed than in the case where both the x direction and the y direction are detected for each chip. Can be expected.

If the main controller 50 inputs data from a keyboard device (not shown) to arbitrarily select which chip on the wafer WA should be subjected to the step alignment, the main controller 50 changes according to the processing conditions of the wafer WA. It is possible to more flexibly cope with the changing surface state (particularly, mark shape), and it can be expected to improve the accuracy of position measurement.
Also, the offset amount (O) using equations (10) and (11)
In determining (x, Oy), for example, only the position measurement results of chips within a specified range from the center of the wafer WA may be used. The specified range may be determined, for example, within a circle having a half diameter of the wafer WA,
The size of the range may be arbitrarily changed according to the accuracy characteristics of the exposure apparatus (stepper such as reduction projection type, equal-size projection, proximity, etc.) when chips and marks are formed on the wafer WA.

In the present embodiment, the addressing of the step-and-repeat method is performed by applying the equation (4) to all the chips of the wafer WA.
Equation (4) can be applied to the so-called block alignment in which the surface is divided into several regions (blocks) and an optimal alignment is performed for each block. For example, in FIG. 5, step alignment is performed on a total of nine chips, that is, four chips located in each quadrant of the array coordinates αβ and five chips C0, C3, C6, C7, and C8 shown in FIG. After detecting the actual measurement value of the position of, the error parameters A and O are determined using the equations (10), (11), and (14) to (17) for each of the quadrants of the array coordinates αβ. 4)
The position (Fxn, Fyn) is calculated. For example, for the block of the first quadrant of αβ in the array coordinates,
Equation (4) is determined using the measured values of one chip in the phantom and four chips C3, C6 and C7, and
For the blocks in the quadrant, equation (4) is determined using the measured values of one chip of the second quadrant and four chips of chips C0, C3 and C7. Then, at the time of actual exposure, the chip on the wafer WA is aligned with the projection image Pr based on the shot position (Fxn, Eyn) from Expression (4) determined for each block. In this way, position detection and alignment failure due to non-linear elements on the wafer can be reduced, and unlike conventional block alignment, blocks can be formed while averaging elements are left. There is an advantage that the alignment accuracy is almost averaged for all chips. In addition, a great advantage can be obtained in the case of mixing with an exposure apparatus other than a stepper, particularly a mirror projection exposure apparatus. In general, the chip arrangement of a wafer burned by a mirror projection exposure apparatus is often curved. Therefore, when performing overlay exposure on the wafer using a stepper (mixing and matching), if the above-described block alignment is performed, the curvature of the chip arrangement in each block becomes so small that it can be ignored. Baking with extremely high overlay accuracy can be performed over the entire surface of the wafer.

As described above, in the exposure apparatus suitable for the embodiment of the present invention, the position of the mark (chip) is detected by irradiating the spot light of the laser on the mark on the wafer WA. Alignment system for single oscillation or linear scanning at constant speed, or the mark on reticle R and the mark on wafer WA are observed (detected) by a microscope objective lens arranged above reticle R. An exposure apparatus using a so-called die-by-die alignment optical system that performs alignment by using the same method can be implemented in exactly the same manner. In this case, if it is assumed that the reticle R is not moved slightly in the x and y directions for alignment during die-by-die alignment, the projected image of the mark on the reticle R is changed to the spot lights LXS and LYS of the present embodiment. Would be equivalent. In the case of a system in which the reticle R is slightly moved, the reticle R is first set accurately to the origin position. In step alignment (actual measurement) of a plurality of chips, the stage is stepped in accordance with the array design value, and then the reticle R
The reticle R is finely moved so that the mark of the mark and the mark of the chip to be measured have a predetermined positional relationship, and the amount of movement of the reticle R from the origin in the x and y directions is detected.
The actual measurement value (Hxn, Hyn) of the position of the chip can be calculated.

In this embodiment, the offset amounts (Ox, O
y) was separately obtained to simplify the arithmetic processing, but error parameters A and O that minimize the address error E in equation (9) were calculated by exact arithmetic processing. Needless to say, it is good.

[0062]

As described above, according to the present invention, an alignment error is reduced on average for all of a plurality of chip patterns on a substrate to be processed such as a wafer, and a non-defective product can be obtained from one substrate to be exposed. The number of chips increases, and the productivity of semiconductor elements can be improved. For alignment shots (specific shots) whose accuracy is degraded due to the influence of a process or dust, position information of a mark in a shot area located next to the specific shot area is measured. The reliability of determining the sequence of the region is improved.

Further, since position measurement using marks of the same shape is repeated a plurality of times, there is an advantage that a mechanical and electrical random error of the detection system is reduced. Variation in sensitivity of the alignment sensor (microscope) for position detection is suppressed by statistical processing, and overall alignment accuracy is improved. Some more specific shot areas
Move the stage on which the sensitive substrate is placed for mark detection.
To determine the characteristics of the shot array while
To perform a part of the overall alignment
The exposure processing time for one sensitive substrate
Shorter. The present invention is not limited to a reduction projection type exposure apparatus, and can be widely applied to a step-and-repeat type exposure apparatus, for example, a 1 × projection stepper or a proximity type stepper (X-ray exposure apparatus). .
In addition to the exposure apparatus, an apparatus (defect inspection, prober, etc.) for inspecting a semiconductor wafer, a photomask having a plurality of chip patterns, etc., aligns each chip with a reference position such as an inspection visual field or a probe needle in a step-and-repeat manner. The present invention can be carried out in the same manner.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a schematic configuration of a reduction projection type exposure apparatus suitable for an embodiment of the present invention.

FIG. 2 is a plan view showing a positional relationship between detection centers of an alignment system in the apparatus shown in FIG.

FIG. 3 is a flowchart showing an overall operation procedure using the alignment method of the present invention.

FIG. 4 is a plan view of a wafer suitable for alignment and exposure using the apparatus of FIG. 1;

FIG. 5 is a plan view of a wafer showing positions of chips to be step-aligned.

[Description of Signs of Main Parts]

WA: wafer, CP, Cn: chip, αβ
· Arrangement coordinates, 103, 104 ··· Actual measurement step by step alignment, 107 ··· step to determine error parameter, 108, 109, 110, 111 ··· Step and along the corrected actual chip arrangement coordinates Positioning process by repeat method.

Claims (2)

(57) [Claims] And a step of moving said sensitive substrate so as to sequentially align a mask on which a circuit pattern is formed with each of a plurality of shot areas on said sensitive substrate, and applying said circuit pattern to each of said plurality of shot areas. A method of forming a plurality of circuit patterns on the sensitive substrate by using an exposure apparatus for overlay exposure, comprising: (a) providing a plurality of shot areas with respect to a moving coordinate system of a two-dimensional moving stage in the exposure apparatus; A first step of placing the sensitive substrate on the stage so that the array coordinate system is roughly aligned; and (b) four or more non-adjacent ones of the plurality of shot areas on the sensitive substrate Is selected as a specific shot area, and the stage is moved so that marks in each specific shot area are sequentially detected by a mark detection system in the exposure apparatus. (C) when the detection information of each mark obtained in the second step has deteriorated in accuracy compared to a predetermined reference, The mark detection system additionally detects a mark of a shot area located next to the specific shot area where the error has occurred, and specifies an error characteristic of the array coordinate system of the shot areas with respect to the moving coordinate system. A third step of performing the calculation of the unit using the mark detection information acquired so far while the stage is moving for mark detection; and (b) calculating in the third step. A final error characteristic is determined based on the determined result, and the stage movement position is controlled based on the determined error characteristic, thereby sequentially exposing the circuit pattern of the mask to each of the shot areas. the 4th Circuit pattern forming method, which comprises the steps. 2. The method according to claim 1, further comprising: moving the sensitive substrate so as to sequentially align the mask on which the circuit pattern is formed with each of the plurality of shot regions on the sensitive substrate; and applying the circuit pattern to each of the plurality of shot regions. A method for forming a plurality of circuit patterns on the sensitive substrate by using an exposure apparatus for overlay exposure, comprising: (a) array coordinates of the shot area with respect to a moving coordinate system of a two-dimensional moving stage in the exposure apparatus; After placing the sensitive substrate on the stage so that the system is roughly aligned, marks associated with each of a number of specific shot areas that are not adjacent to each other on the sensitive substrate are marks in the exposure apparatus. The stage is moved so as to be sequentially detected by a detection system, detection information corresponding to the position of each mark is sequentially obtained, and detection of each obtained mark is performed. When the information has deteriorated in accuracy as compared with a predetermined reference, a step of additionally detecting a mark in an adjacent shot area located next to the specific shot area causing the accuracy deterioration by the mark detection system; The arrangement coordinate system of the shot area and the movement based on the actually measured position information of the specific shot area and the adjacent shot area determined by the obtained detection information of each mark and the design position information of each actually measured shot area. Determining an error characteristic with respect to a coordinate system by calculation; and (c) when sequentially exposing each shot area on the sensitive substrate with the circuit pattern of the mask, the stage based on the determined error characteristic. Correcting the movement position of the shot area with respect to the design position information of the shot area.