JP2938601B2 - Arrangement method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arrangement of modules in an apparatus for automatically creating a logic circuit diagram from net data. When creating a logic circuit diagram of an electronic CAD system, an arrangement cost is calculated from input net data, and the arrangement is performed while freely moving the arrangement area.

In this case, it is necessary to reduce the number of pages to make the logic circuit diagram easier to understand.

[0003]

2. Description of the Related Art In general, when a logic circuit diagram is input from an electronic CAD system, a process of creating a netlist is performed by arranging a data flow based on a connection relationship between the FROM-TO nets. The extracted module data is extracted and processed.

That is, by referring to the module data having the pin data from the pin data as the net data, the data to be arranged next is determined and processed.

[0005]

However, in such a conventional module arrangement method, one of the most optimal module data is extracted from the net data according to the connection relation, and the arrangement processing is performed. Since the module having the strongest connection relation is extracted and sequentially processed for that module, it is compared with a manual logic circuit diagram using an interactive input format, which is a general circuit diagram creation means. There has been a problem that the number of modules per page is reduced by several steps, the number of pages is increased from 1.5 times to about 2 times, and the logic circuit diagram is difficult to understand.

[0006] This is inadequate for data having a small module size, such as analog parts. Since each module is handled individually, it is necessary to secure a certain area between modules. However, it is inevitably required to be arranged relatively large. The present invention
The present invention has been made in view of such conventional problems, and has as its object to provide an arrangement method that reduces the number of pages and makes a logical circuit diagram easier to understand.

[0007]

FIG. 1 is an explanatory view of the principle of the present invention. In FIG. 1, 3A is a tentative module generating means for creating a tentative module in which a plurality of macros of a macro having an arbitrary size or less are defined as one macro, 3B is a cost calculating means for calculating a channel interval control cost based on the circuit data,
3C is a variable channel generating means for generating a channel according to the channel interval control cost by repeating a core module setting for setting a core module and a grouping for generating a module set with the core module as one group;
D is a level sorting means for rearranging modules having a connection relationship among modules in the same group by the level grouping by level sorting, and 3E is an inter-group correcting means for optimizing the number of inter-group wiring crosses.

[0008]

According to the present invention, provisional modularization is performed by setting a plurality of sets to one macro for macros of an arbitrary size or less from netlist-based circuit data, and the cost of the nuclear module (channel interval control cost) is reduced. calculate.
A nucleus module is set from the module group, a variable channel is generated according to the channel interval control cost during grouping, and if the threshold value is exceeded, a new nucleus module is set and the above-described processing is repeated.

After grouping is completed, level sorting is performed according to the flow of signals, and inter-group correction for optimizing the number of inter-group wiring crosses is performed. As described above, the optimal arrangement of modules is performed by taking the concept of the variable channel as the interval width between modules, so that the number of pages can be reduced and the logic circuit diagram can be easily understood.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 8 are views showing an embodiment of the present invention.
In FIG. 2, reference numeral 1 denotes a display device, and the display device 1 is connected to a CPU 3 via an interface unit 2.

An input device 4 is connected to the CPU 3 via an interface unit 5. Reference numeral 6 denotes a disk device having a function as a database.
Connected to U3. Reference numeral 8 denotes a RAM serving as a memory. The RAM 8 has an internal table 9 for storing netlist-based circuit data.

Reference numeral 10 denotes a ROM.
A module arrangement processing program 11 for realizing optimal arrangement of modules is stored. The CPU 3 controls each unit, and creates a temporary module 3A for creating a temporary module in which a plurality of macros of a given size or less are set as one macro, and a cost calculation unit 3B for calculating a channel interval control cost based on the circuit data. A variable channel generating means 3C for generating a channel according to the channel interval control cost by repeating a core module setting for setting a core module and a grouping for creating a module set with the core module as one group; and the grouping. And has a function as a level sorting means 3D for rearranging modules having a connection relationship among modules in the same group by level sorting and an inter-group correcting means 3E for optimizing the number of wiring crosses between groups.

Next, the operation will be described. FIG. 3 is a flowchart illustrating the operation. In FIG. 3, first, data input is performed in step S1. In other words, circuit data based on the netlist is input, and macro and net information constituting the circuit are set in the internal table 9.

Next, in step S2, a temporary module is formed. In a coordinate system with a basic size of 1 × 1 (minimum unit between macro pins), a plurality of set macros are treated as one macro (module) for macros of an arbitrary size or less, to speed up processing and normalize module arrangement. I do. Conventionally, as shown in FIG.
2 and macros 13 and 14 having an arbitrary size or less were treated equally, but as shown in FIG. 4B, a plurality of set macros 15 of macros 13 and 14 having an arbitrary size or less are regarded as one macro (module). By creating a temporary module, high-speed processing is performed, and a normalized module arrangement is performed.

In FIGS. 4A and 4B, reference numeral 16 denotes a module. Next, cost calculation is performed in step S3. Channel spacing control based on the connection strength of the net (number of connections between modules), the number of input / output pins of the module, the layout cost determined from the module size, the number of wiring between modules (expected number of X and Y directions), and the value determined from the correction value. Cost. Cc = Mc × Kc Mc = (placement cost) Kc = (number of wires between modules) × (correction value) (correction value = 1 or an integer greater than or equal to 1) That is, as shown in FIG. A placement cost Mc is obtained from the number of connections between modules, the number of input / output pins of the module, and the module size, and a value Kc obtained by multiplying the expected number of wirings between modules after placement by a correction value for controlling the channel capacity range of the router and the placement cost Mc. To determine the channel interval control cost Cc.

In FIG. 5, reference numerals 18 to 21 denote modules arranged with respect to the target module 17, respectively. next,
In step S4, a variable channel is generated based on the channel interval control cost Cc obtained in step S3 during the repetition of the nuclear module and the grouping.

When the number of channels exceeds the threshold value, a new kernel module is formed and grouping is performed. Here, the grouping is a set of a plurality of channels, and when performing the grouping, as shown in FIG. 6, each module 22 serving as a core of channel allocation is set. This is determined from the arrangement cost, the number of wirings between modules, and the number of module stages from the input / output of the circuit.

When one arbitrary module 22 is selected, the distance from the second and subsequent modules to the n-1 nucleus candidate module is also calculated as the nuclear selection cost. Thus, the nuclear module is formed, and then the group is formed. A macro set is created in which each of the core modules 22 selected in the core module conversion is a group.

Within this group, Cc of the allocated channel is calculated and channel assignment processing is performed. At this time, the number of modules to be assigned to one channel is determined by the cost Kc ≦ m. Next, level sorting is performed in step S5. In one group, the channel exchange is performed for all the modules except for the core module using the wiring cross relation and the module relation with the feedback connection as the cost of the signal flow (in → out).

As shown in FIG. 7 (A), modules 23 and 24 having a connection relation among modules 23 and 24 which have been grouped into the same group 25 are subjected to level sorting in FIG.
Rearrange as shown in (B) and add coordinates. Next, an inter-group correction is performed in step S6. That is, the number of wiring crosses between groups is optimized (see FIG. 8). here,
Optimal refers to the following conditions.

(1) The number of wiring crosses is near an arbitrary value Xc. (2) The total cost of one group is equalized. (3) External input / output is to be integrated into one group. In addition, in FIG. 8, 26-28 shows each group. Finally, in step S7, the layout data is output from the internal table 9 to the disk device 6.

As described above, the cost for the placement processing is calculated based on the netlist-based circuit data, and the interval between the modules on the circuit diagram is grasped on the concept of a variable channel on the basis of the calculated value, and the optimum module placement is calculated. Is performed, the number of pages can be reduced, and the logic circuit diagram can be easily understood.

[0023]

As described above, according to the present invention, in the automatic layout processing of the logic circuit diagram, the module interval is determined by the variable channel, so that the number of pages can be reduced and the logic circuit can be reduced. The figure can be easily understood.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 shows an embodiment of the present invention.

FIG. 3 is a flowchart illustrating an operation.

FIG. 4 is an explanatory diagram of temporary module conversion.

FIG. 5 is an explanatory diagram of cost calculation.

FIG. 6 is an explanatory diagram of nuclear modularization and grouping.

FIG. 7 is an explanatory diagram of level sorting.

FIG. 8 is an explanatory diagram of correction between groups.

[Explanation of symbols]

 1: Display device 2, 5, 7: Interface unit 3: CPU 3A: Temporary module unit 3B: Cost calculation unit 3C: Variable channel generation unit 3D: Level sorting unit 3E: Inter-group correction unit 4: Input device 6: Disk Apparatus 8: RAM 9: Internal table 10: ROM 11: Module placement processing program 12 to 14: Macro 15: Set macro 16, 18, 21 to 23, 24: Module 17: Target module 22: Core module 25 to 28: Group

────────────────────────────────────────────────── (5) References JP-A-63-221480 (JP, A) JP-A-63-195772 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 17/50

Claims (1)

(57) [Claims] An apparatus for automatically creating a logical circuit diagram from netlist-based circuit data, comprising: a temporary module converting means (3A) for generating a temporary module in which a plurality of macros of an arbitrary size or less are set as one macro; A cost calculation means (3B) for calculating a channel interval control cost based on the circuit data; a core module for setting a core module; and a grouping for creating a module set including a core module as one group, and the channel is repeated. A variable channel generating means (3C) for generating a channel according to an interval control cost; and a level sorting means (3D) for rearranging modules having a connection relationship among modules in the same group by the level grouping.
And an inter-group correcting means (3E) for optimizing the number of inter-group wiring crosses, wherein module arrangement is performed by determining module intervals.