JPH0887533A - Function cell arrangement method for semiconductor device - Google Patents

Abstract

PURPOSE: To turn the cells of the same functions included in the same cell string or the cells related closely to each other into a macro cell by carrying out successively such steps for the hierarchical division of a net list, the macro generation and the generation of a virtual terminal. CONSTITUTION: The group name corresponding to a single cell string and used for grouping of cells and two parameters of the relative positions of each group are previously added to each cell of a read new net list 22. This list 22 is divided into plural net lists based on the group name of each cell for generation of a class including the cells of the same functions or the cells related closely to each other. Then the cells are arranged in order for each divided group based on the relative position parameters showing the order of cells in each group. The block generated by the arrangement of cents is regarded as a cell and a virtual terminal of a macro cell is generated. Then a net list is generated for the generated macro cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of arranging a functional cell of a semiconductor device which is composed of functional cells designed by a standard layout method, and more particularly, arranging a plurality of functional cells closely related to each other. And a method for arranging functional cells of a semiconductor device.

[0002]

2. Description of the Related Art An automatic arrangement of a semiconductor device designed by a conventional standard cell (cell-based) method will be described with reference to the drawings.

Referring to FIG. 11, a semiconductor device 100 having a functional cell 1 designed by a normal standard cell (cell-based) system has a logic cell region 4 in which the functional cells 1 are arranged in a column and The wiring channel region 5 is provided between the logic cell regions 4, and the wiring 3 that passes through the channel region 5 or vertically passes through the logic cell region 4 by the wiring feed cell 2.

Referring to FIG. 12 showing the configuration of a general automatic placement and routing CAD tool for designing the placement and wiring of the semiconductor device 100, this CAD tool is based on the circuit connection information 21 and the cell library 23. Based on the netlist expansion step (S13) of expanding the netlist and the output result of this netlist expansion step (S13) and the new netlist 22 generated by the timing constraint information input 26, initial automatic placement and placement improvement are performed. A cell placement step (S20) of performing and placing cells, an automatic routing step (S14) of automatically routing between cells based on the placement result, and a delay verification of verifying delays based on the timing information 26 and the delay library 25. Step (S
15) and.

The circuit connection information 21, which is input information, includes a circuit module name that is a circuit component, an external terminal name / type related to a module, a cell name (individual name) / type, a net name related to connection, and an external terminal or an instance terminal. It includes net information including arrangements, net weights (net combination) which are relative numerical values added to cells and nets connecting cells.
The net weight added to the net connecting these cells is
It represents the degree of coupling between the cells, and the degree of coupling causes the cells to be arranged close to each other or separated from each other.

The cell information included in the cell library 23 includes a cell name, cell shape (size), terminal name, terminal position (coordinates), input / output terminal type, terminal layer, and the like.

Referring to each of FIG. 13 showing a conventional automatic arrangement method and FIG. 7 showing a schematic view of cell column length limit values, the automatic arrangement method is as follows. A limit value 62 is provided for the sum of the cell widths included in one column, and there is a step (S61) of grouping so as to align (or fit) with the limit value 62 (see FIG. 7).

Next, regarding the cell rows (71 to 73), the cell order (7
1-73), the cell replacement and cell movement are performed so as to minimize the number of wirings, and the cell column correction step (S62) is included.

By using this conventional method, it is possible to carry out automatic arrangement assuming the arrangement shown in FIG.

[0010]

However, in the conventional automatic placement method, the sum of the cell widths to be arranged in the same column is the limit value of the cell column length in the first grouping process (S62). If the number of cells exceeds 62, the cells are divided into other groups, are not arranged in the same row, and the cell rows are replaced (see FIG. 9).

Further, even if the cells are divided into the same group, the cell columns are corrected and the cells are not arranged in a predetermined order (see FIG. 10).

Further, when the cell columns are exchanged and the order of the cells is exchanged, there arises a problem that the channel region between the cell rows becomes wide and the wiring length becomes long.

That is, according to the conventional automatic placement method, when cells are grouped with a limit value of the cell column length and cell column correction is performed, when cells with the same function are to be placed as one block, the cells are placed. There is a problem that it is not arranged at the expected position and replacement can easily occur.

Further, when the cell columns are exchanged and the order of the cells is exchanged, there arises a problem that the channel region between the cell rows becomes wide and the wiring length becomes long. .

Therefore, an object of the present invention is to provide a semiconductor device having, for the above-mentioned solution, a cell macro formation technique in which cells having the same function arranged in the same cell row or cells closely related to each other are made into one block cell. Is to propose the automatic placement method of.

[0016]

A method for arranging a functional cell of a semiconductor device according to the present invention is a basic cell for performing a desired logical operation by connecting a plurality of transistor elements or a plurality of passive elements with a predetermined wiring, and the basic cell. A plurality of functional block cells each having a desired logical function operation are arranged on one main surface of a semiconductor substrate, and a plurality of functional cells having the same function among the basic cells are repeatedly arranged. In the method of arranging the functional cells of the semiconductor device in the repetitive array portion of the functional cell of the semiconductor device having the repetitive array portion, the function name of the functional cell having the same function, the functional cell, the basic cell, and the functional block The functional cell, the basic cell, and the functional block are included in a netlist including respective connection relationships of cells. A netlist hierarchy dividing step of adding two parameters of a group name for grouping a group and a relative position order in this group to generate a divided netlist including the same functional cell of the same group name based on the group name And a macrocell generating step of generating a macrocell for each of the functional cells of the divided netlist, and a virtual terminal generating step of generating a virtual terminal of the macrocell, the netlist hierarchy dividing step, the macro generating step, and the This is a configuration having a cell macro conversion step that sequentially executes virtual terminal steps.

In the method of arranging a functional cell of a semiconductor device according to the present invention, a macro cell selecting step of selecting a macro cell having the highest degree of coupling among the macro cells, a width of a macro cell region in which the macro cell is arranged, and a plurality of basic cells are arranged. And a width of the arrayed basic cell row regions are compared, and an initial placement space generation step including a macrocell placement step of placing the macrocells based on the comparison result in the width comparison step. is there.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of arranging functional cells of a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

As shown in FIG. 8, it is considered to arrange a semiconductor device having cells in which cells of the same function are repeated as a group. G1 to G4 attached to FIG. 8 are group names attached to the cells A, B, C, and D, respectively.
Symbols A to D represent cells having the same function, and [0], [1] ... Subscripts.

Referring to FIG. 1, the method of arranging functional cells of a semiconductor device according to this embodiment includes a step (S11) of reading a netlist which is the circuit connection information 21, a step (S12) of reading a cell library 23, and Step for expanding the netlist based on the step (S1)
3) and the timing constraint information 26 are input to create the new netlist 22.

Next, the arranging method of this embodiment has a cell macro formation step (S1) and an initial arrangement space generating step (S2) to arrange cells.

Further, a step (S14) of performing automatic wiring based on the completed data of the new netlist 22 and cells, and the wiring / wiring result 24 is based on the delay library 25 and the timing constraint information 26. This is a configuration including a step (S15) of performing delay verification.

Further, referring to FIG. 2A, in the cell microminiaturization step of the functional cell placement method of the embodiment of the present invention, the new netlist 22 is read (S101).

Two parameters of a group name for grouping and relative positions in the group are added to each cell of the net list 22 in advance. The group used here corresponds to one cell column.

The netlist 22 is divided into netlists that generate a hierarchy including cells having the same function or closely related cells based on the group name of each cell (S10).
2 and S103).

Next, for each of the divided groups shown in FIG. 4, for each cell included in the group, the relative position parameter indicating the position (order) in the group
The cells are arranged side by side in that order (S105). The block generated by the arrangement of these several cells is generated as one cell, and the virtual terminal of the macro cell is generated (S1
06), which is a macro cell.

Finally, a netlist of the generated macrocell is generated, the netlist is divided, and the remaining netlist and the netlist incorporated in the read netlist are created.

FIG. 5 is a schematic representation of netlist generation. In the upper diagram, connection information between individual cells and a group name G1 and X and Y indicating relative positions are added to each cell. The state of the read netlist is shown. The lower diagram shows the state after processing, but it creates a netlist of macrocells that are divided by the same group name and that includes a group of cells arranged based on the relative position Y, and use it as a lower layer. The netlist it has is the top-level netlist.

Referring to FIG. 3 showing a cell arrangement of a semiconductor device to which the cell macro forming step is applied, macro cells (6a to 6e) are arranged. Also, the macro cell 6
e has a power supply line 8a and a ground line 9a, and further generates a virtual terminal 10.

Next, referring to FIG. 2B, in the initial placement space generating step of the functional cell placement method of the embodiment of the present invention, the cell having the largest net coupling to the previously placed macro cell is selected. And a step (S203) of comparing the macro area width in which the macro cell is arranged with the cell width of the basic cell row area,
If the macro area width is smaller than the cell width, the macro cell is placed in the cell row that is currently focused (S204), or if the macro area width is larger than the cell width, the next cell row next to the cell row that is currently focused. Place a macro cell in the cell row (S
205).

Referring to FIG. 6 showing the cell arrangement of the semiconductor device to which the initial arrangement space generating step is applied, first, the macro cell 6a is arranged.

Next, among the remaining macro cells, the macro cell 6b having the largest net connection to the macro cell 6a is formed.
Select The macro cell 6b is compared with the maximum cell width or the empty width of the cell row obtained by subtracting the macro cell 6a from the specified module width, and the macro cell 6b is more than the empty width of the cell row.
, The macro cell 6b is arranged in the next cell row. Similarly, the macro cell 6b and the macro 6c having a large net connection are selected, the empty width 8a of the cell row is compared with the width, and the macro cell 6b is arranged in the next cell row.

After arranging the macro cell 6g, the macro cell 6g and the macro cell 6h having a large net connection are selected.
The width of the macro cell 6h is compared with the empty width of the cell row after the macro cell 6g is arranged. Since the width of the macro cell 6h is smaller than (or the same as) the empty width of the ROW, the macro cell 6h is arranged in the empty area of the ROW. To do. Similarly, the arrangement position of the macro cell 6f is determined by comparing the empty area widths 8d of the cell rows.

[0034]

According to the method of the present invention, in the conventional automatic data path arrangement, the problem that the channel area is increased and the wiring length is lengthened due to the easy cell replacement is solved.
It is possible to arrange the cells having the same function in an assumed position.

[Brief description of drawings]

FIG. 1 is a flowchart of a method of arranging functional cells of a semiconductor device according to an embodiment of the present invention.

2 is a detailed flowchart of a method for arranging functional cells of the semiconductor device shown in FIG. 1, a partial view (a) shows a detailed flowchart of a cell macro conversion step, and a partial view (b) shows a detailed flowchart of an initial placement space generation step. Indicates.

FIG. 3 is an array of functional cells of a semiconductor device to which a cell macro conversion step of one embodiment of the present invention is applied.

FIG. 4 is a diagram showing a state of macro cell generation in cell macro conversion according to an embodiment of the present invention.

FIG. 5 is an image diagram of a netlist for macro cell generation for macroization according to an embodiment of the present invention.

FIG. 6 is an array of functional cells of a semiconductor device to which the initial placement space generating step of one embodiment of the present invention is applied.

FIG. 7 is a diagram showing criteria for grouping in a cell placement method of a conventional technique.

FIG. 8 is a diagram showing an arrangement assumption of a conventional cell arrangement method.

FIG. 9 is a diagram showing a problem of the conventional cell placement method.

FIG. 10 is a diagram showing another problem of the conventional cell placement method.

FIG. 11 is a configuration diagram showing a logic cell array of a semiconductor device designed by the standard cell method.

FIG. 12 is a flowchart of a conventional cell placement method.

FIG. 13 is a diagram schematically showing a method of a conventional cell placement method.

[Explanation of symbols]

1 Functional Cell 2 Field Cell 3 Wiring 4 Logic Cell Area 5 Channel Area 6, 6a, 6b, 6c, 6e, 6f, 6g, 6h Macro Cell 7, 7a, 7b Cell Outline 8, 8a, 8b Power Supply Line 9, 9a, 9b Ground line 10 Virtual terminal 11 Individual cell A, B, C, D Same function cell [0], [1], [2] Subscript

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/82 M

Claims (2)

[Claims] 1. A basic cell for performing a desired logical operation by connecting a plurality of transistor elements or a plurality of passive elements with a predetermined wiring, and a plurality of functional block cells including a plurality of the basic cells and performing a desired logical function operation. Each of which is arranged on one main surface of a semiconductor substrate, and wherein the repeating array of the functional cells of the semiconductor device is provided with a repeating array part in which a plurality of functional cells having the same function among the basic cells are repeatedly arranged. In the method of arranging functional cells of a semiconductor device in a part, the functional cells are added to a netlist including the function names of the functional cells having the same function and the connection relationships of the functional cells, the basic cells, and the functional block cells. And the group name for grouping the basic cell and the functional block cell and the phase in this group. A netlist hierarchical division step of adding two parameters of the pair position order and generating a divided netlist including the same functional cell of the same group name based on the group name; and dividing the divided netlist into macrocells for each of the functional cells. A macro cell generating step of generating and a virtual terminal generating step of generating a virtual terminal of the macro cell, and a cell macro forming step of sequentially executing the netlist hierarchy dividing step, the macro generating step and the virtual terminal step. A method of arranging a functional cell of a semiconductor device in the repetitive array section of the functional cells having the same function as described above. 2. A macro cell selecting step of selecting a macro cell having the highest degree of coupling among the macro cells, a width of a macro cell area in which the macro cells are arranged, and a width of a basic cell row area in which a plurality of the basic cells are arranged. 2. The function of the semiconductor device according to claim 1, further comprising: an initial placement space generating step including a width comparing step for comparing and a macro cell arranging step for arranging the macro cells based on the comparison result in the width comparing step. Cell placement method.