JP2721337B2 - Image signal encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION 〔Technical field〕   The present invention is applicable to facsimile, electronic image file, etc.
The present invention relates to an apparatus for encoding an image signal to be encoded. [Conventional technology]   Conventional facsimile and other image transmission devices and recent optical
Image file devices using disks and magnetic disks, etc.
In other words, by encoding and handling image signals,
Speed up the transmission or storage operation by reducing the amount of data
Is being measured.   For example, in the facsimile field, one-dimensional
Modified Huffman (MH) method for encoding, 2D
Modified lead (MR) method for coding, high efficiency
Modified as a dimensional encoding
(MMR) method is used.   The relationship between the MH method, MR method and MMR method is
The method includes a method very similar to the MH method, and also partially incorporates the MR method.
The modified one is the MMR method.   Also, the image to be encoded and the rules of the encoding method, etc.
In short, CCITT (International Telegraph and Telephone Advisory Committee)
It conforms to the recommendations of T4 and T6.   Furthermore, the above-mentioned encoding method is the same as that of the MMR method on March 2, 1985.
Facsimile of 52 pages or less of the Official Gazette of the 2nd (Extra No. 29)
Among the recommended communication methods for Group 4 devices (Postal Service 197)
Announced as a highly efficient two-dimensional coding method, the MH method is
As a one-dimensional coding method, the MR method is a two-dimensional coding method.
And both were notified in 1981 Notification No. 1013 of the Ministry of Posts and Telecommunications.
You.   The above three types of coding such as MH, MR, and MMR are coded.
Select to apply to the subsequent processing device that handles the processed image signal
Is done. And when the processing form of the subsequent stage is changed
Requires a circuit change suitable for it, and
Was. However, as mentioned earlier,
Related, and use this relationship to create a common encoding device.
It is desirable that three more encodings be achieved. 〔Purpose〕   The present invention has been made in view of the above points, and has been described above.
Modified Huffman coding, Modified
Coded and Modified Mode Lee
Of image signals in three coding modes
The purpose of this is to make
Feid Huffman coding, Modified lead sign
Coding or modified-mode lead code
Image signal encoding device that encodes image signals by encoding
Input means for inputting an image signal of an encoding line
And the image signal that has been encoded by the previous encoding operation is stored.
Buffer means for outputting the image signal of the reference line
And an image signal of a coding line input from the input means.
Detecting means for detecting a change point of the signal, and the detecting means
Counting means for counting the number of pixels between the detected transition points;
The horizontal mode image coding is performed based on the counting result of the counting means.
First generation means for generating run-length code contained in the code
And a picture of a coding line input by the input means.
Between the image signal and the reference line output from the buffer means.
A monitor that monitors the correlation of the change point with the image signal
And a pass mode based on the monitoring result of the monitoring means.
And second generating means for generating a vertical mode image code
And a horizontal mode run generated by the first generation means.
Length code or path model generated by second generation means
Output means for outputting an image code in a code mode or a vertical mode.
And the encoding mode to be executed is
Read-Read or Modified-Modified
-In the case of read encoding, the first generating means and the
Causing the encoding operation to be performed using both of the second generating means;
On the other hand, the coding mode to be executed is Modified Huff
In the case of the Man coding, a code is generated using the first generating means.
Encoding control means for performing the encoding operation and indicating the end of one screen
RTC code and line delimiter to indicate line delimiters
Modified Huffman coding, Modified
De Read Coding and Modified Modified
・ Can be generated in multiple formats corresponding to each of lead coding
With a memory table that can be used, the format according to the encoding mode
Generate RTC code and line break code with
An image signal encoding device having a generating means.
aimed to. 〔Example〕   FIGS. 1 and 2 show examples of the configuration of an encoding circuit to which the present invention is applied.
This is shown in the circuit block diagram of FIG. Next, the operation of the embodiment is described.
This will be described with reference to FIGS. 1 and 2 and FIGS. 3 to 5 and the like.
You.   The signal indicated by 121 in FIG. 1 is an image scanner or an image.
Code supplied from an external device such as a file or computer
This is an image signal to be encoded, and is “0” or “1” (for example, “0”
= White, "1" = black pixel)
Given. The signal indicated by 134 is the input of the image signal 121.
Clock supplied from external equipment in synchronization with power
There is one clock per pixel. Next, the note indicated by 136
The signal is a synchronizing signal.
It shows several types of synchronization signals indicating the interval and the like.   That is, in this embodiment, the image signal 121 to be encoded is
Like the signals given to the user printer, etc., each main scan
As a scanning image signal which is a serial image signal of
Shall be   Next, 101 is a coding line (image to be encoded)
Next to the last pixel of the actual image
So that the element (= virtual pixel) always becomes a change point
This is a circuit that creates a transition point.
A ". However, the above “virtual change point generating circuit A”
Do not change the actual image on the coding line
It has a good structure.   102 is a line buffer memory A, 103 is a line buffer memory
It is a buffer memory B, which is independently written or read
Operable RAM (random access memory)
RAMs that can be written or read independently
Access memory), each of which is coded
.Capacity capable of storing one line of binary image (main scanning image)
Prime number).   In addition, the line buffer memory A102 and the line buffer
One of the memory B103 is executing the write operation
The other is controlled to perform a read operation.
You. In other words, these two line buffer memories depend on each other.
To form a set of double buffer memories.   111 is a memory address counter,
Clock 134 corresponding to the number of pixels in the
This is the counter to be executed. The count value of the counter 111
Is a line buffer as the memory address signal 135.
Memory A102 and line buffer memory B103
Is commonly given to Also, memory address count
Data 111 returns to the initial value for each coding line,
Repeat the counting operation. Therefore, the line buffer
The binary image of each line written in the memory is newly input.
Corresponding to the pixel position of the image signal 121 of the line
It is read out for each pixel.   104 is a selector, which is a line buffer memory A10
Either 2 or line buffer memory B103
Obtain read data from the person performing the read operation.
This is a circuit that performs a selection operation in response to a select signal 901. This
Data selectively obtained by the selector 104 of
As the coding line 125, that is, the coding line
This is given to the next stage as reference data (image) for the application.   105 is the last pixel of the actual image on the reference line
Force the next pixel (virtual pixel) to always be a change point
A circuit that creates a change point in a virtual way
B ".   However, the virtual change point generation circuit B105 is a reference line.
The structure does not change the actual image on the screen.
You.   106 is a real image and a virtual pixel on the reference line
This is a circuit that detects the pixel that is the upper transition point.
This is referred to as “detection circuit A”.   107 is a real image and a virtual image on the coding line.
"Change point detection circuit B" is a circuit that detects a change point on a pixel.
Called.   108 is A register, 109 is B register, 110 is C register
, Each being a 4-bit shift register   The signal indicated by 126 is the actual image on the reference line.
A signal representing an image and a virtual pixel, and a signal represented by 127
Are the changes on the real image and virtual pixels on the reference line.
It is a transition point signal. The signal indicated by 128 is the coding line.
5 shows a change point signal on a real image on a virtual pixel and a change point signal on a virtual pixel.   112 receives a clock 134 and a synchronization signal 136 as inputs.
Timing of each circuit block based on
Timing signal for forming various timing signals 137
Road.   The operation of the circuit block shown in FIG.
An actual image (image to be coded) as shown in FIG.
This is explained using an example in which this is encoded by the MMR method.
I will tell.   First of all, the image of FIG. 4 exemplified here is simply described.
32 pixels per line (number of main scanning pixels = 32 pixels)
And a total of two lines (the number of sub-scanning lines = 2)
This is an extremely simple image that composes one page.   To actually encode the first line indicated by 402 in FIG.
Is a virtual line indicated by 401 in FIG. 4 as shown in FIG.
Is the reference line, and the first line 402 is
Ing line.   Also, when encoding the second line indicated by 403 in FIG.
6, the first line 402 in FIG. 4 is lifted as shown in FIG.
Coordinate the second line 403 as the Allens line
・ Line.   Hereinafter, suppose that one page consists of three or more lines of main scanning.
Even if the third line, the fourth line, ...
As mentioned, the reference line and the coding line
If the relationship of IN is gradually lowered, regardless of the number of sub-scanning lines,
Encoding can continue.   FIG. 3 shows the circuit block diagram shown in FIG.
This is a timing chart when given to Tsuk.   In FIG. 3, reference numeral 136-1 denotes a vertical synchronizing signal in the sub-scanning direction.
Indicates the section of the image, that is, the input period of the image of one page.
You. 136-2 is a horizontal synchronizing signal, an image section in the main scanning direction,
That is, it indicates the input period of the image of one line. 134 is the image
Reference numeral 121 denotes a signal of an image to be encoded illustrated in FIG.
Black pixel = "1" = "H", white image
Element = “0” = “L”. That is, as shown in FIG.
Of the images, the image in the section T1 is the one shown in FIG.
This is the actual image of the first line 402, and the image in the section T2 is encoded.
It is an actual image of the second line 403 shown in FIG.   The virtual line 401 shown in FIG. 4 is printed on an actual paper surface or the like.
In the case of such an image,
White or equivalent to out of paper, according to the MMR method
Is an all white (one line of pixels is all white pixels) line and virtual
It is stipulated that Therefore, the virtual shown in FIG.
Line 401 does not appear on image signal 121 shown in FIG.
No.   FIG. 5 is a timing chart showing the encoding operation of the first line 402.
Guchayat, a virtual line that becomes the reference line
In 401 and the first line 402 which is the coding line
Shows the relationship.   First, the image of the first line 402 shown in FIG.
When applied to the generation circuit A101, 122 (code
Virtual change point (virtual pixel) 302 as shown in FIG.
Is added to the image. That is, in section T1, the actual image is
Although unchanged, as shown in the figure, the last pixel 30 of the first line
1 and the next pixel 302 have opposite colors (white → black)
You. Also, several virtual pixels following the virtual change point (virtual pixel) 302
Is a virtual change so that it does not become a change point for the reasons described later.
A pixel of the same color as the point (virtual pixel) 302 is held.   Now, the coding line signal 122 in FIG.
Is an image signal to be encoded as shown in FIG.
Input to the dot detection circuit B107, and
Full memory A102 and line buffer memory B103
Is provided as write data.   On the other hand, the address counter 111 is only for the section T1 in FIG.
The image clock 134 is counted, as shown at 135 in FIG.
And outputs the same to memory address 135
As the line buffer memory A102 and the line buffer
Commonly applied to the toe memory B103.   Further, although not shown at this time, the line buffer
Memory A102 is in the write mode and the line buffer memory
Assuming that B103 is controlled to read mode, code
The data of Ing Line 122 is a line buffer memo.
In order of the address specified by memory address 135 in A102
Next is written. Also, line buffer memory B103
Is in read mode at this time, as described above.
If you write all “0” in the initial state,
"0" is sequentially read from the address specified by the dress 135, and
The read signal B indicated by reference numeral 124 in FIG.
Is selected and becomes the data of the reference line 125.
You.   Reference numeral 125 in FIG. 3 indicates a data signal of the reference line.
The waveform is shown and is “0” during the section T1. this
Means that, as shown in FIG.
What I got on the circuit as a “white” reference line
You.   The coding line 122 is used for detecting the change point as described above.
It is also given to road B107. The detection circuit B107 receives the given data.
Change point (pixel) in the data input is detected and the change point pixel
Is output as “1”, and all pixels that do not
Output as "0". Reference numeral 128 in FIG. 1 is the output.   The virtual change point generation circuit B105 and the change point detection circuit A106
Of the coding line 122 described above.
Operation of circuits 101 and 107 with the same name
Reference line 12 read from buffer memory
Execute for 5.   After all, the signal on the reference line 125 generates a virtual change point
The circuit B105 provides the next pixel after the last pixel as indicated by 126 in FIG.
Converted to a signal with virtual pixels of a different color from the end pixel
It is.   The signal 128 generated from the change point detection circuit B107 is
The data is sequentially shifted into the A register 108 by the clock 134.
Symbols A1 to A4 of the A register 108 are parallel
It shows a simple 4-bit output, which is always output.
The output signal waveform of the A register 108 is shown in FIG.
It shows in 9-4. Therefore, the target pixel of the coding line
Is shifted to the output A4 of the A register 108,
Whether there is a change point in the data of three pixels following the pixel of interest
Can be determined from the output 129.   Similarly, 130-1 to 130-4 in FIG. 3 and 131- in FIG.
Output of B register 109 and C register 110 to 1-131-4
3 shows a signal waveform. That is, the B register 109 and the C register 1
In FIG. 10, each pixel position stored in the A register 108 is
Change point signal and color of the corresponding reference line pixel
The signal is stored. Therefore, the output A of the A register 108
If 4 is the pixel of interest for the coding line,
The reference line by the data register 109 and the C register 110.
Whether there is a change point in three pixels following the target pixel position in
No and its color can be determined.   In order to encode the second line, the second line 403 in FIG.
Is input as the image signal 121, the line buffer
Memory B103 enters the write mode and the line buffer
The memory A102 enters the read mode. That is, the first la
Line buffer memory B during coding operation of IN 402
The first line 402 written in 103 is the reference line
And the second line 403 to be newly input is
It becomes. Then, the same operation as in the first line
The operation is performed.   Each signal waveform in the second line 403 is shown in section T2 in FIG.
Shown in At this time, the section T2 of the reference line 125
Data is written to line buffer memory A102 during section T1.
The data of the first line 402
is there.   The above is the specific operation of the circuit block shown in FIG.   Next, the circuit block shown in FIG. 2 will be described.   201 is a symbol detection circuit, as shown in FIG.
Signals 129, 130, 131 from the A, B, C registers of the circuit block
Then, in the MMR coding method, the necessary symbol a₀, A₁, A_TwoPassing
B₁, B_TwoIt is a circuit for detecting symbols such as. These notes
The definition of the number is as follows. a₀= Image on coding line that is the starting point of encoding
Elementary. a₁= A₀First change on the coding line to the right
Inversion point (pixel). a_Two= A₁First change on the coding line to the right
Inversion point (pixel). b₁= A₀Transition point on the reference line to the right
(Pixel) at a₀The opposite color and the first change point. b_Two= B₁First change on the reference line to the right
Inversion point (pixel).   However, the right here refers to, for example, each pixel shown in FIG.
Same as the relationship between left and right.   Next, reference numeral 202 denotes a B 'register, which is indicated by 222 in FIG.
Change point signal b₁With clock 134 as input data.
3-bit shift register shifted in sequentially
It is. Therefore, the change detected by the symbol detection circuit 201
Point signal b₁Is maintained for the next three clock periods
Change point signal b for pixel₁Can be determined.   203 is a run-length counter, usually a pixel a₀
From pixel a₁Number of pixels up to (run length) or pixel a₁Or
Pixel a_TwoA binary counter that counts the number of pixels up to
It has a 12-bit output and counts up to 2559 decimal.
Counter that can be   The signal indicated by 228 in FIG.
Are the lower 6 bits of the count value output. Also, the second
The signal indicated by 227 in the figure is the count of the run-length counter 203.
This is the upper 6 bits of the event value output.   Reference numeral 204 denotes a ROM table A, which is mainly in a bus mode.
(P mode) code and vertical mode (V mode) code
Stores codes and the number of bits (code length) of each code
The code and the code according to the input provided.
ROM (read only memory) that can output lengths in parallel
You.   Reference numeral 205 denotes a ROM table B, which is mainly a horizontal mode.
(H mode) make-up code and code length
Is stored in the ROM, and the signal 227 is output as an address.
The code to be input and the code length are selectively output.   Reference numeral 206 denotes a ROM table C.
RO that stores the mining code and code length
M and the code and signal to output signal 228 as address
And the code length are selected and output.   207 and 208 indicate the make-up output from each ROM.
A latch circuit for temporarily storing a loop code and a code length.
You. Reference numeral 209 denotes the termination output from the ROM.
Latch circuit that temporarily stores the running code and code length
is there.   210 indicates the code and code length in the latch circuit C209 sequentially.
This is a buffer memory for receiving and temporarily storing.   Here, the coding rules of the MMR method are described a little more.
Good. Symbols defined as above in this encoding method
a₀, A₁, A_TwoIs on the coding line and is the same
Symbol b₁And b_TwoIs on the reference line. Soshi
And each of these symbols a₀, A₁, A_TwoGroups and b₁, B_TwoNo
Depending on the relative position (distance) of the loop, the encoding mode
Uniquely select from three modes and encode
Stipulated. (1) Pass mode (P mode) b_TwoIs a₁When to the left (only one occurrence code) (2) Vertical mode (V mode) ｜ a₁b₁When | ≦ 3 (7 different codes are generated for each distance)
Occurrence code) (3) Horizontal mode (H mode) Other than (1) and (2) above (Run length code table
Obey) Format: H + M (a₀a₁) + M (a₁a_Two)   Here, H is a code indicating the H mode, and M (a₀a₁) Is white
Or black | a₀a₁| Run-length code, M (a₁a_Two)
Is black or white | a₁a_Two| Is the run-length code. However, two or more modes among the above (1), (2) and (3)
Are satisfied at the same time, (1) P mode> (2) V mode> (3) H mode Takes priority. The code output circuit 212 controls the priority output operation.
The latch is selected by the code determination circuit 212.
You.   Next, the operation of encoding the image 402 of the first line in FIG.
Explain the work.   First, in the present embodiment, at time t shown at 320 in FIG.₀To
This is the encoding start time.   That is, time t₀Is Reference Line and Cordine
The first pixel of the line is the C4 output of the C register 110 in FIG.
The time at which they appear at the output or A4 output of the A register 108, respectively.
You. That is, time t₀Then, C register 110, B register 109
And each output of the A register 108 is a reference line and
And the first pixel of the coding line
The three pixel states are output in parallel. Also, a₀In Figure 3
221 A0 (a₀), The initial value “0” (white pixel = temporary)
).   The run-length counter 203 counts from the initial value 0 to time t.₀Less than
The counting of the descending image clock 134 is started.   The count value output at each time of the counter 203 is set to the third
This is shown at 322 in the figure.   Time t₀In this case, "1" is set to the signal 129-4 in FIG.
The A shift register 108 of FIG.
4 There is no change point in the output, and similarly, the B shift register 109
B4 output has no change point. Therefore, generate the code
Since there is no cause, the count value of the run-length counter
Only by one, the next time t₁Go to time t₁But when
Time t₀This is the same as the state described above.   Then at time t_TwoGoes to "1" in signal 129-4 in FIG.
Are standing. This means that A4 of the A register 108 in FIG.
The output becomes 1 and changes to that position on the coding line
Indicates that a point exists. This change point is the current starting point a₀
To the right (the time corresponds to a later time)
Therefore, the symbol detection circuit 201 shown in FIG.₁In
Is determined. Note that this symbol a₁The detection status of Fa₁age
To remember.   This time t_TwoAt 130-1 to 130-4 in FIG.
Then, "1" does not stand in any of them. This is at time t_Two
Change point b within 3 hours from₁Means that there is no or,
Symbol detection circuit 201 is b₁B is detected when₁To B '
Shift register 202 and disappear for 3 hours
I try not to. The symbol detection circuit 201 is b₁Already
Also, there is a circuit for storing the detection.   Thus, in this case, the change point pixel a₁Left and right 3 strokes
Change point pixel b within the element₁Is missing and origin a₀From a₁For up to
Between b₁That there is no_TwoCan also be determined.
Therefore, at time t_TwoIn a₁Is detected, but in P mode (b_TwoAlready
And V mode (| a₁
b₁| 3 is not satisfied), and therefore
H mode is set.   At this time, the value of the run length counter 203 is
As also shown in a₀From a₁Is "2".
The run-length color remains the same as the initial setting “0” = white
is there. Therefore, the output 228 of the run length counter 203, etc.
More run length values and colors are given to ROM table C206.
And the corresponding code and code length are output from ROM 206.
Is done. In this case, the code for “White Run 2” is output
You. That is, M (a₀a₁) = White 2.   At this time, it is determined that this is the first code in the H mode,
The code “001” indicating the mode is changed to the code “0111” of the white run 2
At the same time, control is performed so as to output in one clock. Also code
The length is also output simultaneously as a binary number.   Next, the run-length counter 203 is initialized to 1 (0
Note that there is no₁From pixel a_Twoof
Move on to counting. Where pixel a₁I.e., time t_TwoIn the initial value
Just prepare for setting and the counter will be set to the initial value.
The next time t_ThreeBecause. Also this
Time t_ThreeThe color of A0 is also inverted. (Time t_Two= “0” → hour
Time t_Three= "1"), after which time t_nTime t_FourIn
As a result, the A4 output of the A register 108 becomes “1” and the transition point appears.
It is. The change point is detected by the symbol detection circuit 201 as a change point a.₁Already
It remembers that it passed and was detected (Fa₁= 1
The symbol detection circuit 201_TwoIs determined
You. In addition, this a_TwoDetection status is Fa_TwoIs stored as Sa
And time t_FourAnd the value of the run-length counter 203 is 2.
A0 = “1” = black. Time t_TwoAt
Since it is determined that the mode is H, a_TwoDetected
Sometimes the state of the reference line, ie, 13 in FIG.
References to 1-1 to 131-4 and FIG.
It is unnecessary and not in this case.
B on the line₁, B_TwoIs controlled to ignore any
It is.   After all, M (a₀, A₁), M (a₁, A_Two) = Black “2” code and code length are output
You. In this case, M (a₀, A₁H mode is different from the case of
The code "001" is controlled not to be added.   Then, at time t_FourAfter, that is, time t_FiveRun length with
The counter 203 is set to an initial value of 1. A0
(= A₀) Is inverted. And time t_FourChange point a_TwoIs the next
Mode origin a₀Is considered.   By the above operation, generation by the encoding of the first line 402
The code is as shown at 501 in FIG.   The time t in FIG.₃₀So, the run-length counter
The value is 9, where the symbol a ″₁(= A₁) Is detected
Changes point b ″ two pixels after the reference line₁Has
Time t₃₀At the output of the B register 109 in FIG.
130-2 and the output 131-2 of the C register 110, etc.
It is. Therefore | a₁b₁| 3 condition is satisfied, P mode
(B_TwoIs necessary), so it is determined to be V mode by definition
V_L(2) Code (a₁Is b₁At the position of two pixels to the left of
Is output.   At this time, the H mode run-length white 9 code
Although it was in a state where it could be produced,
V-mode is a valid code according to the definition of priority between
Therefore, the H mode code becomes invalid. In addition, V mode
The run-length counter 203
At the time t₃₀The count value until is cleared and newly
It is controlled so that it is reset to 1. Also, V mode
Start code a after the code₀The symbol color is inverted
You. (However, generation of V mode code is a₁Change point of symbol
Same time as detection (time t₃₀). )   Although not described so far, the symbol b₁Is the symbol a₁
If it is detected earlier, the symbol b₁Detection signal is B '
As an input signal to the register 202, a shift into the register is performed.
The output of the B 'register 202, B
Shifts in the order of 5 → B6 → B7, then disappears.
Also, the symbol b₁Already passed the B4 output of B register 109
When no code is generated yet, the fact is memorized and detected.
Output Fb of road 201₁Is stored as shown in FIG.   Next, each function block of the circuit block shown in FIG.
A specific circuit will be described.   The virtual change point generation circuit A101 of FIG.
The raw circuit B105 is a circuit of the same type, and both are virtual circuits shown in FIG.
This is realized by a change point generation circuit. In the figure, 702 is frits
Flop, 703-1 and 703-4 are AND gates, 704
Is an OR gate, and 705 is an inverting circuit (inverter).
The operation of the circuit shown in FIG. 7 is applied to the timing chart of FIG.
Show. That is, the numbers of the respective parts in FIG. 7 and FIG.
And the numbers in FIG. However, FIGS. 7 and 8
The signal indicated by 701 in the figure is, for example, the memory address shown in FIG.
By decoding the count value of the
Shows the position (timing) of the last pixel of one line obtained
Signal. That is, the flip-flop occurs at the time when the signal 701 is generated.
Make 702 the same color as the last pixel of the coding line
Set in synchronization with clock 134, and after that time, ie,
After the horizontal synchronizing signal 136-2 is deactivated, the flip-flop 702
Of the horizontal synchronization signal before the time, that is, the horizontal synchronization signal
During output of signal 136-2, the image 121 is output as a 122 signal.
It is something.   1 is realized by the circuit shown in FIG.
Is done. In the figure, 902-1 and 902-2 are AND gates, 90
3 is an OR gate, and 904 is an inverter. In FIG. 9, 123,
Reference numeral 124 denotes outputs 123 and 124 of the line buffer memories A and B in FIG.
However, the signal 901 in FIG. 9 is recorded every line of the image.
The select signal with inverted bell, the horizontal sync signal shown in FIG.
136-2. The select signal 901 causes a signal
Switch output to 125.   The change point detection circuit A106 and the change point detection circuit B107 in FIG.
Is a circuit of the same type, and FIG.
The configuration is shown as a representative. In the figure, 1002 is a flip-flop,
1003 is an exclusive OR gate, and 1004 is an inverter.   That is, as shown in the timing chart of FIG.
Input of flip-flop 1002 synchronized with lock 134
Next by taking the exclusive OR of the output
It detects that the colors of the pixels that match each other are different and generates a change point signal.
ing.   Next, the specific function blocks in the circuit block shown in FIG.
The circuit will be described.   Figure 11 shows the symbol a on the above-mentioned coding line.₁Or
a_TwoAnd a mentioned above₁Fa indicating that has been detected₁Faith
Signal detection circuit 201 in the symbol detection circuit 201 shown in FIG.
You. In the figure, reference numeral 1102 denotes a flip-flop, 1104-1 and 1104
-2 is an AND gate, and 1105 is an inverter.   By the way, the numbers of each part in FIG. 11 are the numbers in FIG. 1 and the like.
It matches. The signal indicated by 1101 in FIG. 11 is a flip-flop.
Returning the rope 1102 to the initial state (that is, the Q output = "0");
Q output is a control signal that inhibits the output from being set to "1".
Normally, it is at the level of “1”. ▲ ▼ Shin
No. 1103 is similar. Here, change point A4 (129-4)
A4 = "1" when the first signal arrives. in this case,
Output of flip-flop 1102 = "1" and control signal 1101
= “1”, so a₁= “1” is output and the symbol a₁Is detected
Is done. This a₁The flip-flop 1102 is activated by the detection signal.
Set and the Q output becomes "1".₁Has already been detected
(That is, Q output = Fa₁= “1”). Next in this state
A when A4 = "1"_Two= "1" and the symbol a_TwoIs detected
You.   Next, the symbol b₁FIG. 12 shows a circuit for detecting the like.
In the figure, 1201 is an exclusive OR gate, 1202 and 1203 are flips
Flops, 1204-1 and 1204-2 are AND gates, 1205
Is an inverter. The sign of each part number is as shown in Fig. 11.
Is the same as Where b₁Can be a₀And the opposite color
Reference line with exclusive OR gate 1201
Change and a₀The signal after taking the exclusive OR with the signal
The circuit to be used. The circuit shown in FIG.
It is included in the symbol detection circuit 201 shown in FIG.   The specific configuration of the run length counter 203 shown in FIG.
See Figure 3. First, the run-length counter 203 is described above.
As shown, the counter is a 12-bit binary counter.
The counting range of the counter 203 is from 0 (decimal) to 2560-1 (decimal number).
2559). The counter 203 has a preset function.
And has a clear function, etc.
IC made by Fair Child, Inc., composed of 74F163, etc.
Can be done.   Further, the count value output of the counter 203 is a decimal number 2559.
And a circuit 1301 for generating an MK1 signal
The decoded value of the lower 6 bits of the output is decimal "63".
It has a circuit 1302 that detects something and generates an MK2 signal
I have.   Furthermore, “0” is set as the value to be set by the preset function.
(Decimal) or “1” (decimal) can be selectively preset
It has a clear structure.   The following describes how the run-length counter 203 operates.
You. First, the position outside the left edge of the image for each coding line
Preset (or cleared) to the initial value “0”
You. Next, counting is performed sequentially for each pixel in the image area.
However, the counter 203 is not
It is returned to "1" by the set function. That is, (1) Change point a₁Or a_TwoWhen is detected, (2) When the count value reaches 2559, (3) P-mode code or V-mode code occurs
When However, due to the rules of the coding method, the coding line
Change point a on virtual pixel outside right end₁A_TwoIf a₁
The counter value is returned to "0" upon detection of.   Next, the configuration of the ROM table A204 shown in FIG. 2 will be described.
You. The ROM table A204 has 8 types of P mode and V mode.
And the code length and the like.
The configuration described here is based on the configuration principle of the present embodiment and the above description.
As is clear, the coding line and
The relative position of the change point of the
Change point b on the lens line_TwoIs B4 output of B register 109
At the point of change or on the coding line₁
Appears as the A4 output of the A register 108,
The state of the symbol detection circuit 201 and the A register 108 and B register
Each output of the register 109, C register 110 and B 'register 202
It is configured to be able to judge the state of force etc. at the same time in parallel
You. Therefore, the combination of the above output states is of course finite.
At the time to be judged,
I can. Therefore, P mode or V to be output for each combination
Mode code and code length can be determined.
It can be configured as a table. Here is the ROM
Since the specific contents of the table are too verbose,
As an example, a logic circuit equivalent to ROM shown in FIG.
Code code and code length are generated as examples.
Good. In the figure, 1409-1 to 1409-3 are inverters and 1410-1
1410-6 is a timing circuit, 1411 is a NAND gate, 14
12 is a NOR gate. That is, the signal indicated by 1401 in FIG.
In the symbol detection circuit 201 shown in FIG.
Change point b_TwoIs a signal indicating that is detected.   That is, the b4 output of the B register 109 in FIG._TwoStrange as
It means that there is an inflection point. Also, 1402 in FIG.
A₁The signal is similarly supplied to A4 of the A register 108 in FIG.
A as output₁It is a turning point. Fa indicated by 1403 in FIG.
₁The signal is already detected by the symbol detection circuit 201 in FIG.
To a₁Is a signal indicating that the change point as
You.   The logic circuit of FIG._TwoAt the time of detection of
a₁Or Fa₁P mode due to signal not being "true"
Is determined. That is, starting point a₀Hereafter, b_TwoBut
A by the time of detection₁It means that there is no change point. Immediately
In the image, the origin a₀From b_TwoJust below the point of change
a₁There will be no change. Therefore, by definition, P-mode
Becomes In FIG. 14, 1404 is a P mode detection signal, and 1405 is a P mode detection signal.
1406 is the code of the P-mode code.
This is a binary number that represents the length of the command. Also, 1407 has P mode code
This is a signal indicating that an event has occurred. As described above, the determination method of the P mode
However, the same method can be applied to the V mode. The hand
The ROM table A204 is configured by the method.   After all, the code and code length of P mode or V mode are before
Note b_TwoOr a₁At the time the symbol is detected,
Figure 2 ROM table A204 based on the above registers
Instantaneously by giving the status signal of
Generated in lock time.   ROM table B205 and ROM table C206 in FIG. 2 are the same.
Because of the structure shown in FIG. 15 and FIG.
The M table C206 will be described.   First, 206 is a ROM with at least 11-bit address input
And 21 bits of parallel output, and 228 inputs are second
This corresponds to the signal 228 in the figure. That is, the run length of FIG.
The lower 6 bits of the counter 203. In addition, 150 in FIG.
2 Input is a signal to specify the run length color, and symbol detection
This is an a0 signal output from the circuit 201. In this example, white = 0 and black =
Let it be 1. The 1503 input is a code indicating the H mode (= 00
1) Add a symbol or specify whether the symbol is unnecessary.
This is the Fa1 signal output from the circuit 201. In this example, necessary = 1, unnecessary
= 0. In other words, if the 1503 input is 1, the H mode
Code (001) as the first run length code
Is output in one clock. 1504 is the
Output of the ROM table C206 in accordance with the output of the
Chipine to control whether force is enabled or disabled
Bull signal. 1507 input is EOL, 1508 input is EOL + 1,
1509 input is the address that controls each reading of EOL + 0
Input, and by inputting a pulse to these inputs
Thus, the corresponding line delimiter code is read. or,
1505 is the code output of the address specified by the input and 1506 is the code output
Similarly, it is the code length of the code.   FIG. 16 shows the addresses A0 to A10 of FIG.
FIG.   The code determination circuit 212 of FIG.
explain. In the figure, 1706-1 to 1706-3 are AND gates,
Reference numerals 1707-1 and 1701-2 denote inverters. 1407 is the 14th
P mode code from ROM table A204 shown
Signals 1702 and 1703, respectively.
Signal indicating generation of V-mode code and H-mode code
It is.   As can be seen from the principle of the code generation method in this embodiment.
The ROM tables 204 and 205 or 206 shown in FIG.
Each code of P mode, V mode and H mode is finally
Before the code to be generated
May be output from the ROM table. I
However, two or more codes have priority defined as described above.
ing. Figure 17 must be generated uniquely according to the definition
This is a circuit for determining the code.   That is, the P mode, V mode and H mode codes are
In this case, AND gates 1706-1 to 1706-
3 and 1707-1, 1707-2
As mentioned above, P mode> V mode> H mode Depending on the order, one of the outputs 1701, 1704, and 1705 becomes 1.
The code of the mode in which the priority was
Is determined as the power code, and the other mode code is invalid.
Is not generated code.   Note that the signal 1708 indicates that the present encoding circuit uses the MH method,
Whether to use for coding or two-dimensional coding of MMR or MR
Mode signal for selecting
L level to execute, on the other hand, execute two-dimensional encoding
In this case, the level becomes H level.   Therefore, when performing one-dimensional encoding, the P mode
Code and V mode code are prevented, and the H mode
Only code that indicates run length is valid
It is said.   Next, the role of the latch A207 and the latch B208 in FIG.
I will talk about it. Latch A207 and Latch B208 are codeine
H mode make-up code and
And whether the H mode is enabled or disabled.
This is a circuit for temporarily storing until it is determined. And
If the H mode is determined to be valid, the contents of the latch will be
Delivered to the road.   The operation of the latches A207 and B208 in FIG.
Has a long run length at which a make-up code occurs
In this case, for example, the description will be made with a run length of 2972. This time,
According to the coding rules, two make-up code
Code and one terminating code for a total of three
It is split into length codes and output. That is, (1) Makeup code 1 =   Run-length 2560 code (common for white and black) (2) Makeup code 2 =   Run length 384 cord (white or black) (3) Terminating code =   Run length 28 cord (white or black) In this way, multiple codes like 2560 + 384 + 28 = 2972
To represent one more run length, first the second
The count value of the run-length counter 203 in the figure is 63 + 64
× N (positive integer of N = 0,1,2 ...) at that time
And the A4 output of the A register is a₁If it is not a change point,
Foreseeing that a capture value will occur,
The value of the upper 6 bits (corresponding to N) indicates one higher (that is, N =
0 to 64 make-up codes)
Data length from ROM table B205, and
Remember the time. Next, the previous count value advances by 64.
Every (that is, every time N advances by 1 in the above-mentioned formula of 63 + 64 × N)
Then, the contents of the latch B208 are updated.   Then, the value of the run-length counter 203 becomes 2559 (immediately).
Change point a at the time when N = 39 in the formula of 63 + 64 × N₁But
If not detected, the run length currently being counted is
It can be predicted that it will be 2560 or more.
Code B205 to run length 2560 code and code length
Is read out and temporarily stored in the latch A 207. Also at the same time
The stored contents of the latch B208 are temporarily invalidated. Also, runle
The count value of the pitch counter 203 is returned to the initial value 1.
You. Then, as the count goes on, 63 + 64 ×
Make up code for latch B208, etc. in the same way for each formula of N
Is resumed.   And the change point a₁Is detected, another P mode or
The competition with the V mode is determined, and the H mode is determined.
And the change point a₁Run length counter 203 at time
Run length indicated by lower 6-bit value (0 to 63)
ROM-terminated terminating code and code length
Is temporarily stored in the latch C209 via the file C206. Also already
As described above, the contents stored in Latch A 207 and Latch B 208
Becomes effective.   However, change point a₁If V mode etc. occur at the time of
The H mode itself will not occur, and naturally the latch A207 and
And the contents of the latch B208 are invalidated, and the ROM table C206
Is disabled by the chip enable signal 1504,
Latch C209 is replaced with the terminating code
V-mode from ROM table A204 via OR gate 231
The code is latched as a valid code.   Above make-up code 1 and make-up code
FIG. 18 shows a circuit for controlling generation and storage of 2 etc.
Are included in the timing circuit 112. This circuit
Timing chart (run length is 2972
Is shown in FIG. In the figure, 1801 and 1802 are
Lip flop, 1803 AND gate, 1804 Invar
It is.   MK1 and MK2 are the run-length counters 20 shown in FIG.
3 from 2559 detection circuit 1301 and 63 detection circuit 1302 respectively
This is the output signal. Flip flop 1802 is MK2 signal
Signal is set and the MK2 signal is generated.
The flip-flop 1801 is set by the input of the MK1 signal and
Generates K1 signal. It should be noted that, due to the input of the MK1 signal,
The flop 1802 is reset.   With the above configuration, the run length counter 203
MK2 signal is high when the count value of
Level, and if it becomes 2560 or more, MK1 signal
Only the MK1 existence signal and the MK2 existence signal both become high level.
The run length depends on the level of the MK1 signal and the MK2 signal.
Is the only terminating code
Or the terminating code and make-up code
Combination and the number of make-up codes is 1
Or 2 can be determined. Therefore, in H mode
The MK1 signal and MK2 signal
The packing circuit 211 determines the level of the signal and the three levels.
Select a valid one of latches A, B, and C, and
Capture data.   In this way, at least in the generation of make-up codes
Also predicts the occurrence of the code one hour before and temporarily stores the code.
By sending it to the memory circuit (Latch A, B)
Change point a₁Output code to be processed at the same time when
Has the effect of preventing an increase in the number of bits and the number of bits.
Extremely effective.   That is, run-length cowling to Latch A207 and Latch B208
Required by the counter 203 before the H mode was determined
And temporarily store the make-up code and code length
By setting, when H mode is decided,
Since only the code and code length need to be processed, a₁Inspection
All H mode codes to be output at the time of
The decoding operation can be performed without delay.   Send the contents of latches A, B and C of 207, 208 and 209 to the next circuit.
The order of delivery is Latch A207> Latch B208> Latch C209 (210
(Buffer) is controlled so as not to break the order (contents are invalid)
Omit and ignore when.)   The contents of the latch C209 are temporarily stored in the buffer memory 210.
The next code is determined from the next time when the encoding mode is determined.
The encoding operation starts and the next encoded data is read from the ROM table.
Is input to the latch C209 with a few clocks (minimum 1 clock).
May be Therefore, after the mode is determined, the next encoding
The contents of the latch C209 are buffered so that data can be latched.
Sent to memory 210, timing from buffer memory 210
And output to the subsequent stage.   Next, change point a₁And change point a_TwoAccording to the encoding method,
Describe special cases such as setting on the same pixel.
You.   FIG. 20 illustrates the above case. That is,
In Fig. 20, 2001 is the reference line, and 2002 is the reference line.
It is a decoding line. Also, 2003 is a coding line
The last pixel of the image, 2004, is a virtual change point (pixel).   Now, in FIG. 20, the encoding result from the left
a₀Is the position shown in the figure.
Is as shown in Fig. 21 [H mode code + white 12 terminator
Ing code + black 0 terminating code]. here
Then, the code in FIG.₁At the time
There is no problem because it can be treated as one code by means.
However, the code in FIG._TwoIs the changing point
a₁When it comes to another time, change point a_TwoOccurs at time
Code to be done. However, in this case,
Change point a_TwoIs not detected from the symbol detection circuit 201 or the like.   Therefore, in the case of this case, the second
The following processing is performed by the circuit shown in FIG. Fig. 23 shows this circuit
This is an operation timing chart. 2201 in Fig. 22
Is a signal indicating that the image has entered the virtual area (horizontal synchronization signal).
Signal 2202) a₁Change point detection signal, 2203 is H mode
The first terminating code is generated.
Is a signal indicated by. Monitor the above signal and AND gate
By taking the logical product of the 2201 to 2203 signals by 2207
20 is detected and a 2204-1 signal is generated (ie,
Time is a₁First, the code shown in Fig. 20 (1)
Output. Next, the run-length counter is cleared to 0.
22. The signal 20204-1 shown in FIG.
Delay one time by a delay circuit 2208 composed of a lip flop
The terminator of black 0 in FIG.
Generate a code.   The packing circuit 211 of FIG. 2 is obtained by the method described above.
The entered code and code length are input (in this case,
Each generated code length (number of code bits) is constant
Not in. However, the longest is H mode code (= 001)
Even 16 bits), and sequentially grouped in 16-bit units
In this embodiment, the circuit is connected to the next external circuit every 16 bits.
They are delivered in parallel.   The signal indicated by 238 in FIG.
This is a code summarized in bits.
This is a signal for notifying the fact to the external circuit of the next stage. In addition,
The tucking circuit 211 is a code length adding circuit, a bit shifter,
Combining known circuits such as multiplexers and latches
It can be realized more easily.   Next, RTC (Return To Control) indicating the end of one page
The signal will be described. RTC code = EOL code for MMR method
X 2 times. That is, the RTC signal is (000000000001) × 2
= 000000000001,000000000001. In addition
In the example, 16 clocks per clock time as described above.
It has a structure that can output even bit codes. Follow
In order to output the RTC signal, the vertical synchronization signal 136 shown in FIG.
By monitoring 1 etc., the end of 1 page is detected and 2
A pulse of clock time (2 times) is generated and this pulse
Address of the ROM table C206 (shown in FIG. 15).
By giving it as number 1507, it corresponds to the ROM table
Write the EOL code and code length in the address
If possible, add the RTC code
You can get it.   Next, Table 1 lists the differences between the above three encoding methods.
Keep it.   Therefore, the coding method of the MH method uses
It is almost the same as when repeating, but differs in the following points
You. That is (1) H mode code (001) is not required for MH method (2) White run and black run need not be paired in MH method (3) In the MH method, insert an EOL code for each line (4) Difference of RTC In the case of MR method (1) One-dimensional line is the same as MH method (2) Two-dimensional line is the same as MMR method (3) Line break EOL + 1 = 0000000000011   Or EOL + 1 = 0000000000010 (4) Difference of RTC (5) One-dimensional line and two-dimensional line by K parameter
Are mixed.   After all, the switching between the three encoding methods is the same as the MMR method described above.
Circuit operation controlled by MR or MH method selection signal
Can be easily realized.   First of all, Fig. 24 controls the differences between lines, breaks and codes.
An example of a circuit is shown below. In the figure, 2407 is a line counter, 2408 is
NAND gate, 249-1 to 2409-3 are AND gate, 24
10 is an inverter. That is, 2401 in FIG.
The pulse signal at time t-1 shown at 320
It is repeated for each line.
Accompanying, no code is generated. This pulse at time t-1
The signal is to decode the value of the address counter 111.
Get more. Also, 2402 and 2403 are CPUs that specify the encoding method.
Etc. are encoding method selection signals from outside the circuit of this embodiment. or
The 136-2 signal corresponds to the 136-2 signal in FIG.
The K-base counter 2407 indicates how the K parameter of the MR method advances.
The signal 136-2 is counted and monitored as a line counter.
To watch.   The signals 2404 to 2406 obtained by the logic of FIG.
Input of the ROM table C206 (1507 to 150 in FIG. 15)
8 input) and none, none to specify a specific address,
Code and code length required for the specific address are stored
Output the desired line / division
Get the cut and code.   Also, the encoding method of the one-dimensional line of the MH method is described in FIG.
H mode always takes precedence in the MMR method mode decision circuit
It may be controlled by the selection signal 1708 so that it can be performed.   In the MH method, the H mode code (001) is always
This is controlled as required, but this is also the same as the ROM table C206
This is achieved by setting the address signal A7 of FIG.   Also, the difference in the number of EOLs in RTC is
By changing the number of applied pulses according to the mode,
Achieve.   In this embodiment, as shown in FIG.
Works synchronously with clock 134, but with clock intervals
It has nothing to do with (cycle). Therefore, as shown in FIG.
For example, the clock 134 is masked by an image gate signal.
Pauses between images or lines easily
I can do it.   That is, in FIG. 25, reference numeral 2501 denotes an image gate signal, which is at the “0” level.
This signal indicates that the operation is suspended during the operation. Also 2502
Is the logical product of the gate signal 2501 and the clock 134
It is a clock with a missing tooth, and the clock 2502
In place of the above-mentioned clock 134,
If this signal is sent to the road, this embodiment
The hatched area in Fig. 25 is clearly
It will stop.   With this pause control, for example, an image signal to be encoded
The output speed of the image signal from the source of the
Is not limited to Conversely, for example, an image source
Is an image file with a disc, etc.
Even if the image signal is output intermittently, the encoding
Channel intermittently performs the encoding operation in synchronization with the intermittent output.
You can do it. Therefore, the output source and sign of the image signal
A large amount of buffer memory etc.
Encoding the image signal from the output source without need
Can also.   26 and 27, reference is made to the circuit of this embodiment.
Describes how to provide images to be encoded in parallel format.
You. That is, 2601 in FIG. 26 inputs 8-bit parallel data.
And 2602 can be output as 1-bit serial data
This is a serial change shift register.   As shown in FIG. 27, an image signal to be encoded is an 8-bit image signal.
After loading the register 2601 as parallel data,
A series shift is performed by the check, and a series image as shown in FIG. 27 is displayed.
An image signal 2602 is obtained. Clock during the serial shift at the same time
A gate signal 27 that counts the number etc. and indicates the section of the actual data
Create 02. Also, clock 2702 corresponding to actual data
You can get it as well.   As described above, the signals as shown in FIG.
The format that can be encoded as described above in this embodiment by the method
Has become. The operation for parallel input of this image is Cpu etc.
This is extremely effective when images are given by
You.   In the above embodiment, the coding of MH, MR, MMR
Explained, but can be applied to other encoding methods
Not to mention. Also, the image signal to be encoded is a light from the original image.
Input from a device that reads electronically or a computer, etc.
Also, the encoded code was transmitted to a remote location via a transmission line, etc.
Or stored in an image file. As described above, the present invention
Although described based on the preferred embodiment, the present invention
The invention is not limited to the
It is needless to say that the modification and change of are possible. 〔effect〕   As described above, according to the present invention,
・ Huffman coding, modified lead coding or
Modified-mode lead coding
In an image signal encoding device that encodes an image signal,   Counting the number of pixels between changing points of the image signal of the coding line
The run-les included in the horizontal mode image code
First code generating means for generating an encoding code;
Between the image signal of the reference line and the image signal of the reference line
Based on the correlation monitoring results, pass mode and vertical mode
And second generating means for generating an image code of the code.
The coding mode to be executed is Modified Read Coding
Or modified-mode lead coding
In this case, both the first generating means and the second generating means are used.
To execute the encoding operation, while the encoding mode to be executed is
If the mode is Modified Huffman coding,
Coding control means for performing a coding operation using one generating means
And the RTC code indicating the end of one screen, and the separation of each line
The line break code indicating the
Coding, Modified Read coding and Modified coding
According to each of the Eyed Modified Eyed lead coding
It has a memory table that can be generated in multiple formats,
RTC code and line break in the format corresponding to the encoding mode
Code generation means for generating a code.
Ifif Huffman coding, modified lead
Encoding and Modified Lead Code
Encoding of image signals using three encoding modes
It can be executable.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are block diagrams showing the configuration of an encoding apparatus to which the present invention is applied, FIG. 3 is a timing chart showing an encoding operation, and FIGS. 6 is a diagram showing a relationship between a reference line and a coding line, FIG. 7 is a diagram showing a configuration example of a virtual change point generating circuit, and FIG.
9 is a timing chart showing the operation of the circuit shown, FIG. 9 is a diagram showing a configuration example of a selector, FIG. 10 is a diagram showing a configuration example of a change point detection circuit, and FIG. 11 and FIG. FIG. 13 shows a configuration example of a run-length counter, FIG. 14 shows a configuration example of an equivalent circuit of the ROM table A, and FIG. 15 shows a configuration example of a ROM table C. FIG. 16, FIG. 16 is a diagram showing an example of the contents of a ROM table C, FIG. 17 is a diagram showing an example of the configuration of a code determination circuit, FIG. FIG. 19 is a timing chart showing the operation of the circuit shown in FIG.
FIG. 20 is a diagram showing a relationship between a reference line and a coding line, FIG. 21 is a diagram showing an H mode code, FIG. 22 is a diagram showing a configuration example of a delay circuit at a virtual change point, and FIG.
FIG. 24 is a timing chart showing the operation of the circuit shown, FIG. 24 is a diagram showing a configuration example of a circuit for controlling generation of a line break code, FIG. 25 is a timing chart showing a pause control operation of the encoding operation, FIG. 26 Is a diagram showing a configuration example of a circuit for serially outputting the parallel input of the image signal, FIG. 27 is a timing chart showing the output state of the circuit shown in FIG. 26,
101 and 105 are virtual change point generation circuits, 106 and 107 are change point detection circuits, 108 to 110 are registers, 111 is an address counter, 201 is a symbol detection circuit, 203 is a run length counter,
207 to 209 are latches.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Shigeki Sakurai               3-30-2 Shimomaruko, Ota-ku, Tokyo               Inside Canon Inc. (72) Inventor Yukio Murata               3-30-2 Shimomaruko, Ota-ku, Tokyo               Inside Canon Inc. (72) Inventor Tatsuo Okano               3-30-2 Shimomaruko, Ota-ku, Tokyo               Inside Canon Inc.

Claims (1)

(57) [Claims] Modified Huffman coding, Modified lead coding or Modified
An image signal encoding apparatus for encoding an image signal by read encoding, comprising: an input unit that inputs an image signal of an encoding line; an image signal that has been encoded by a previous encoding operation; Buffer means for outputting as an image signal; detecting means for detecting a change point of the image signal of the coding line inputted from the input means; and counting means for counting the number of pixels between the change points detected by the detecting means. First generation means for generating a run-length code included in a horizontal mode image code based on the counting result of the counting means; an image signal of a coded line input by the input means and output from the buffer means Monitoring means for monitoring a correlation with respect to a change point with the image signal of the reference line to be detected; and A second generating means for generating a direct mode image code; and an output for outputting a horizontal mode run length code generated from the first generating means or a pass mode or vertical mode image code generated from the second generating means. When the encoding mode to be executed is the modified read encoding or the modified modified read encoding, the encoding is performed by using both the first generating means and the second generating means. If the encoding mode to be executed is Modified Huffman encoding, encoding control means for performing the encoding operation using the first generating means, and RTC indicating the end of one screen. The code and the line break code indicating the break of each line are written in Modified Huffman coding, Modified lead coding and Model It is provided with a memory table that can be generated in a plurality of formats corresponding to each of the Fed, Modified, and Read coding, and a code generation unit that generates an RTC code and a line delimiter code in a format corresponding to a coding mode. Characteristic image signal encoding device.