JPS6231262A - Two-dimensional coding device for picture signal - Google Patents

Abstract

PURPOSE:To shorten output time when plural codes are outputted and to execute the coding action without delay to the input picture signal by outputting the identifying code to show that the mode is the horizontal mode and the head coding code to be generated in succession to it, as the solid code. CONSTITUTION:A pass mode (P mode), a vertical mode (V mode) a horizontal mode (H mode) are preferred in the sequence of the P mode > the V mode > the H mode. The preferring output action is controlled by a code determining circuit 212, and the latch is selected. For example, when within three right and left picture elements of a changing point picture element a1, a changing point picture element b1 does not exist and the b1 does not exist from a starting point a0 to a1, the conditions of the P mode and the V mode are not satisfied and the H mode is obtained. The value of a run length counter 203 shows the number of the picture element '2' from the a0 to the a1, the color of the run length is '0' = white set initially, and this is outputted from a ROM206. At such a time, a code '0111' to show the H mode is controlled so that the code can be outputted simultaneously with a code '0111' of a white run 2, namely, by one clock. The code length is outputted simultaneously by the binary number, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a two-dimensional encoding device for image signals used for facsimiles, image electronic files, and the like.

[Prior art]

In conventional 7-axis T image transmission devices and recent image file devices using optical disks, magnetic disks, etc., image signals are encoded and handled to reduce the amount of data and speed up transmission or storage operations. We are trying to improve efficiency.

For example, in the field of facsimile, the modified Huffman (MH) method is generally used for dimensional encoding, the modified read (MR) method is used for two-dimensional encoding, and the modified modified read (MMR) method is used for high-efficiency two-dimensional encoding. ing.

Regarding the mutual relationship between these MH method, MR method, and MMR method, the MMR method includes methods that are very similar to the MH method,
Furthermore, the MMR method is an integrated modification of the MR method.

Furthermore, the image to be encoded and the rules for the encoding method are, in a nutshell, based on T4 and T6 recommended by the CCITT (Consultative Committee on International Telegraph and Telephone).

Furthermore, the above-mentioned encoding method was developed in March 1985 for the MMR method.
The MR method is announced as a high rate two-dimensional encoding method in the recommended communication method for facsimile group 4 type equipment (post office - Migami) on page 52 and below of the Official Gazette (extra issue No. 29) dated August 22nd. Both the MR method is used as a one-dimensional encoding method, and the MR method is used as a two-dimensional encoding method in accordance with the Ministry of Posts and Telecommunications Notification No. 1013 of 1982.
It is announced in the number.

In the two-dimensional encoding described above, the correlation between the image signal of the line to be encoded and the image signal of the previous line is determined,
The configuration is such that a mode encoding code is generated according to this correlation. Among these encoding code modes, in the horizontal mode, it is necessary to generate a code indicating the consecutive number of pixels of the same color (run length) together with an identification code indicating the water mode. Therefore, in the horizontal mode, multiple codes must be generated together, and if the run length is relatively long, the code length to be generated will be long. Therefore, it is possible to output multiple codes separately, but it takes time to generate multiple codes, which affects the next encoding and makes it impossible for the encoding operation to catch up with the input of the image signal to be encoded. There is.

[verbal]

The present invention was made in view of the above points, and the above-mentioned M
The purpose is to enable two-dimensional encoding such as R, MMR, etc. to be performed at high speed and without delay in inputting image signals to be encoded. means for serially capturing the image signal of the reference line in synchronization with the image signal of the encoded line, means for counting the number of pixels between changing points of the image signal of the encoded line, and correlation between the image signal of the encoded line and the image signal of the reference line. It has means for monitoring the relationship and determining the encoding mode, and means for generating an encoding code based on the count value of the counting means, and when the determining means determines the horizontal mode, the mode is the horizontal mode. The purpose of the present invention is to provide a two-dimensional encoding device for an image signal that outputs an identification code indicating this and the first encoding code to be generated by the first generation f stage as an integrated code.

〔Example〕

Examples of the configuration of an encoding circuit to which the present invention is applied are shown in Figures 1 and 2.
This is shown in the circuit block diagram in the figure. Next, the operation of this embodiment will be explained using FIG. 1, FIG. 2, FIG. 3 to FIG. 5, etc.

The signal indicated by 121 in FIG. 1 is an image signal to be encoded supplied from an external device such as an image scanner, an image file, or a computer.
(For example, 0° = white, 1'° = black pixel. The zero-order signal 136, which is a clock and has one clock per pixel, is a synchronization signal, and shows several types of synchronization signals indicating horizontal sections, vertical sections, etc. of the image signal 121.

That is, in this embodiment, the image signal 121 to be encoded is provided as a scanning image signal that is a serial image signal for each main scan, similar to a signal provided to a laser printer or the like.

Next, 101 is forcibly changed so that the next pixel (=virtual pixel) after the last pixel of the real image on the coding line (one line in the main scanning direction of the image to be encoded) is always the change point. This is a circuit that generates points, and is called a "virtual change point generation circuit A." However, the above-mentioned "virtual change point generation circuit A" has a structure that does not give any change to the actual image on the coding number.

102 is a line buffer memory A, and 103 is a line buffer memory B, each of which is a RAM (random access number memory) capable of independently writing or reading operations. It has a capacity (number of main scanning pixels) that can store a binary image.

Further, the line buffer memory Al 02 and the line buffer memory B 103 are controlled so that when one is executing a write operation, the other one is executing a read operation. That is, these two line buffer memories constitute a set of double buffer memories.

A memory address counter 111 is a counter that counts a clock 134 corresponding to the number of pixels of a coding line. The count value of the counter 111 is commonly given as a memory address signal 135 to both the line buffer φ memory AlO2 and the line buffer memory B102. Also, the memory address counter 111 returns to the initial value for each coding line and repeats the counting operation. Therefore, the binary image of each line written to the line 11/header memory is newly input. Each pixel is read out in correspondence with the pixel position of the image signal 121 of the line.

104 is a selector, which is a line working buffer memory A.
Of lO2 or line fist buffer memory B103,
This circuit operates selectively in response to a select signal 901 in order to obtain read data from whichever one is executing the read operation.

The data selectively obtained by this selector 104 is given to the next stage as a reference line 125, that is, as reference data (image) of the coding line.

105 is a circuit that forcibly creates a change point so that the last pixel of the real image on the reference line and the next pixel (virtual pixel) always become the change point, and is called "virtual change point generation circuit B".
”.

However, the virtual change point generating circuit B105 has a structure that does not give any change to the real image on the reference line.

Reference numeral 106 denotes a circuit that detects a pixel serving as a changing point on the real image and virtual pixel on the reference line, and is referred to as a "changing point detection circuit A."

Further, 107 is a circuit for detecting changing points on the real image and virtual pixels on the coding line, ``changing point detection circuit B''.
It is called.

108 is A register, 109 is B register, 110 is C
The signals shown at 126 are the signals representing the real image and the virtual pixels on the reference line, and the signals shown at 127 are the signals representing the real image and virtual pixels on the reference line. It is a change point signal on an image and a virtual pixel. The signal indicated at 128 is the coding signal.
These are the real image on the line and the change point signal on the virtual pixel.

A timing circuit 112 receives a clock 134 and a synchronization signal 136, and based on these, forms various timing signals 137 for timing the operation of each circuit block.

The operation of the circuit block of FIG. 1 described above will be explained by taking as an example a case where an actual image (image to be encoded) as shown in FIG. 4 is given and this is encoded by the MMR method.

First, for the sake of simplicity in the image shown in FIG. ) to create an extremely simple image that makes up one page.

To actually encode the first line shown at 402 in FIG. 4, the virtual line shown at 401 at 47 is used as a reference line, and the first line 402 is used as a coding contest line, as shown in FIG. .

When encoding the second line 403 in FIG. 4, the first line 402 in FIG. 4 is used as a reference line and the second line 403 is used as a coding line, as shown in FIG. 6.

Below, it is assumed that one page consists of main scanning of 3 or more lines,
Even if the third line, fourth line, -11111, etc. continue, if the relationship between the reference line and the coding line is sequentially lowered as described above, encoding will continue regardless of the number of sub-scanning lines. can.

FIG. 3 is a timing chart when the image illustrated in FIG. 4 is applied to the circuit block illustrated in FIG. 1.

In FIG. 3, a vertical synchronizing signal 136-1 indicates an image section in the sub-scanning direction, that is, an input period of one page of images. 136-2 is a horizontal synchronizing signal, which is an image section in the main scanning direction;
That is, it shows the input period of the image of Elaine. 134 is an image clock, 121 is an expression as a signal waveform of the image to be encoded illustrated in FIG. 4, and black pixel=°"1'°=
It is drawn as “H”, white pixel = “l OIT = l” Loo. That is, one section TI of the image shown in the third figure
The image is the real image of the first line 402 shown in the fourth figure to be encoded, and the image of section T2 is the real image of the second line 403 shown in the fourth figure to be encoded.

Furthermore, in an image printed on an actual paper surface, the virtual line 401 shown in the fourth figure corresponds to a so-called margin at the upper part of the paper surface, or outside the paper surface, and in the MMR method, It is specified that it is assumed to be an all-white line (all pixels in the line are white pixels). Therefore, the virtual line 401 shown in the fourth figure does not appear on the image signal 121 shown in the third figure.

FIG. 5 is a timing chart showing the encoding operation of the first line 402, and shows the relationship between the virtual line 401, which is a reference line, and the first line 402, which is coding.

First, when the image of the first line 402 shown in FIG. 5 is given to the virtual change point generation circuit A101, a virtual change point (virtual pixel) 302 is added as shown at 122 (coding fist line) in FIG. It becomes an image. That is, in the interval T1, the actual image remains unchanged, but as shown in the figure, the last pixel 301 of the first line and the next pixel 302 have contradictory colors (white→black). Also, virtual change point (virtual pixel) 302
The virtual several pixels following 302 are kept as pixels of the same color as the virtual change point (virtual pixel) 302 so that they do not become change points for reasons described later.

Now, the coding line signal 122 in FIG.
As shown in FIG. 1, is input to the change point detection circuit B107 as an image signal to be encoded, and is also given to the line buffer memory AlO2 and the line buffer memory B103 as data for writing.

On the other hand, the address counter 111 only uses the image clock in the interval TI in FIG. 34 and outputs a count value as shown at 135 in FIG.

Furthermore, at this time, although not shown, the line buffer memory AlO2 is controlled to write mode, and the line buffer φ memory B103 is controlled to read mode.
The data of the coding line 122 is sequentially written to the address indicated by the memory address 135 in the line group buffer number memory AlO2. Also, at this time, the line buffer good memory B 103 is in the read mode as described above, so if all "0's are written in the initial state," will be read from the i location specified by the memory address 135.
0''' are sequentially read out to become a read signal B shown at 124 in FIG.

Reference numeral 125 in FIG. 3 indicates the data signal waveform of the reference line, which is zero during the interval Tl. That is, as shown in FIG. 5, the virtual line 401 is obtained on the circuit as an all-white reference number line.

The coding line 122 is also provided to the change point detection circuit B107 as described above. The detection circuit B107 detects a change point (pixel) in the given data input, outputs the change point pixel as "1", and outputs all pixels that are not a change point as O°. 128 in FIG. 1 is the output.

Virtual change point generation circuit B105 and change point detection circuit A10
6, as its name suggests, is the coding line 1 mentioned above.
Circuits 101 and 107 with the same name that operate on 22
The following operations are performed on the reference line 125 read from the line buffer memory.

Eventually, the signal on the reference line 125 is converted by the virtual change point generating circuit B105 into a signal in which a virtual pixel of a color different from the last pixel is added next to the last pixel, as shown at 126 in FIG.

The signal 128 generated from the change point detection circuit B107 is sequentially shifted into the A register 108 by the clock 134. Symbols A1 to A4 of the A register 108 each indicate a parallel 4-bit output of the register, which is always output. The output signal waveforms of the A register 108 are shown at 129-1 to 129-4 in FIG.

Therefore, the pixel of interest on the coding line is A register 1.
If it is shifted to output A4 of 08, output 1 indicates whether there is a change point in the data for 3 pixels following that pixel of interest.
This can be determined based on 29.

Similarly, 130-1 to 130-4 in Figure 3 and 1 in Figure 3
31-1 to 131-4 show the output signal waveforms of the B register 109 and the C register lO, that is, the B register 10
The change point signal and color signal of the pixel of the reference line corresponding to each pixel position stored in the A register 108 are stored in the 9 and C registers 110. Therefore, if the output A4 of the A register 108 is the pixel of interest on the coding line, the B register 109 and the C register 1
10, it is possible to determine whether there is a change point within the three pixels following the target pixel position on the reference line and its color. In order to encode the second line, the second line 403 in FIG.
When input as the image signal 121, the line buffer memory AlO2 is in the write mode, and the line number buffer memory B103 is in the read mode. That is, the first line 40 written in the line buffer memory B103 during the coding operation of the first line 402
2 becomes the reference line, and the newly input second line 403 becomes the coding. Then, the same operation as in the first line is executed.

Each signal waveform on the second line 403 is shown in section T2 in FIG. At this time, the data of the section T2 of the reference line 126 is the data read from the first line 402 written in the line buffer Φ memory AlO2 during the section Tl.

The above is the specific operation of the circuit block shown in the first diagram.

Next, the circuit block shown in the second diagram will be explained.

201 is a symbol detection circuit, and as shown in the figure, signals 129,
I got 130,131.

In the MMR encoding method, the necessary symbol aO9at+'a
This is a circuit for detecting symbols such as 2, bl, b2, etc.

The definitions of these symbols are as follows.

aQ=pixel on the coding line that is the starting point for encoding.

al=first change point (pixel) on the coding line to the right of aQ.

a2=first change point (pixel) on the coding number line to the right of a1.

b1 = A changing point (pixel) on the reference line to the right of ao, the opposite color to aQ, and the first changing point.

b2 = first change point (pixel) on the reference line to the right of bl.

However, the right here means the same as the relationship between the left and right of each pixel shown in FIG. 4, for example.

Next, there is a B register 202, and the clock 134 receives the change point signal b1 shown at 222 in FIG. 2 as input data.
This is a 3-bit shift register that is sequentially shifted in by .

Therefore, the change point signal b detected by the symbol detection circuit 201
1 is held for a total of three clock periods, and the position of the change point signal b1 relative to the pixel of interest can be determined.

203 is a run length counter, which usually corresponds to the pixel a.
A binary counter that counts the number of pixels from Q to pixel a1 (run length) or from pixel a1 to pixel a2, and has a 12-bit output, with a maximum of 10iifi.
This is a counter that can count up to 2559.

The signal shown at 228 in FIG. 2 is the run length counter 2.
These are the lower 6 bits of the count value output of 03. or,
The signal shown at 227 in FIG. 2 is the run length counter 2.
These are the upper 6 bits of the count m output of 03.

204 is a ROM table A, which mainly contains codes for pass mode (P mode) and vertical mode (V mode).
A ROM (read only memory) that stores the codes and the number of bits (code length) of each code, and can output the codes and code lengths in parallel according to a given input.
It is.

Further, 205 is a ROM table B, which is a ROM that mainly stores make-up codes and code lengths for the horizontal mode (H mode), and selects the code and code length to be output using the signal 227 as an address. Output.

Reference numeral 206 denotes a ROM table C, which is a ROM that mainly stores H mode termination codes and code lengths, and selects and outputs the code and code length to be output using the signal 228 as an address.

207 and 208 are latch circuits that temporarily store the make-up code and code length output from each of the ROMs. Further, 209 is a latch circuit that temporarily stores the terminating code and code length output from the ROM.

210 is a buffer memory for sequentially receiving the code and code length in the latch circuit C209 and temporarily storing it.

Here, the encoding rules of the MMR method will be explained a little more. In this encoding method, the symbol a defined as described above
otal+a2 is on the coding Φ line, and
Similarly, symbols b1 and b2 are on the reference line. And each of these symbols ao, a1 . A2 group and bl.

Based on the relative position (distance fa) of the group b2, it is specified that the encoding mode is uniquely selected from the following three modes and encoding is performed.

(1) Pass mode (P mode) When b2 is to the left of al (there is only one generation code) (
2) Vertical mode (V mode) When lalbtl≦3 (A total of 7 types of generation codes differ depending on the distance) (3) Horizontal mode (H mode) At times other than (1) and (2) above (run/ (according to the length code table) Format: H+M(aoat)+M(ata2) where,
H is the code indicating H mode, M (ao a t) is the white or black Iaoa II run length code, M (a
xa2) is a black or white Iata21 run length φ code.

However, if two or more of the above modes (1), (2), and (3) are satisfied at the same time, the ranking will be: (1) P mode > (2) V mode > (3) H mode. have priority.

The code determination circuit 21 controls this priority output operation.
2, and the code determination circuit 212 selects the latch.

Next, the operation of encoding the first line image 402 in FIG. 4 will be described.

First, in this embodiment, at time 1 ( 320 in FIG. 3),
, is the encoding start time.

That is, time 1 (, is the time when the first pixel of the reference line and the coding line appears at the C4 output of the C register 110 or the A4 output of the A register 108, respectively, in FIG. 2).

That is, at time 1 (,), each output of the C register 110, B register 109, and A register 108 is the reference signal.
The states of the first pixel of the line and coding line and the three pixels following the first pixel are output in parallel. Also, aQ
is the initial value ' as shown in 221 AO (ao) in Figure 3.
“It is set to 0pa (white pixel = virtual).

The run length counter 203 starts from the initial value O to the time to
Thereafter, the image clock 134 starts counting.

The count value output of the counter 203 at each time is
It is shown at 322 in the figure.

At time 1 (, at time 1, signal 129-4 in FIG.
" is not set, that is, there is no change point in the A4 output of the A shift register 108 in FIG. 2, and similarly there is no change point in the B4 output of the B shift register 109. Therefore, a code is generated. Since there is no cause, the count value of the run length counter is simply incremented by 1 and the process advances to the next time t1, but the state at time t1 is the same as that at time 1.).

Next, when proceeding to time t2, the signal 129-4 in FIG.
°° is standing. This means that A register 1 in FIG.
The A4 output of 08 becomes 1, indicating that a change point exists at that position on the coding line. Since this change point is the first change point to the right of the current starting point aQ (corresponding to a later time), the symbol detection circuit 201 in FIG. 2 determines that it is the symbol a1.

Note that the detection state of this symbol a1 is stored as Fal.

At this time t2, 130-1 to 130- in FIG.
Looking at number 4, there is no "1" in any of them. This means that there is no change point b1 within three times from time t2. Further, when the symbol detection circuit 201 detects bl, it shifts the bl into the B' shift register 202 so that it does not disappear for three time periods.

The symbol detection circuit 201 also has a circuit for storing that bl has already been detected.

Due to these, in this case, there is no change point pixel b1 within 3 pixels on the left and right of change point pixel a1, and
Until then, it can be determined that there is no bl (therefore, there is no b2 either). Therefore, although al was detected at time t2, P
It is determined that the conditions of mode (b2 must already be detected) and V mode (la1bxl!3 is the condition) are not satisfied, and therefore the mode becomes H mode.

At this time, the value of the run length counter 203 is
As shown in 22, the number of pixels from aQ to al is shown, and “2
It is °゛. Also, the run length color is initially set °“
0°゛=remains white. Therefore, the run length value, color, etc. are given to the ROM table 0206 by the output 228 of the run length counter 203, and the corresponding code and code length are output from the ROM 206. In this case, the code of “white run 2” is output, that is, M (a
oal)=white 2.

At this time, it is determined that it is the first code of H mode, and the code "°001°" indicating H mode is controlled to be output at the same time as the code "0111" of white run 2, that is, in one clock. They are output simultaneously in binary numbers, etc.

Next, the run length counter 203 is set to an initial value of 1 (0
(Note that this is not the case.) and moves on to counting from pixel a1 to pixel a2. However, pixel a1, that is, time t2
Then, only preparations for setting the initial value are made, and the initial value is set in the counter and the count is started from the next time t3. Furthermore, from this time t3, the color of AO is also inverted.

(Time t2=゛0'°→Time t3=゛1'') From then on, as time 1n progresses, at time L4, a change point appears where the A4 output of the A register 108 becomes "1'°."

Since the symbol detecting circuit 201 remembers that the changing point a1 has already passed and been detected (Fa1=1), the symbol detecting circuit 201 determines that the changing point is a2. Note that this detection state of a2 is stored as Fa2. Now, at time t4, the value of the run length reference counter 203 is 2, and AO="1°°=black.Also, since the H mode has already been determined at time t2, a2 When is detected, there is no need to refer to the state of the reference line, ie, 131-1 to 131-4 in FIG. 3 and 130-1 to 130-4 in FIG. 3, although this is not the case.

Even if bl, b2, etc. are present on the reference line, they are controlled to be ignored.

As a result of the above, in the end, the same procedure as in the case of M(ao, al) is performed.

M (a 1. a 2) = black 2° code and code length are output. At this time, unlike the case of M(ao, al), the code 001 indicating the H mode is not added.

Next, one time after time t4, that is, at time t5, the run length counter 203 is set to the initial value 1. or,
AO(-a□) is inverted.

Then, the change point a2 at time t4 is the starting point aQ of the next mode.
considered to be.

Through the above operations, the code generated by encoding the first line 402 becomes as shown at 501 in FIG.

Also, at time 130 in FIG. 3, the run length counter value is 9, and at this time the symbol ft (=at) is detected, but there is a change point b'l after two pixels on the reference line. At time t30, the B register 109 in FIG.
Output 130-2 of C register 110 and output 131- of C register 110
Judging from 2nd place. Therefore, since the condition of 1albl143 is satisfied and the mode is not P mode (b2 is required), the V mode is determined by definition and the VL (2) code (al is located at the position of 2 pixels to the left of bl) is output.

At this time, the H mode run length/white 9 code could have occurred, but according to the definition of priority between each mode mentioned earlier, the ■ mode became the valid code, and the H mode code becomes invalid. Due to the occurrence of the Zara V mode code, the run length counter 203
The count value up to time t30 is cleared and controlled to be newly preset to 1. Also, ■
After the mode code is generated, the color of the origin aQ symbol is inverted. (However, the ■ mode code is generated at the same time as the change point detection of the a1 symbol (time t30).) Also,
Although not explained so far, when symbol b1 is detected earlier than symbol a1, the detection signal of symbol b1 is shifted into the register as an input signal of the B register 202, and is shifted into the register at three times thereafter. Between, B register 202 output, B
It shifts in the order of 5 → B6 → B7, and disappears after that. Further, when the code b1 has already passed through the 84 output of the B register 109 and no code is generated yet, this fact is stored as shown by the output Fbl of the storage detection circuit 201.

Next, specific circuits of each functional block of the circuit block shown in the first diagram will be explained.

Virtual change point generation circuit Al01. of FIG. and the virtual change point generation circuit B105 are circuits of the same type, and both are realized by the virtual change point generation circuit shown in FIG.
703 is a flip-flop, 704 is an OR gate, and 705 is an inversion circuit (inverter).

The operation of the circuit shown in FIG. 7 is shown in the timing chart of FIG. 8. That is, the numbers of the parts in FIGS. 7 and 8 correspond to the numbers in FIGS. 1 and 3. However, Figures 7 and 8
The signal indicated by 701 in the figure is, for example, the position (timing) of the last pixel in one line obtained by decoding the count value of the memory address counter 111 shown in the first figure.
This is a signal indicating. That is, at the time when the signal 701 is generated, the flip-flop 702 is set to the same color as the last pixel of the coding line in synchronization with the clock 134, and after that time, that is, after the horizontal synchronization signal 136-2 is deenergized, the flip-flop 702 is The Q output of 122 is set as the 122 signal, and before that time, the image 121 is output while the horizontal synchronization signal 136-2 is being output.
is configured to output the signal as a 122 signal.

The selector 104 in FIG. 1 is realized by the circuit shown in FIG. 9, in which 902 is an AND gate, 903 is an OR gate, and 904 is an inverter. 123,1 in Figure 9
24 is the output 12 of the line buffer memories A and B in FIG.
3°124, but the signal 901 in FIG.
This is a select signal whose level is inverted for each line, and is generated by the horizontal synchronizing signal 136-2 in FIG. The output to signal 125 is switched by the select signal 901.

Change point detection circuit A106 and change point detection circuit B in Fig. 1
Reference numeral 107 designates a circuit of the same type, and FIG. 10 shows a typical configuration of the change point detection circuit B107. In the figure, 1002 is a flip-flop, 1003 is an exclusive OR gate, and 100
4 is an inverter.

That is, as shown in the timing chart of FIG.
), it is detected that the colors of adjacent pixels are different, and this is used as a change point signal.

Next, specific circuits of various functional blocks in the circuit block of FIG. 2 will be explained.

FIG. 11 is a circuit for detecting the symbol a1 or a2 on the aforementioned coding line and the FAL signal indicating that the aforementioned al has been detected, and is the symbol detection circuit 2 shown in the second diagram.
In the 0 diagram in 01, 1102 is a flip-flop, 1
104 is an AND gate, and 1105 is an inverter.

Now, the numbers of each part in FIG. 11 correspond to the numbers in FIG. 1, etc. The signal shown at 1101 in FIG. 11 returns the flip-flop 1102 to its initial state (i.e., Q output =
This is a control signal that prohibits the Q output from being set to "0") or to Q output = "1"°, and is normally at the "1" level.

The same applies to the RESET signal 1103. Here, when the change point A4 (129-4 signal) arrives first, A4
= “1” in this case.

Since the Q output of the flip-flop 1102 is "1" and the control signal 1101 is "lo", a1="1" is output and the symbol a1 is detected. This a1 detection signal sets the flip-flop 1102 and the control signal 1101 is "lo". Output = “l
o” and remembers that al has already been detected (that is, Q output = F a 1 = “ 1 ”) Detected.

Next, the circuit for detecting the symbol bl etc. is shown in FIG. 12, in which 1201 is an exclusive OR gate;
03 is a flip-flop, 1204 is an AND gate, 1
205 is an inverter. The number of each part is numbered 11th.
This is the same as the case shown in the figure. However, aQ can be bl.
Because of the condition that the color is opposite to that of the signal, the circuit uses the signal obtained by exclusive ORing the change in the reference line and the aQ multiplied signal using the exclusive OR gate 1201. The circuit shown in FIG. 12 is included in the symbol detection circuit 201 shown in FIG.

The specific configuration of the run length counter 203 in FIG. 2 is shown in FIG. 13. First, the run length counter 203 is a 12-bit binary counter as described above.
The counting range of the counter 203 is from 0 (decimal) to 256
0-1 (2559 in decimal), and the counter 203 has a preset function, a clear function, etc.
, model number 74F163, etc.

Furthermore, the count value output of the counter 203 is decimal number 2.
559 and generates the MKI signal.
301 and the value obtained by decoding the lower 6 bits of the output is 1
The circuit 1302 detects that the decimal number is "63pa" and generates an MK2 signal.

Furthermore, the value to be set using the preset function is O” (
The structure is such that it can be selectively preset to decimal number) or °'l'' (decimal number).

The movement of the run-length fist counter 203 will be explained. First, preset (or clear) the initial value “O°” at a position outside the left edge of the image for each coding line.
In the zero-order image area, the count is sequentially advanced pixel by pixel, but in the following values or three states, the counter 203
is returned to °°1″ by the preset function.

That is, (1) when change point a1 or a2 is detected, (2) when the count value reaches 2559, (3) when P-mode code or V-mode code occurs, however, the encoding method According to the rule, if the change point a1 is set to a2 on a virtual pixel outside the rightmost end of the coding line, the counter value is returned to "Opa" when al is detected.

Next, the configuration of the ROM table A204 in FIG. 2 will be described. The ROM table A204 is for generating a total of 8 types of codes, P mode and V mode, and the code lengths. As is clear from the configuration principle of this embodiment and the above explanation, the configuration described here is based on the relative relationship between the change point positions of the coding line and the reference line, and especially when the change point b2 on the reference line is at the B register 1.
09, or when the change point a1 on the coding line appears as the A4 output of the A register 108, the state of the symbol detection circuit 201 and the A register 1081. The configuration is such that the status of each output of the B register 109, C register 110, and B register 220 can be determined simultaneously and in parallel. Therefore, the combination of the states of the above-mentioned request forces is naturally finite, and at the time when the judgment is to be made, it can be treated as a stationary state. Therefore, since the P mode or V mode code and code length to be output for each combination can be determined, it can be configured as the ROM table.

Since the specific contents of the ROM table are too redundant here, as an example, FIG. 14 illustrates a case where a P mode code and code length are generated by a logic circuit equivalent to a ROM. In the figure, 1409 is an inverter, 1410 is a timing circuit, 1411 is a Nant gate, and 1412 is a NOR gate. That is, 140 in FIG.
The signal indicated by 1 is No. 18 indicating that the symbol detection circuit 201 in FIG. 2 has detected the change point b2 on the reference line.

That is, this means that the B4 output of the B register 109 in FIG. 1 has a changing point as b2. Similarly, the a1 signal indicated by 1402 in FIG. 14 is the a1 change point as the A4 output of the A register 108 in FIG. Furthermore, the Fa1 signal shown at 1403 in Fig. 14 has reached the second level by the current time.
This is a signal indicating that the graphic symbol detection circuit 201 has already detected the change point as al.

The logic circuit in FIG. 14 means that at the time when b2 is detected, the P mode is determined because the al or Fal signal is not true. In other words, the starting point a
This means that there is no a1 change point after Q until the time when b2 is detected. In other words, on the image, from the starting point aO to b
This means that there is no a1 change point directly below the two change points.

Therefore, by definition, it is in P mode. 140 in Figure 14
4 is a P mode detection signal, 1405 is a specific code of P mode, and 1406 is a binary number representing the code length of the P mode code. Further, 1407 is a signal indicating that a P mode code has been generated. The above is the determination method for P mode, but the same method can also be applied to ■mode. The ROM table A204 is configured by this method.

After all, the code and code length of the P mode or V mode are determined by applying the status signals of each register etc. as input data to the ROM table A204 in FIG. 2 based on the above method at the time when the b2 or a1 symbol is detected. In some cases, it is generated instantaneously at a time of 1 clock.

FIG. 2 (7) Since ROM table B2O5 and ROM table C206 have similar structures, the first
The ROM table C206 will be explained with reference to FIG. 5 and FIG. 16.

First, 206 is a ROM with at least 11 bits of address input and 21 bits of parallel output;
The human power corresponds to the 228 signal in FIG. That is, they are the lower 6 bits of the run length counter 203 in FIG. Further, 1502 manual input in FIG. 15 is a signal specifying the color of the run length, and in this example, auto=O1 black=1.

Also, 1503 human power is the code indicating H mode (=001)
This is a signal that specifies whether to add or not. In this example, required = 1
, unnecessary=0. That is, if 1503 manpower is 1, H
The code (OOl) is added to the first run-length code of the mode code and is output at l clocks.

Reference numeral 1504 is a chip enable signal that controls whether to enable or disable the output of the ROM 206 (7). 1
507 manpower is EOL<1507 manpower is EOI, +1.1
508 are address inputs that control the reading of each of EOL+O, and by inputting pulses to these inputs, the delimiter code of the corresponding line is read. Further, 1505 is the code output of the address specified by the input, and 1506 is the code length of the code.

FIG. 16 is a diagram showing the correspondence between each address AONA10 in FIG. 15 and storage contents (data).

The code determination circuit 212 of FIG. 2 is specifically explained with reference to FIG. 17. In FIG. 17, 1706 is an AND gate;
is an inverter.

As can be seen from the principle of the code generation method in this example,
ROM table 204 and 205 or 206 shown in the second diagram
etc., P mode.

In the stage before each mode and H mode code is finally determined as the code to be generated, two or more codes may be output from the ROM table at the same time. However, the priority of two or more codes is defined as described above.

FIG. 17 shows a circuit for determining the code to be uniquely generated according to the definition.

That is, if P mode, ■ mode, and H monido codes can occur simultaneously, the code of the mode that has acquired priority will ultimately be generated according to the order of P mode>■ mode>H mode as described above. Determined as the correct code.

Codes for other modes are invalid and cannot be used as generation codes.

Note that the signal 1708 uses the MH method for this encoding circuit.

In other words, it is a mode signal for selecting whether to use it for -dimensional encoding or for two-dimensional encoding of MMR or MR. When executing, it becomes H level.

Therefore, when performing -dimensional encoding, the generation of P-mode and V-mode codes is prevented, and only the H-mode code, that is, the code representing the run length, is always valid.

Next, the roles of the latch A207, latch B2O3, etc. in FIG. 2 will be described. Latch A207 and latch B2O
Reference numeral 3 denotes a circuit for temporarily storing an H-mode make-up code and code length that may occur during coding until it is determined whether the H-mode is valid or invalid. If it is determined that the H mode is valid, the contents of the latch are transferred to the next stage circuit.

Taking the functions of the latches A207 and B2O3 in FIG. 2 as an example, a case where the run length in which the make-up code is generated is long will be explained, for example, with run length=2972. At this time, according to the encoding regulations, the code is divided into a total of three ten-length codes, two make-up codes and one terminating code, and output as follows.

That is, Makeup code 1 = Ten length 2560 code (common for white and black) Makeup code 2 = Run length 384 code (White or black) Terminating code = Run length 28 code (White or black) In this way, 2560 + 384 + 28 =2972, when one run length is represented by multiple codes, first, the count value of the run length counter 203 in FIG. 2 is 63+64XN (N=0.1.2...
If the A4 output of the A register is not at the a1 change point at that point, it is predicted that a make-up value will occur next, and the upper 6 bits of the counter 203 (Iff(N (equivalent to
Makeup code and code length of ROM table B2O5 are output from latch B2O3.
Temporarily memorized (latched) to , then the previous value count value is 6.
The contents of the latch B2O3 are updated every time N advances by 4 (that is, each time N advances by 1 in the formula 63+64XN).

Then, the value of the run length counter 203 is 2559.
(In other words, if the change point a1 is not detected at the time when N = 39 in the formula 63 + 84 Read the code and code length of 2560 and latch A2.
078 Temporarily memorized. At the same time, the stored contents of latch B2O3 are temporarily invalidated. Further, the count value of the run length counter 203 is returned to the initial value l. Subsequently, as the count progresses, storage of makeup codes and the like to the latches B2O3 is restarted again in the same manner for each hole of 63+64XN.

When the change point a1 is detected, the competitive relationship with other P mode or V mode is determined, and when the H mode is determined, the run length counter 2 at the time of the change point a1 is determined.
The ten-length termination code and code length indicated by the value of the lower 6 bits of 03 (O to maximum 63) are temporarily stored in latch C209. Furthermore, as described above, the contents of latch A207 and latch B20B also become valid.

However, if the V mode or the like occurs at the time of the change point a1, the H mode itself will not occur, and naturally the latch A20
7 and the contents of latch B2O3 are invalidated, and the contents of latch C
209 instead of the above-mentioned terminating code.
Mode code is latched as valid code.

Makeup code 1 and makeup code 2 above
FIG. 18 shows a circuit for controlling the generation and storage of the data, etc., and this circuit is included in the timing circuit 112. Timing chart of this circuit (run length is <2 as mentioned above)
972) is shown in FIG. 19.

1801.1802 are flip-flops.

1803 is an AND gate, and 1804 is an inverter.

MKI and MK2 are signals output from the 2559 detection circuit 1301 and the 63 detection circuit 1302, respectively, of the run length counter 203 shown in FIG. The flip-flop 1802 is set by the input of the MK2 signal and generates the MK2 presence signal, and the flip-flop 1801
is set by the input of the MKIi signal and generates the MKI presence signal. Note that the flip-flop 1802 is reset by inputting the MKI signal.

With the above configuration, the run length counter 203
When the count value becomes 64 or more, the MK2 signal becomes high level, and when the count value becomes 2560 or more, the MK2 signal becomes high level.
Only the KI presence signal or both the MK2 presence signal and the MK2 presence signal become high level. Depending on the levels of the MKI presence signal and the MK2 signal, it is determined whether the code representing the run length is only a termination code or a combination of a termination code and a makeup code.

Also, it can be determined whether the number of makeup codes is 1 or 2. Therefore, when generating a code in H mode, the backing circuit 211 determines the levels of the MKI present signal and the MK2 present signal, and the three latches A,
Select the valid one from B and C and import its latch data.

In this way, when the make-up code is generated, by predicting the generation of the code at least one time in advance and sending the code to the temporary memory circuit (latches A and B), the change point a1 can be predicted. This is extremely effective in circuit configuration since it has the effect of preventing an increase in the number of output codes and the number of bits to be processed at the same time.

That is, by temporarily storing the required make-up code and code length among the numbers counted by the latch A 207 and latch B 20g run length counter 203 before determining the H mode, the terminating code and code length are stored when the H mode is determined. Since only the code length needs to be processed, all the H-mode codes to be output at the time of a1 detection are available, and the subsequent encoding operation can be executed without delay.

207, 208, 209 latches A, B.

The order in which the contents of C are sent to the next stage circuit is latch A207>
Controlled to maintain the order of latch B2O3 > latch C209 (21O buffer) (omitted when the contents are invalid,
ignore).

The reason why the contents of latch C209 are temporarily stored in Batza memory 210 is that the next encoding operation starts from the time after the encoding mode is determined, and the next encoded data is stored in latch C209 from the ROM table for several clocks (minimum 1 clock). Therefore, after the mode is determined, the contents of the latch C209 are sent to the buffer memory 210 so that the next encoded data can be latched, and then output from the buffer memory 210 to the subsequent stage at a certain timing.

Next, a special case in which the change point a1 and the change point a2 are set on the same pixel according to the encoding method will be described.

FIG. 20 illustrates the above case. That is,
In Figure 20, 2001 is the reference line, 2
002 is a coding line. Also, 2003 is the final pixel of the coding line, and 2004 is the virtual change point (
pixels).

Now, in FIG. 20, assuming that the starting point ao is at the position shown in the figure as a result of encoding from the left, the code to be generated next is as shown in FIG.

[H mode code + white 12 terminator code + black O terminator code]. Here, the code in Figure 21 (1) can be treated as one code at the time of the change point a1 by the above-mentioned means, and there is no problem. However, the code in Figure 21 (2) originally changed at the change point a2. This is the code that should be generated at the time of change point a2 when the time point is different from point a1. However, in this case, it is clear that the change point a2
As such, it is not detected by the symbol detection circuit 201 or the like.

Therefore, in this case, the following processing is performed by the circuit shown in FIG. 22 provided in the symbol detection circuit 201. FIG. 23 is a timing chart of the operation of this circuit. In FIG. 22, 2201 is a signal indicating that the image has entered the virtual area (
2202 is an a1 change point detection signal, and 2203 is a signal indicating up to the generation of the first termination code in H mode. The signals 2201 to 22 are monitored by the AND gate 2207.
Detect the state in Figure 20 by taking the AND of the 03 signals, create the 2204-1 signal (that is, time 1 is the same as al), and first output the code in Figure 20 (1) using the method described above. After performing predetermined processing such as clearing the run length counter to O, the signal 2205-1 in FIG. 21 is generated by delaying the signal 2204-1 in FIG. 2) Generates the black 0 termination code.

The backing circuit 211 in FIG. 2 receives as input the code and code length obtained by the method described above, and the length of each code (the number of bits of the code) generated by this division is not constant. However, even if the H mode code (=ooi) is added, the longest is 16 bits), and the circuit is sequentially grouped in units of 16 bits, and in this embodiment, each 16 bit is transferred in parallel to the next external circuit. This is what we do.

The signal 238 in FIG. 2 is a code compiled into 16 bits by the backing circuit 211, and the signal 239 is a signal for reporting this fact to the next stage external circuit. Note that the backing circuit 211 is a code length addition circuit and a bit shifter.

This can be easily realized by combining well-known circuits such as multiplexers and latches.

Next, there is an RTC (Re turn) indicating the end of one page.
To Control) signal details. MM
In the case of the R method, RTC code=EOL code×2 times.

That is, the RTC signal is (000000000001)X2=
0000000000QI, 00000000000
It is expressed as 1. Also, in this embodiment, as described above, the structure is such that up to 16 bit codes can be output in one clock time. Therefore, in order to output the RT-C signal, the end of one page is detected by monitoring the vertical synchronizing signal 136-1 shown in FIG.
This pulse is used as the address signal 150 of the ROM table 0206 (shown in FIG. 15).
7, the EOL code and code length are written in the corresponding address of the ROM table, and by outputting them, the RTC code can be obtained following the code for the above-mentioned image.

Next, Table 1 lists the differences between the three encoding methods described above.

Therefore, the encoding method of the Ml (method) is almost the same as the case of repeating the H mode of the MMR method described above, but differs in the following points.

That is, (1) H mode code (001) is not required in the MH method (2) It is not necessary to pair white runs and black runs in the MH method (3) Inserting an EOL code for each line in the MH method (4) Differences in RTC and in the case of the MR method: (1) One-dimensional lines are the same as the MH method (2) Two-dimensional lines are the same as the MMR method (3) Line separation is EOL + 1 = 0000000000011 or EOL + 0 = OO00000000010 (4) RTC
Difference (5) Due to the K parameter, one-dimensional lines and two-dimensional lines coexist.

After all, switching between the three encoding methods can be easily realized by controlling the operation S of the circuit for the MMR method described above using a method selection signal for the MR method or the MH method.

First, FIG. 24 shows an example of a circuit for controlling differences between lines, delimiters, and codes. In the figure, 2407 is a line counter;
408 is Nantes Gate, 2409 is And Gate, 24
10 is an inverter. That is, 2401 in FIG. 24 is a pulse signal at time t-1 shown in 320 in FIG. do not. This pulse signal at time t-1 is obtained by decoding the value of address counter 111. Further, 2402 and 2403 are encoding method selection signals from outside the circuit of this embodiment, such as a CPU, which specifies the encoding method. Also, the 136-2 signal is 13 in Figure 3.
Therefore, the K advance counter 2407 counts the signal 136-2 and monitors the progress of the parameters in the MR method as a line counter.

Signals 2404 to 2406 obtained by the logic in FIG.
were used as address inputs for the ROM table C206 in Figure 2 (1507 to 1508 in Figure 15), each specifying a specific address, and the code and code length required for the specific address were stored. The desired line/separator Φ code is obtained by outputting the desired line/separator Φ code.

Furthermore, the one-dimensional line encoding method of the MH method is described in the 17th
The selection signal 1708 may be used to control the mode determination circuit of the MMR method shown in the figure so that the H mode can always be given priority.

Also, in MHi, control is performed so that the H mode code (001) is always unnecessary, and this is also achieved by setting the address signal A7 of the ROM table C20B to 0.

Also, the difference in the number of EOLs in RTC is ROM table C.
This is achieved by varying the number of pulses applied to 206 depending on the mode.

In this embodiment, as shown in FIG. 3, etc., it operates in synchronization with the (image) clock 134, but it is not related to the interval (period) of the clock. Therefore, as shown in Figure 25,
A pause period can be easily provided between images or lines by masking the clock 134 with an image gate signal, so to speak.

That is, in FIG. 25, 2501 is the image gate signal "0".
2502 is a signal indicating that the operation is stopped during the "° level. Also, 2502 is a signal that indicates that the operation is stopped during the "° level.
2502, and if this clock 2502 is sent to the actual internal circuit of this embodiment instead of the aforementioned clock 134, the state of this embodiment can be changed only by the clock signal. Since the state can be changed, the shaded area in FIG. 25 is clearly in a rest state.

With this pause control, for example, the output speed of the image signal of the source of the image signal to be encoded is not limited by the operation of the encoding circuit, or conversely, for example, if the image source is Even if the image signal of one page is output intermittently, such as in the case of an image file provided with the image file, the encoding circuit can perform the encoding operation intermittently in synchronization with the intermittent output. Therefore, the image signal from the output source can be sequentially encoded without requiring a large amount of backup memory for time alignment between the image signal output source and the encoding circuit.

Next, a method of supplying images to be encoded to the circuit of this embodiment in parallel format will be described with reference to FIGS. 26 and 27. That is, 2601 in FIG. 26 is a parallel-to-serial change shift register that can input 8-bit parallel data and output it to 2602 as 1-bit serial data.

As shown in FIG. 27, after loading the image signal to be encoded into the register 2602 as 8-bit parallel data,
The signal is serially shifted by a clock, and a serial image signal 2602 as shown in FIG. 27 is obtained. At the same time, the number of clocks during the serial shift is counted to generate a gate signal 2702 indicating the section of the actual data, and a clock 2702 corresponding to the actual data can also be obtained in the same way.

As described above, the word signal as shown in FIG. 27 is in a format that can be encoded as described above in this embodiment by the pause method described in FIG. 25. The operation for parallel input of this image is Cp
This is extremely effective when an image is provided by u, etc.

In the above embodiments, MH, MR, and MMR encoding has been described, but it goes without saying that other encoding methods can also be applied. The encoded code is input from a digital reading device, a computer, etc., and the encoded code is transmitted to a remote location via a transmission line or the like, or is stored in an image file. Although the present invention has been described above based on preferred embodiments, it goes without saying that the present invention is not limited to this configuration, and that various modifications and changes can be made within the scope of the claims.

Table 1 [Effects] As explained above, according to the uninvented invention, the identification code indicating the water mode and the first encoding code to be generated following it are output as an integrated code, so multiple codes can be output. The output time at the time of output is shortened, and encoding operation without delay can be used for the input image signal.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing the configuration of an encoding device to which the present invention is applied, FIG. 3 is a timing chart showing the encoding operation, and FIGS. 4, 5, and 6 are reference line 7 is a diagram showing a configuration example of a virtual change point generation circuit, FIG. 8 is a timing chart diagram showing the operation of the circuit shown in FIG. 7, and FIG. 9 is a configuration example of a selector. , FIG. 10 is a diagram showing an example of the configuration of a change point detection circuit, FIGS. 11 and 12 are diagrams showing an example of the integral configuration of the symbol detection circuit, and FIG. 13 is a diagram showing an example of the configuration of a run length counter. 14 is a diagram showing a configuration example of an equivalent circuit of ROM table A, and FIG. 15 is a diagram showing an example of the configuration of an equivalent circuit of ROM table A.
FIG. 16 is a diagram showing an example of the contents of ROM table C, FIG. 17 is a diagram showing an example of the configuration of the code determination circuit, and FIG. 18 is a configuration example of the make-up code generation and storage circuit. 19 is a timing chart showing the operation of the circuit shown in FIG. 18, FIG. 20 is a diagram showing the relationship between the beam reference line and the coding line, and FIG.
Figure 22 is a diagram showing a configuration example of a delay circuit at a virtual change point, Figure 23 is a timing chart diagram showing the operation of the circuit shown in Figure 22, and Figure 24 is a diagram showing control of generation of line separation codes. Diagram 25 showing an example of the configuration of a circuit for
26 is a timing chart showing a pause control operation of the encoding operation, FIG. 26 is a diagram showing a configuration example of a circuit that serially outputs parallel input of an image signal, and FIG. 27 is a timing chart showing the output state of the circuit shown in FIG. 26. It is a chart diagram, and 10
1 and 105 are virtual change point generation circuits, 106 and 107
is a change point detection circuit, 108 to 110 are registers, 111
is an address counter, 201 is a symbol detection circuit, 203 is a run length counter, and 207 to 209 are latches. Applicant: Canon Co., Ltd. Managing Director: Gi Marushima - Rokun Wa 7th figure: Xie J drawing 52 illustrations tO drawing roll//Illustration #/215J Moeshi 73 drawings reprint 2 Tsu,/Otsu U 2nd Theta Section 24th Figure VEN Pause Pause

Claims (1)

[Claims] means for serially capturing the image signal of the reference line in synchronization with the serial input of the image signal of the encoded line; means for counting the number of pixels between changing points of the image signal of the encoded line;
means for monitoring the correlation between the image signal of the encoded line and the image signal of the reference line and determining the encoding mode; and means for generating the encoded code based on the count of the counting means, Two-dimensional encoding of an image signal, characterized in that when the horizontal mode is determined by the means, an identification code indicating the horizontal mode and a leading encoding code to be generated by the generating means are output as an integrated code. Device.