JPS6231263A - Two-dimensional coding device for picture signal - Google Patents

Abstract

PURPOSE:To decrease the burden of coding action due to the occurrence of plural codes and to realize the coding action with good efficiency by dividing and outputting plural codes to the same picture element. CONSTITUTION:When the run length generated by a make-up code is long, for example, in case of the run length = 2972, one run length is displayed by plural codes like 2560 (make-up code 1) + 384 (make-up code 2) + 28 (terminating code). Before a run length counter 203 determines the H mode, out of the number counted, the necessary make-up code and the code length are stored temporarily. Next, when the changing point is detected and the H mode is determined, the terminating code and the code length of the run length shown by the value of the lower order 6 bits of the run length counter 203 at the time of the changing point are once stored to a latch C209, and thereby, at the time of determining the H mode, when the terminating code and the code length only are processed, the code of the H mode to be outputted are all arranged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a two-dimensional encoding device for image signals used for facsimiles, image electronic files, and the like.

[Prior art]

In conventional image transmission devices such as facsimiles and recent image file devices using optical disks and magnetic disks, image signals are encoded and handled to reduce data loss and increase the speed and efficiency of transmission or storage operations. is planning to change. 7 For example, in the field of facsimile, the modified Huffman (MH) method is generally used for one-dimensional encoding, the modified read (MR) method is used for two-dimensional encoding, and the modified modified read (MMR) method is used for high rate two-dimensional encoding. It is being

Regarding the mutual relationship between these MH, MR, and MMR methods, the MMR method includes methods that are very similar to the MH method, and the MMR method is a partially modified version of the MR method.

Furthermore, the images to be encoded and the rules of the encoding method are, in a nutshell, based on T4 and T6 recommended by the CCITT (Consultative Committee for International Telegraph and Telephone).

Furthermore, the above-mentioned encoding method was developed in March 1985 for the MMR method.
The MR method is announced as a high-efficiency two-dimensional encoding method in the recommended communication method for facsimile group 4 type equipment (Postal Service - Migami) on page 52 and below of the Official Gazette (Extra Issue No. 29) dated May 22, 2017. Both the original encoding method and the MR method are two-dimensional encoding methods as per Ministry of Posts and Telecommunications Notification No. 1013 of 1982.
It is announced in the number.

In two-dimensional encoding such as the above-mentioned MR and MMR, the encoding operation is performed based on the correlation between change points and color information of the image signal of the line to be encoded and the image signal of the previous line. Furthermore, as an encoding rule, a virtual pixel is defined after the last pixel of the line to be two-dimensionally encoded.

In this encoding, it becomes necessary to generate a plurality of encoding codes for this virtual pixel. In such a case, if you try to generate multiple codes when inputting that pixel, each code will have an undefined length due to the characteristics of the code, and depending on the run length, the code length will become long, which will place a burden on the circuit. .

(L, I target) The present invention has been made in view of the above points, and the above-mentioned M
The purpose is to reduce the burden of generating encoded codes in two-dimensional encoding such as R, MMR, etc., and to execute encoding efficiently. A means for serially capturing the image signal of the reference line, a stage for counting the number of pixels between changing points of the encoding line, and a means for monitoring and encoding the correlation between the image signal of the encoding line and the image signal of the reference line. means for determining a mode; and means for generating an encoding code based on the count value of the counting means, wherein the horizontal mode is determined by the determining means and a plurality of encoding codes are generated for the same pixel. If generated, the present invention provides a two-dimensional encoding device for an image signal, which outputs the first encoding code to be generated corresponding to the pixel, and outputs the encoding code following the output.

〔Example〕

Examples of the configuration of an encoding circuit to which the present invention is applied are shown in Figures 1 and 2.
This is shown in the circuit block diagram in the figure. Next, the operation of this embodiment will be explained using FIG. 1, FIG. 2, FIG. 3 to FIG. 5, etc.

In FIG. 1, the signal indicated by 121 is an image signal to be encoded supplied from an external device such as an image scanner, an image file, or a computer.
For example, it is given as serial data of a binary signal of "0°" = white, "11 I+ = black pixel)". Also, 134
The signal indicated by is a clock supplied from an external device in synchronization with the input of the image signal 121, and is one clock per pixel. Next, a signal 136 is a synchronization signal, and indicates several types of synchronization signals indicating horizontal sections, vertical sections, etc. of the image signal 121.

That is, in this embodiment, the image signal 121 to be encoded is provided as a scanning image signal that is a serial image signal for each main scan, similar to a signal provided to a laser printer or the like.

Next, 101 is forcibly changed so that the next pixel (=virtual pixel) after the last pixel of the real image on the coding line (one tree in the main scanning direction of the image to be encoded) is always the change point. This is a circuit that generates points, and is called a "virtual change point generation circuit A." However, the above-mentioned "virtual change point generation circuit A" has a structure that does not give any change to the real image on the coding φ line.

102 is a line buffer memory A, and 103 is a line buffer memory B, each of which is a RAM (random access memory) that can write or read independently, and each of which stores binary values for one coding line. It has a capacity (number of main scanning pixels) that can store images.

Further, the line buffer memory AlO2 and the line buffer memory B103 are controlled so that when one is performing a write operation, the other is performing a read operation. In other words, these two line buffer memories constitute one set of double buffer memories.

A memory address counter 111 is a counter that counts a clock 134 corresponding to the number of pixels of a coding line. The count value of the counter 111 is commonly given as a memory address signal 135 to both the line buffer memory AlO2 and the line buffer number memory B102. Also, the memory address counter 111 returns to the initial value for each coding line and repeats the counting operation. Therefore, the binary image of each line written to the line buffer memory is newly input. It is read out for each pixel in correspondence with the pixel position of the line image signal 121.

104 is a selector, and line buffer memory A
Of lO2 or rise buffer Φ memory B103,
This circuit operates selectively in response to a select signal 901 in order to obtain read data from whichever one is executing the read operation.

The data selectively obtained by this selector 104 is given to the next stage as a reference line 125, that is, as reference data (image) of the coding line.

105 is a circuit that forcibly creates a change point so that the last pixel of the real image on the reference line and the next pixel (virtual pixel) always become the change point, and is called "virtual change point generation circuit B".
”.

However, the virtual change point generating circuit B105 has a structure that does not give any change to the real image on the reference line.

Reference numeral 106 denotes a circuit that detects a pixel serving as a changing point on the real image and virtual pixel on the reference line, and is referred to as a "changing point detection circuit A."

Further, 107 is a circuit for detecting changing points on the real image and virtual pixels on the coding line, ``changing point detection circuit B''.
It is called.

108 is A register, 109 is B register, 110 is C
Each register is a 4-bit shift register. Also, the signals denoted by 126 are signals representing the real image and virtual pixels on the reference line, and the signals denoted by 127 are signals representing the real image on the reference line. and a change point signal on the virtual pixel. The signal indicated at 128 is the coding signal.
These are a real image of a line hill and a change point signal on a virtual pixel.

A timing circuit 112 receives a clock 134 and a synchronization signal 136, and based on these, forms various timing signals 137 for timing the operation of each circuit block.

The operation of the circuit block of FIG. 1 described above will be explained using an example in which an actual image (image to be encoded) as shown in FIG. 4 is given and is encoded by the MMR method.

First, in the image shown in FIG. 4 shown here, in order to simplify the explanation, one line consists of 32 pixels (number of main scanning pixels = 32 pixels), and a total of 2 lines (number of sub-scanning lines = 22). This created an extremely simple image that constitutes one page.

To actually encode the first line 402 in FIG. 4, use the virtual line 401 in FIG. 4 as a reference line and the first line 402 as the coding number line, as shown in FIG. do.

When encoding the second line 403 in FIG. 4, the first line 402 in FIG. 4 is used as a reference line, as shown in FIG. 6.

The second line 403 is a coding line.

Below, it is assumed that one page consists of main scanning of 3 or more lines,
Even if the third line, the fourth line, etc. continue, if the relationship between the reference line and the coding line is sequentially lowered as described above, the encoding will be possible regardless of the number of sub-scanning lines. I can continue.

FIG. 3 is a timing chart when the image illustrated in FIG. 4 is applied to the circuit block illustrated in FIG. 1.

In FIG. 3, a vertical synchronizing signal 136-1 indicates an image section in the sub-scanning direction, that is, an input period of one page of images. 136-2 is a horizontal synchronizing signal, which is an image section in the main scanning direction;
That is, it shows the input period of the l-line image. 134 is an image clock, 121 is a signal waveform representation of the image to be encoded illustrated in FIG. 4, and black pixel -1"="H°
', white pixel = "Q II = ti L IT. That is, among the images shown in the third figure, the image in section T1 is the actual image of the first line 402 shown in the fourth figure to be encoded. , the image of section T2 is the actual image of the second line 403 shown in the fourth figure to be encoded.

Furthermore, in an image printed on an actual paper surface, the virtual line 401 shown in the fourth figure corresponds to a so-called margin at the upper part of the paper surface, or outside the paper surface, and in the MMR method, It is defined to be assumed to be an all-white line (all pixels in one line are white pixels). Therefore, the virtual line 401 shown in the fourth figure does not appear on the image signal 121 shown in the third figure.

FIG. 5 is a timing chart showing the encoding operation of the first line 402, and shows the relationship between the virtual line 401, which is a reference line, and the first line 402, which is coding.

First, when the image of the first line 402 shown in FIG. 5 is given to the virtual change point generation circuit A101, a virtual change point (virtual pixel) 302 is added as shown at 122 (coding line) in FIG. It becomes an image. That is, in the interval T1, the actual image remains unchanged, but as shown in the figure, the last pixel 301 of the first line and the next pixel 302 have contradictory colors (white→black). Also, virtual change point (virtual pixel) 302
The virtual several pixels following 302 are kept as pixels of the same color as the virtual change point (virtual pixel) 302 so that they do not become change points for reasons described later.

Now, the coding line signal 122 in FIG.
As shown in FIG. 1, is input to the change point detection circuit B107 as an image signal to be encoded, and is also given as write data to the line buffer memory AlO2 and line buffer memory B103.

On the other hand, the address counter 111 counts the image clock 134 only in interval T1 in FIG. 3, outputs a count value as shown at 135 in FIG. AlO2
and the line buffer memory B103.

Furthermore, although not shown in the figure, assuming that the line buffer memory AlO2 is controlled to write mode and the line buffer memory B103 is controlled to read mode.
The data of the coding line 122 is sequentially written to the address indicated by the memory address 135 in the line buffer memory AlO2. Also, at this time, the line buffer memory B 103 is in the read mode as described above, so if all 0 degrees are written in the initial state, the line buffer memory B 103 will be read from the address specified by the memory φ address 135.
are read out sequentially to become a read signal B shown at 124 in FIG.

Reference numeral 125 in FIG. 3 indicates the data signal waveform of the reference line, which is "0°" during the interval Tl.

That is, as shown in FIG. 5, the virtual line 401 is obtained on the circuit as an "all-white" reference line.

The coding line 122 is also provided to the change point detection circuit B107 as described above. The detection circuit B107 detects a change point (pixel) in the given data input, outputs the change point pixel as 1'', and outputs all pixels that are not a change point as 0. 128 in FIG. 1 is the output.

Virtual change point generation circuit B105 and change point detection circuit A10
6, as its name suggests, is the coding line 1 mentioned above.
Circuits 101 and 107 with the same name that operate on 22
The following operations are performed on the reference fist line 125 read from the line buffer memory.

Eventually, the signal on the reference line 125 is converted by the virtual change point generating circuit B105 into a signal in which a virtual pixel of a color different from the last pixel is added next to the last pixel, as shown at 126 in FIG.

The signal 128 generated from the change point detection circuit B107 is sequentially shifted into the A register 108 by the clock 134. Symbols A1 to A4 of the A register 108 each indicate a parallel 4-bit output of the register, which is always output. The output signal waveforms of the A register 108 are shown at 129-1 to 129-4 in FIG.

Therefore, if the pixel of interest on the coding line is shifted to the output A4 of the A register 108, it can be determined from the output 129 whether there is a change point in the data for three pixels following the pixel of interest.

Similarly, 130-1 to 130-4 in Figure 3 and 1 in Figure 3
31-1 to 131-4 show the output signal waveforms of the B register 109 and the C register 110. That is, B register 10
The change point signal and color signal of the pixel of the reference line corresponding to each pixel position stored in the A register 108 are stored in the 9 and C registers 110. Therefore, if the output A4 of the A register 108 is the pixel of interest on the coding line, the B register 109 and the C register 1
10, it is possible to determine whether there is a change point within the three pixels following the pixel position of interest on the reference line and its color.

To encode the second line, the second line 403 in FIG.
When input as the image signal 121, the line buffer memory Al02 is in the write mode, and the line buffer memory B103 is in the read mode.

That is, the first line 4 written in the line buffer memory B103 during the coding operation of the first line 402
02 becomes the reference line, and the second input line
Line 403 is the coding. Then, the same operation as in the first line is executed.

Each signal waveform on the second line 403 is shown in section T2 in FIG. At this time, the data of the first line 402 written in the line buffer memory AlO2 during the interval Tl is read from the end of the interval T2 of the reference line 126.

The above is the specific operation of the circuit block shown in the first diagram.

Next, the circuit block shown in the second diagram will be explained.

201 is a symbol detection circuit, and as shown in the figure, signals 129,
130, 131, and the necessary symbol aQ in the MMR encoding method.

This is a circuit for detecting symbols such as al, a2, tB, and b2. The definitions of these symbols are as follows.

aQ=pixel of the coding line that is the starting point for coding.

al”: first change point (pixel) on coding line L to the right of aQ 6 a2 = first change point (pixel) on the coding line to the right of al.

bl=A changing point (pixel) on the reference line to the right of a□, the opposite color to aQ, and the first changing point.

b2 = first change point (pixel) on the reference line to the right of b1.

However, the right here is the same as the relationship between the left and right of each pixel shown in FIG. 4, for example.

Next, there is a B register 202, and the clock 134 receives the change point signal b1 shown at 222 in FIG. 2 as input data.
are shifted in sequentially by 3 bit shift
It is a register.

Therefore, the change point signal b1 detected by the symbol detection circuit 201 is held for a total of three clock periods, and the position of the change point signal b1 with respect to the pixel of interest can be determined.

203 is a run length red counter, which usually corresponds to pixel a
It is a binary counter that counts the number of pixels (run length) from Q to pixel a1 or from pixel a1 to pixel a2, and has a 12-bit output, and the maximum is 2 in decimal notation.
This counter can count up to 559.

The signal shown at 228 in FIG.
These are the lower 6 bits of the count value output of 03. or,
The signal shown at 227 in FIG.
These are the upper 6 bits of the count value output of 03.

204 is a ROM table A, which mainly stores codes for pass mode (P mode) and vertical mode (V mode).
A ROM (read only memory) that stores the codes and the number of bits (code length) of each code, and can output the codes and code lengths in parallel according to a given input.
It is.

Further, 205 is a ROM table B, which is a ROM that mainly stores make-up codes and code lengths for the horizontal mode (H mode), and stores the code and code length to be output using the signal 227 as an address. is selected and output.

Reference numeral 206 denotes a ROM table C, which is a ROM that mainly stores H-mode terminating codes and code lengths, and selects and outputs the code and code length to be output using the signal 228 as an address.

Reference numerals 207 and 208 are latch circuits that temporarily store the make-up code and code length output from each of the ROMs. Further, 209 is a latch circuit that temporarily stores the terminating code and code length output from the ROM.

210 is a buffer memory for sequentially receiving the code and code length in the latch circuit C209 and temporarily storing it.

Here, let's talk a little more about the encoding rules of the MMR method.

Let me state that in this encoding method, the symbols ao+a1. a2 is on the coding line, and similarly symbols b1 and b2 are on the reference line. And each of these symbols ao + at
r a2 group and bl.

Based on the relative position (distance) of the group b2, it is specified that the encoding mode is uniquely selected from the following three modes and encoding is performed.

(1) Pass mode (P mode) When b2 is to the left of al (there is only one generation code) (
2) Vertical mode (V mode) When Ia1btl≦3 (A total of 7 types of generation codes differ depending on the distance) (3) Horizontal mode (H mode) At times other than (1) and (2) above (run/ (according to length code table) Format: H+M (a □ a 1) 10M (a l
a2) Here, H is a code indicating H mode, M (a
o a 1) White or black Iaoaxl run length code.

M(a1a2) is black or whitec7) Iata21 (7
) -y 7 L/ngsu code.

However, if two or more of the above (1), (2), and (3) are satisfied at the same time, (1) P%-do > (2) V%-do > (3) H Priority is given in order of mode.

The code determination circuit 21 controls this priority output operation.
2, and the code determination circuit 212 selects the latch.

Next, the operation of encoding the first line image 402 in FIG. 4 will be described.

First, in this embodiment, at the time t□ shown at 320 in FIG.
Let be the encoding start time.

That is, at time t□, the first pixel of the reference line and coding line is C of the C register 110 in FIG.
4 output or the A4 output of the A register 108, respectively.

That is, at time 1 (, the outputs of the C register 110, B register 109, and A register 108 are reference
The states of the first pixel of the line and coding line and the three pixels following the first pixel are output in parallel. Also, aQ
is the initial value 1 as shown in 221 AO (ao) in Figure 3.
10” (white pixel = virtual).

The run range counter 203 starts from the initial value 0 at time t□
Thereafter, the image clock 134 starts counting.

The count value output of the counter 203 at each time is
It is shown at 322 in the figure.

At time to, the signal 129-4 in FIG.
In other words, there is no change point in the A4 output of the A shift register 108 in FIG. 2, and similarly, there is no change point in the B4 output of the B shift register 109. Therefore, since there is no cause for generating a code, the count value of the run-length counter is simply incremented by 1 and the process advances to the next time t1, but the state at time t1 is the same as that at time t□.

Next, when proceeding to time t2, the signal 129-4 in FIG.
” is set. This means that A register 1 in Fig. 2 is set.
The A4 output of 08 becomes 1, indicating that a change point exists at that position on the coding line. Since this change point is the first change point to the right of the current starting point aQ (corresponding to a later time), the symbol detection circuit 201 in FIG. 2 determines that it is the symbol a1.

Note that the detection state of this symbol a1 is stored as Fal.

At this time t2, 130-1 to l3 in FIG.
Looking at 0-4, "11 II" is not set in any of them. This means that there is no change point bl within 3 times from time t2. Also, the symbol detection circuit 201 has detected bl. Sometimes, the BL is shifted into the B shift register 202 so that it does not disappear for three hours.

The symbol detection circuit 201 also has a circuit for storing that bl has already been detected. ``Thus, in this case, it can be determined that there is no change point pixel bl within three pixels to the left and right of the change point pixel a1, and that there is no change point pixel bl between the starting point aQ and al (therefore, b2 is also absent). Therefore,
al was detected at time t2, but in P mode (b2 must have already been detected) and V mode (lat
It is determined that the condition bt1w3 is not satisfied, and therefore the mode is set to H mode.

At this time, the value of the run-length fist counter 203 indicates the number of pixels from aO to al, as shown in Fig. 322 of f53, and “
It is 2'. Also, the run length color is initially set °
“0” = remains white. Therefore, the run length value, color, etc. are given to the ROM table C 206 by the output 228 of the run length counter 203, and the corresponding code and code length are output from the ROM 206. In this case, the code of “white run 2°” is output, that is, M (a
oal)=white 2.

At this time, it is determined that it is the first code of H mode, and H
The code indicating the mode “001°° is the code for white run 2”
It is controlled to be output at the same time as "oiii", that is, in one clock. Further, the code length is also output as a binary number or the like at the same time.

Next, the run length fist counter 203 is set to an initial value of 1 (0
(Note that this is not the case.) and moves on to counting from pixel a1 to pixel a2. However, pixel a1, that is, time t2
Then, only preparations for setting the initial value are made, and the initial value is set in the counter and the count is started from the next time t3. Furthermore, from this time t3, the color of AO is also inverted.

(Time t2 mi° “0”→Time t3=゛l”) From then on, when time 1. advances, eventually at time t4, the A register 108
A change point appears at the A4 output of ``l''. The symbol detection circuit 201 remembers that the change point a1 has already passed and been detected (Fal=1).
Therefore, the symbol detection circuit 201 determines that it is a2. Note that this detection state of a2 is stored as Fa2. Now, at time t4, the value of the run-length counter 203 is 2, and AO = '1' = black.Also, since it has already been determined that it is in H mode at time t2,
When a2 is detected, the state of the reference line,
That is, 131-1 to 131-4 in FIG. 3 and 13 in FIG.
References to 0-1 to 130-4, etc. are unnecessary, and even if bl, b2, etc. are present on the reference line, although this is not the case, they are controlled to be ignored.

As a result of the above, M(al, a2)=black "2" code and hicoat length are output in the same way as for M(ao, ax). At this time, unlike the case of M(ao, al), the code "'001" indicating the H mode is not added.

Next, after time t4, ie, at time t5, the run-length counter 203 is set to the initial value 1. or,
AO (=a□) is inverted.

Then, the change point a2 at time t4 is the starting point aQ of the next mode.
considered to be.

Through the above operations, the code generated by encoding the first line 402 becomes as shown at 501 in FIG.

Also, at time t30 in FIG. 3, the run-length counter value is 9, and at this time, the symbol cft (=at) is detected, but there is a change point b'1 after two pixels on the reference line. At time t30, the B register 10 in FIG.
9 output 130-2 and C register 110 output 131
-Judged from 2nd grade. Therefore, the condition 1albll<3 is satisfied, and since it is not P mode (b2 is required), it is determined to be V mode by definition, and VL (2) code (al
is located two pixels to the left of bl) is output.

At this time, the H mode run length/white 9 code could have occurred, but according to the definition of priority between each mode mentioned earlier, the ■ mode became the valid code, and the H mode code becomes invalid. Due to the occurrence of the Zara V mode code, the run length counter 203
The count value up to time t30 is cleared and controlled to be newly preset to 1. Further, after the code of the ■ mode is generated, the color of the starting point aQ symbol is inverted. (However, the ■mode code is generated at the same time as the change point detection of the a1 symbol (time E30).)Also, although it has not been explained so far, if the symbol b1 is detected before the symbol a1 , the detection signal of symbol b1 is shifted into the register as input number 4g to the B register 202, and for three time periods thereafter, the B register 202 output, B
It shifts in the order of 5 → B6 → B7, and disappears after that. Further, when the code b1 has already passed through the B4 output of the B register 109 but no code is generated yet, this fact is stored as shown by the output Fbl of the storage detection circuit 201.

Next, specific circuits of each functional block of the circuit block shown in the first diagram will be explained.

The virtual change point generation circuit A101 and the virtual change point generation circuit B105 in FIG. 1 are circuits of the same type, and are both realized by the virtual change point generation circuit shown in FIG.
is a flip-flop, 703 is an AND gate, 704 is an agate, and 705 is an inversion circuit (inverter).

The operation of the circuit shown in FIG. 7 is shown in the timing chart of FIG. 8. That is, the numbers of the parts in FIGS. 7 and 8 correspond to the numbers in FIGS. 1 and 3. However, Fig. 7 and Fig.
A signal 701 in FIG. 8 is a signal indicating the position (timing) of the last pixel in one line obtained by decoding the count value of the memory address counter 111 shown in FIG. 1, for example. That is, at the time when the signal 701 is generated, the flip-flop 702 is set to the same color as the last pixel of the coding line in synchronization with the clock 134, and after that time, that is, after the horizontal synchronization signal 136-2 is deenergized, the flip-flop 702 is The Q output of 122 is the 122 signal, and before that time, while the horizontal synchronization signal 136-2 is being output, the image 12
1 to the 122 signal.

The selector 104 in FIG. 1 is realized by the circuit shown in FIG. 9, in which 902 is an AND gate, 903 is an OR gate, and 904 is an inverter. 123,1 in Figure 9
24 is the output 12 of the line buffer memories A and B in FIG.
3°124, but the signal 901 in FIG.
This is a select signal whose level is inverted for each line, and is generated by the horizontal synchronizing signal 13B-2 in FIG. The output to signal 125 is switched by the select signal 901.

Change point detection circuit A106 and change point detection circuit B in Fig. 1
Reference numeral 107 designates a circuit of the same type, and FIG. 10 shows a typical configuration of the change point detection circuit B107. In the figure, 1002 is a flip-flop, 1003 is an exclusive OR gate, and 100
4 is an inverter.

That is, as shown in the timing chart of FIG.
By taking R), it is detected that the colors of adjacent pixels are different, and this is used as a change point signal.

Next, specific circuits of various functional blocks in the circuit block of FIG. 2 will be explained.

FIG. 11 is a circuit for detecting the FAL signal indicating that the symbol a1 or a2 on the coding contest line and the previously mentioned al have been detected, and is the symbol detection circuit 2 shown in the second diagram.
In the 0 diagram in 01, 1102 is a flip-flop, 1
104 is an AND gate, and 1105 is an IN gate.

Now, the numbers of each part in FIG. 11 correspond to the numbers in FIG. 1, etc. The signal shown at 1101 in FIG. 11 returns the flip-flop 1102 to its initial state (i.e., Q output =
This is a control signal that prohibits the Q output from being set to "0°" or "1", and is normally at the "l" level.

The same applies to the RESET signal 1103. Here, when the change point A4 (129-4 signal) arrives first, A4
= “1”. In this case, flip-flop 1102
Q output = 111 II and control signal 1101 = “1
”, so a 1 = “1” is output,
Symbol a1 is detected. This a1 detection signal sets the flip-flop 1102 so that Q output = "t", and al stores the already detected car (that is, Q output =
Fa1= “l”), then A4=II in this I) state
When I II, a 2 = "1" and symbol a2 is detected.

Next, a circuit for detecting symbols bl etc. is shown in FIG. In the figure, 1201 is an exclusive OR gate, 1202.12
03 is a flip-flop, 1204 is an AND gate, 1
205 is an inverter. The number of each part is numbered 11th.
This is the same as the case shown in the figure. However, aQ can be bl.
Due to the condition that the color is opposite to that of , the circuit uses the signal after taking the exclusive OR of the change in the reference line and the a0 times signal in step 1201. The circuit shown in FIG. 12 is included in the symbol detection circuit 201 shown in FIG.

The specific configuration of the run length counter 203 in FIG. 2 is shown in FIG. (decimal) to 25
60-1 (2559 in decimal), and the counter 203 has a preset function, a clear function, etc.
C, type name 74F163, etc.

Furthermore, the count value output of the counter 203 is 1O base 2
559 and generates the MKI signal.
301 and the value obtained by decoding the lower 6 bits of the output is 1
The circuit 1302 detects that the decimal number is "63" and generates an MK2 signal.

Furthermore, the value set by the preset function is “0”.
(decimal number) or "1°' (decimal number) can be selectively preset.

The movement force of the run-length counter 203 will be explained. First, preset (or clear) the initial value "0°°" at a position outside the left edge of the image for each coding line.
In the zero-order image area, the count is sequentially advanced pixel by pixel, but in the following values or three states, the counter 203
is returned to l'' by the preset function.

That is, (1) when the change point a1 or a2 is detected, (2) when the count value reaches 2559, (3) when a P mode code or V mode code is generated, however, the encoding method According to the rule, if the change point a1 is set to a2 on a virtual pixel outside the rightmost end of the coding line, the counter value is returned to "0'' when al is detected.

Next, the configuration of the ROM table A204 in FIG. 2 will be described. The ROM table A204 is used to generate a total of eight types of codes, P mode and V mode, and the code lengths. As is clear from the configuration principle of this embodiment and the above explanation, the configuration described here is based on the relative relationship between the changing point positions of the coding line and the reference line, and especially when the changing point b2 on the reference line is in the B register 109. or when the change point a1 on the coding number appears as the A4 output of the A register 108, the state of the symbol detection circuit 201 and the A register 108, B register 109 . The configuration is such that the status of each output of the C register 110 and the B register 220 can be determined simultaneously and in parallel. Therefore, the combinations of the states of the above-mentioned request forces are naturally finite, and at the time when one judgment is to be made, it can be treated as a stationary state. Therefore 1
Since the P mode or V mode code and code length to be output for each combination can be determined, it can be configured as the ROM table.

Since the specific contents of the ROM table are too redundant here, as an example, FIG. 14 illustrates a case where a P mode code and code length are generated by a logic circuit equivalent to a ROM. In the figure, 1409 is an inverter, 1410 is a timing circuit, 1411 is a Nant gate, and 1412 is a NOR gate. That is, 140 in FIG.
The signal indicated by 1 is a signal indicating that the symbol detection circuit 201 in FIG. 2 has detected the change point b2 on the reference line.

That is, this means that the B4 output of the B register 109 in FIG. 1 has a changing point as b2. Similarly, the a1 signal indicated by 1402 in FIG. 14 is the a1 change point as the A4 output of the A register 108 in FIG. Furthermore, the Fa1 signal shown at 1403 in Fig. 14 has reached the second level by the current time.
This is a signal indicating that the graphic symbol detection circuit 201 has already detected the change point as al.

The logic circuit in FIG. 14 means that at the time when b2 is detected, the signal al or Fa1 is not "true °°, so it is determined that the mode is P. That is, the starting point ao
After that, it means that there is no a1 change point by the time when b2 is detected. That is, on the image, from the starting point aQ to b2
This means that there is no a1 change point directly below the change point.

Therefore, by definition, it is in P mode. 140 in Figure 14
4 is a P mode detection signal, 1405 is a specific code of P mode, and 1406 is a binary number representing the code length of the P mode code. Further, 1407 is a signal indicating that a P mode code has been generated. The above is the determination method for P mode, but the same method can also be applied to ■mode. The ROM table A204 is configured by this method.

After all, the code and code length of the P mode or V mode are determined by applying the status signals of each register etc. as input data to the ROM table A204 in FIG. 2 based on the above method at the time when the b2 or a1 symbol is detected. Depending on the event, the signal is generated immediately in one clock time.

ROM table B2O5 and ROM table C in Figure 2
Since 206 has a similar structure, the ROM table C 206 will be explained with reference to FIGS. 15 and 16 as a representative.

First, 206 is a ROM with at least 11 bits of address input and 21 bits of parallel output;
The human power corresponds to the 228 signal in FIG. That is, they are the lower 6 bits of the run length counter 203 in FIG. Further, 1502 manual input in FIG. 15 is a signal specifying the color of the run length, and in this example, white=O1 black=1.

Also, 1503 human power is a code indicating H mode (=001
) is added or unnecessary. In this example, it is required =
1. Unnecessary=O. That is, when the 1503 manual power is 1, the run length code of the H mode code generation method plus the code (OO1) is output in one clock. A chip enable signal 1504 controls whether the output of the ROM 206 is enabled or disabled. 15
07 Manpower is EOL<1507 Manpower is EOL+1.150
8 are address inputs that control the reading of each of EOL+O, and by inputting pulses to these inputs, the delimiter code of the corresponding line is read. Also, the code 505 is the code output of the address specified by the input, and is 15.
Similarly, 06 is the code length of the code.

FIG. 16 is a diagram showing the correspondence between the addresses AO to AIO in FIG. 15 and the stored contents (data).

The code determination circuit 212 of FIG. 2 is specifically explained with reference to FIG. 17. In FIG. 17, 1706 is an AND gate;
is an inverter.

As can be seen from the principle of the code generation method in this example,
ROM table 204 and 205 or 206 shown in the second diagram
etc., P mode.

In the stage before each mode and H mode code is finally determined as the code to be generated, two or more codes may be output from the ROM table at the same time. However, the priority of two or more codes is defined as described above.

FIG. 17 shows a circuit for determining the code to be uniquely generated according to the definition.

That is, if the P mode, ■mode, and H mode codes can occur simultaneously, as described above.

P mode>■mode>H mode According to the order of priority, the code of the mode that has acquired priority is finally determined as the code to be generated, and the codes of other modes are invalidated and do not become one generated code.

Note that the signal 1708 is a mode signal for selecting whether to use this encoding circuit for the MH method, that is, -dimensional encoding, or for two-dimensional encoding of MMR or MR, and executes -dimensional encoding. When performing two-dimensional encoding, the level is L. On the other hand, when two-dimensional encoding is performed, the level is H.

Therefore, when performing -dimensional encoding.

The generation of P mode codes and V mode codes is prevented,
Only the H mode code, that is, the code representing ten length, is always valid.

Next, the roles of the latch A207, latch B2O3, etc. in FIG. 2 will be described. Latch A207 and latch B20
g is a circuit for temporarily storing the H mode make-up code and the code length that are generated during coding until it is determined whether the H mode is valid or invalid. If it is determined that the H mode is valid, the contents of the latch are transferred to the next stage circuit.

Taking the functions of the latches A207 and B2O3 in FIG. 2 as an example, a case where the run length in which the make-up code is generated is long will be explained, for example, with run length=2972. At this time, according to the encoding regulations, the code is divided into a total of three run-length codes, two make-up codes and one terminating code, and output as follows.

That is.

Makeup code l = Run length 2560 code (common for white and black) Makeup code 2 = Run length 384 code (white or black) Terminating code = Run length 28 code (white or black) Like this, 2560 + 384 + 28 = 2972 When one run length is represented by multiple codes, as in the case of , first, the count value of the run length counter 203 in FIG. 2 is 63+64XN (N=0.1.2...
If the A4 output of the A register is not at the a1 change point at that point, it is predicted that a make-up value will occur next, and the value of the upper 6 bits of the counter 203 (N is a positive integer) is predicted. ROM the makeup code and code length of the one above (i.e. 64 makeup with N=0) indicated by
The contents of the latch B2O3 are outputted from the table B2O5 and temporarily stored (latched) in the latch B2O3.Then, each time the previous value count value advances by 64 (that is, each time N advances by 1 in the above-mentioned formula 63+64XN), the contents of the latch B2O3 are as follows: It will be updated.

Then, the value of the run length counter 203 is 2559.
(In other words, if the change point a1 is not detected at the time when N = 39 in the formula 63 + 64 Read the code and code length of 2560 and latch A2.
Temporarily stored in 07. At the same time, the stored contents of latch B2O3 are temporarily invalidated. Further, the count value of the run length counter 203 is returned to the initial value l. Subsequently, as the count progresses, storage of the make-up code, etc. to the latch B20 is resumed in the same manner for each hole of 63+64XN described above.

When the change point a1 is detected, the competitive relationship with other P mode or V mode is determined, and when the H mode is determined, the ten length counter 2 at the time of the change point a1 is determined.
The termination code and code length of the run length indicated by the value of the lower 6 bits of 03 (0 to maximum 63) are temporarily stored in the launch C209. Furthermore, as described above, the contents of latch A207 and latch B2O3' also become valid.

However, if V mode etc. occurs at the time of change point a1, H mode itself will not occur, and naturally latch A20
7 and the contents of latch B20B are invalidated, and the contents of latch C
209 instead of the above-mentioned terminating code.
Mode code is latched as valid code.

Makeup code 1 and makeup code 2 above
FIG. 18 shows a circuit for controlling the generation and storage of the data, etc., and this circuit is included in the timing circuit 112. Timing chart of this circuit (run length is as shown above)
2972) in Figure 19, 18
01.1802 is a flip-flop.

1803 is an AND gate, and 1804 is an inverter.

MKI and MK2 are signals output from the 2559 detection circuit 1301 and the 63 detection circuit 1302, respectively, of the run length counter 203 shown in FIG. The flip-flop 1802 is set by the input of the MK2 signal to generate the MK2K2 signal, and the flip-flop 1801
is set by the input of the MKI signal and generates the MKI presence signal. Note that the flip-flop 1802 is reset by inputting the MKl signal.

With the above configuration, the run length counter 203
When the count value becomes 64 or more, the MK2K2 signal is at level, and when it becomes 2560 or more, the M
Only the KI presence signal or the MK2K2 presence signal or the K2K2 presence signal becomes high level. The levels of the MKI presence signal and MK2 signal determine whether the code representing the run length is only a termination code or a combination of a termination code and a makeup code, and whether the number of makeup codes is 1 or 2. You can determine if there is. Therefore, H
When generating a code in this mode, the backing circuit 211 determines the levels of the MK1 present signal and MK2K2 present signal, selects the valid one among the three latches A, B, and C, and takes in the latch data. .

In this way, when the make-up code is generated, by predicting the generation of the code at least one time in advance and sending the code to the temporary memory circuit (latches A and B), the change point a1 can be predicted. This is extremely effective in circuit configuration since it has the effect of preventing an increase in the number of output codes and the number of bits to be processed at the same time.

That is, by temporarily storing the required make-up code and code length among the numbers counted by the latch A 207 and latch B 20g run length counter 203 before determining the H mode, the terminating code and code length are stored when the H mode is determined. Since only the code length needs to be processed, all the H-mode codes to be output at the time of a1 detection are available, and the subsequent encoding operation can be executed without delay.

207. Each latch A, B of 208, 209.

The order in which the contents of C are sent to the next stage circuit is latch A207>
Controlled to maintain the order of latch B2O3 > latch C209 (210 buffers) (omitted when the contents are invalid,
ignore).

The reason why the contents of the latch C209 are temporarily stored in the buffer memory 210 is because the next encoding operation starts from the next time when the encoding mode is determined.

The next encoded data from the ROM table is latch C209.
may be input in several clocks (minimum Eflock). Therefore, after the mode is determined, the contents of latch C209 are stored in the buffer memory 2 so that the next encoded data can be latched.
10, and is outputted to the subsequent stage from the buffer memory 210 with timing.

Next, a special case in which the change point a1 and the change point a2 are set on the same pixel according to the encoding method will be described.

FIG. 20 illustrates the above case. That is,
In Figure 20, 2001 is the reference line, 2
002 is a coding line. Further, 2003 is the final pixel of the coding line, and 200.4 is a virtual change point (pixel).

Now, in Fig. 20, if the starting point ao is at the position shown in the figure as a result of encoding from the left, the next code to be generated is as shown in Fig. 21: [H mode code + white 12 terminator code + black O-terminated code]. Here, the code in FIG. 21 (1) can be treated as one code at the time of the change point a1 by the above-mentioned means, and there is no problem. However, the code in FIG. 21 (2) originally has the change point a2.
This is the code that should be generated at the time of the change point a2 when the change point a1 comes at a different time. But in this case.

It is clearly not detected as the change point a2 by the symbol detection circuit 201 or the like.

Therefore, in this case, the following processing is performed by the circuit shown in FIG. 22 provided in the symbol detection circuit 201. FIG. 23 is a timing chart of the operation of this circuit. In FIG. 22, 2201 is a signal indicating that the image has entered the virtual area (
2202 is an a1 change point detection signal, and 2203 is a signal indicating up to the generation of the first termination code in H mode. The signals 2201 to 22 are monitored by the AND gate 2207.
Detect the state in Figure 20 by taking the AND of the 03 signals, create the 2204-1 signal (that is, the time is the same as al), and first output the code in Figure 20 (1) using the method described above. After performing predetermined processing such as clearing the run length counter to O, the signal 2205-1 in FIG. 21 is generated by delaying the signal 2204-1 in FIG. 2) Generate the black O termination code.

The backing circuit 211 in FIG. 2 receives as input the code and code length obtained by the method described above, and the length of each code (the number of bits of the code) generated by this division is not constant, however, the longest one is H Even if a mode code (=001) is added, the number of bits is 16 bits).This is a circuit that sequentially collects data in units of 16 bits, and on the Kinotsu side, it passes each 16 bits in parallel to the next external circuit. It is.

The signal 238 in FIG. 2 is a code compiled into 16 bits by the backing circuit 211, and the signal 239 is a signal for reporting this fact to the next stage external circuit. Note that the backing circuit 211 is a code length addition circuit and a bit shifter.

This can be easily realized by combining well-known circuits such as multiplexers and latches.

Next, there is an RTC (Re turn) indicating the end of one page.
The To Control) signal will now be described. MM
In the case of the R method, RTC code=EOL code×2 times.

That is, the RTC signal is (000000000001)X2=
000000000001.000000000001
It is expressed as Also, in this embodiment, as described above, the structure is such that up to 16 bit codes can be output in one clock time. Therefore, in order to output the RTC signal, the end of one page is detected by monitoring the vertical synchronization signal 136-1 shown in FIG. By giving the address signal 1507 of the ROM table 0206 (shown in FIG. You can get it next.

Next, Table 1 lists the differences between the three encoding methods described above.

Therefore, the encoding method of the MH method is almost the same as the case where the H mode of the MMR method described above is repeated, but differs in the following points.

That is, (1) the H mode code (OO1) is not required in the MH method (2) it is not necessary to pair white runs and black runs in the MH method (3) an EOL code is inserted for each line in the MH method (4) Differences in RTC and in the case of the MR method: (1) One-dimensional lines are the same as the MH method (2) Two-dimensional lines are the same as the MMR method (3) Line separation is EOL + 1 = OOO0000000011 or EOL + 0 = 0000000000010 (4) R.T.C.
Difference (5) Due to the K parameter, one-dimensional lines and two-dimensional lines coexist.

After all, switching between the three encoding methods can be easily realized by controlling the operation of the circuit for the MMR method described above using a method selection signal for the MR method or the MH method.

First, Figure 24 shows an example of a circuit that controls the differences between lines, delimiters, and codes. In Figure 24, 2407 is a line counter;
408 is Nantes Gate, 2409 is And Gate, 24
10 is an inverter. That is, 2401 in FIG. 24 is the pulse signal at time t1 shown in 320 in FIG.
It is repeated for each coding line, and at time t-1, no code is generated due to image encoding.
The pulse signal at one time is obtained by decoding the value of the address counter 111. Also, 2402 and 2403
is an encoding method selection signal from outside the circuit of this embodiment, such as a CPU, which specifies the encoding method. Also, the 136-2 signal corresponds to the 136-2 signal in FIG.
7 is a signal 136- indicating how the parameters advance in the MR method.
2 is counted and monitored as a line counter.

Signals 2404 to 2406 obtained by the logic in FIG.
was used as the address input for the ROM table 0206 in Figure 2 (1507 to 1508 in Figure 15), each specifying a specific address, and the code and code length required for the specific address were stored. By outputting something, you can get the desired line, break, or code.

Furthermore, the one-dimensional line encoding method of the MH method is described in the 17th
In the mode determination circuit of the MMR method shown in the figure, control may be performed using the 1 selectivity number 170g so that the H mode can always be prioritized.

Also, in the MH method, the H mode code (0'01) is always
This is also achieved by setting the address signal A7 of the ROM table 0206 to 0.

Also, the difference in the number of EOLs in RTC is ROM table 0.
This is achieved by varying the number of pulses applied to 206 depending on the mode.

In this embodiment, as shown in FIG. 3, etc., it operates in synchronization with the (image) clock 134, but it is not related to the interval (period) of the clock. Therefore, as shown in Figure 25,
A pause period can be easily provided between images or lines by masking the clock 134 with an image gate signal, so to speak.

That is, in FIG. 25, 2501 is the image gate signal "0".
This is a signal indicating that the operation is suspended for one level.

Further, 2502 is the gate signal 2501 and the clock 134.
If this clock 2502 is sent to the actual internal circuit of this embodiment in place of the aforementioned clock 134, the state of this embodiment can be changed only by the clock signal. Therefore, the shaded area in FIG. 25 clearly indicates the weight state.

With this pause control, for example, the output speed of the image signal from the source of the image signal to be encoded is not limited by the operation of the encoding circuit. Conversely, even if the image signal of one page is output intermittently, for example, when the image source is an image file with a disk, the encoding circuit will not be able to synchronize with the intermittent output. Encoding operations can be performed intermittently. Therefore, the image signal from the output source can be sequentially encoded without requiring a large buffer memory for time adjustment between the image signal output source and the encoding circuit.

Next, a method of supplying images to be encoded to the circuit of this embodiment in parallel format will be described with reference to FIGS. 26 and 27. That is, 2601 in FIG. 26 is a parallel-to-serial change shift register that can input 8-bit parallel data and output it to 2602 as 1-bit serial data.

As shown in FIG. 27, after loading the image signal to be encoded into the register 2602 as 8-bit parallel data,
The signal is serially shifted by a clock, and a serial image signal 2602 as shown in FIG. 27 is obtained. At the same time, the number of clocks during the serial shift is counted to generate a gate signal 2702 indicating the section of the actual data, and a clock 2702 corresponding to the actual data can also be obtained in the same manner.

As described above, the signals shown in FIG. 27 are in a format that can be encoded as described above in this embodiment by the method 1) described in FIG. 25. The operation for parallel input of this image is C
This is extremely effective when an image is provided by pu or the like.

In the above embodiments, MH, MR, and MMR encoding has been described, but it goes without saying that other encoding methods can also be applied. The encoded code is input from a digital reading device, a computer, etc., and the encoded code is transmitted to a remote location via a transmission line or the like, or is stored in an image file. Although the present invention has been described above based on preferred embodiments, it goes without saying that the present invention is not limited to this configuration, and that various modifications and changes can be made within the scope of the claims.

Table 1 [Effects] Theory (9I) According to the present invention, multiple codes for the same pixel are output separately, which reduces the burden on the encoding operation caused by generating multiple codes. , efficient encoding operation can be achieved.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the configuration of an encoding device to which the present invention is applied, FIG. 3 is a timing chart showing the encoding operation, and FIGS. 4, 5, and 6 are reference line 7 is a diagram showing a configuration example of a virtual change point generation circuit, FIG. 8 is a timing chart diagram showing the operation of the circuit shown in FIG. 7, and FIG. 9 is a configuration example of a selector. 10 is a diagram showing a configuration example of a change point detection circuit, FIGS. 11 and 12 are diagrams showing a partial configuration example of a symbol detection circuit, and FIG. 13 is a diagram showing a configuration example of a run length counter. 14 is a diagram showing a configuration example of an equivalent circuit of ROM table A, and FIG. 15 is a diagram showing a configuration example of an equivalent circuit of ROM table C.
FIG. 16 is a diagram showing an example of the contents of ROM table C, FIG. 17 is a diagram showing an example of the configuration of the code determination circuit, and FIG. 18 is a configuration example of the make-up code generation and storage circuit. 19 is a timing chart showing the operation of the circuit shown in FIG. 18, FIG. 20 is a diagram showing the relationship between the beam reference line and the coding line, and FIG.
Figure 22 is a diagram showing a configuration example of a delay circuit at a virtual change point, Figure 23 is a timing chart diagram showing the operation of the circuit shown in Figure 22, and Figure 24 is a diagram showing control of generation of line separation codes. Diagram 25 showing an example of the configuration of a circuit for
26 is a timing chart showing a pause control operation of the encoding operation, FIG. 26 is a diagram showing a configuration example of a circuit that serially outputs parallel input of an image signal, and FIG. 27 is a timing chart showing the output state of the circuit shown in FIG. 26. It is a chart diagram, and 10
1 and 105 are virtual change point generation circuits, 106 and 107
is a change point detection circuit, 108 to 110 are registers, 111
is an address counter, 201 is a symbol detection circuit, 203 is a run length counter, and 207 to 209 are latches. Applicant: Canon Co., Ltd. Figure 7: 8a Figure 2 Figure angle %lQ Figure Yu // Figure 75 Figure 7 U

Claims (1)

[Claims] means for serially capturing the image signal of the reference line in synchronization with the serial input of the image signal of the encoded line; means for counting the number of pixels between change points of the encoded line; means for monitoring the correlation of line image signals and determining an encoding mode; and means for generating an encoding code based on the count of the counting means, and the horizontal mode is determined by the determining means; When a plurality of encoded codes are generated for the same pixel, the first encoded code to be generated is outputted corresponding to the pixel, and the encoded codes following the output are outputted. Two-dimensional encoding device for image signals.