JP2701567B2 - Field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a field effect transistor (FET) using a quantum wire as a channel,
In particular, the present invention relates to an epitaxial layer structure capable of improving its performance.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional quantum wire FET. 2A is a structural view of the element, FIG. 2B is a sectional view of the element on a plane (X1-X2-X3-X4) including the gate electrode, and FIG. It is sectional drawing of a superlattice layer. Such quantum wire FETs were manufactured by Tsubaki et al. In Electronics Letters.
cs Lett. ), Vol. 24, No. 20, 1267
Page, 1988. This FET comprises a semi-insulating (SI) GaAs substrate 1, a non-doped GaAs layer 52 constituting a buffer layer, an in-plane superlattice layer 54, and an n-type AlGaAs layer 56 serving as an electron supply layer.

Here, as the GaAs substrate 1, [1-1]
Using a (001) GaAs substrate inclined by 1 ° in the [0] direction and using a metal organic chemical vapor deposition (MOCVD) method, a non-doped GaAs rod 54A and a non-doped AlAs rod 54B are alternately formed. A grid 54 has been made. A cap layer 7 made of n-type GaAs is formed on the electron supply layer 56, and a source electrode 8S and a drain electrode 8D are formed on the cap layer 7 by vapor deposition to make ohmic contact with the channel.
A gate electrode 9 is formed in a recess formed by removing the cap layer 7.

[0004]

FIG. 6 shows a potential profile in the direction from the substrate to the gate electrode of the conventional quantum wire FET shown in FIG. FIG. 6 (A),
(C) is on the line including the AlAs rod 54B (FIG. 5 (B)
Are the potential profiles at the time of low electron density and at the time of high electron density in Y1-Y2). FIGS. 5B and 5D show potential profiles at the time of low electron density and at the time of high electron density, respectively, on a line including the GaAs rod 54A (Z1-Z2 in FIG. 5B). In FIG, E _C is the bottom, E _F of the conduction band is the Fermi level, n represents an electron density distribution. Under the condition of high electron density, as shown in FIGS. 6C and 6D, the electrons approach the vicinity of the hetero interface, so that the electrons are localized toward the GaAs rod 54A and a one-dimensional electron gas is formed. You. On the other hand, under the condition of a low electron density, as shown in FIGS. 6A and 6B, the confinement is reduced, and the electrons travel in the buffer layer 52 and behave as a two-dimensional gas.

As described above, the conventional quantum wire FET
Shows a good electron transport characteristic with a one-dimensional carrier at a high current, but shows the same characteristics as a conventional two-dimensional electron gas FET (2DEGFET) at a low current. In general, when an FET is used as a high-frequency low-noise element, a high transfer conductance (g _m ) at a low current is indispensable. There was a problem that was not reflected.

[0006] The present invention provides an epitaxial layer structure capable of maintaining one-dimensional confinement of carriers even at a low current and exhibiting good electron transport characteristics by changing the epitaxial layer structure of the quantum wire. It is.

[0007]

SUMMARY OF THE INVENTION A field effect transistor according to the present invention comprises, on a semiconductor substrate, a rod made of a first semiconductor material and a second semiconductor material having an electron affinity smaller than that of the first semiconductor material. An in-plane superlattice layer in which rods are alternately arranged and an electron supply layer made of a third semiconductor material doped with an n-type impurity are sequentially stacked, and electrons are emitted in a longitudinal direction of the rod made of the first semiconductor material. In the field effect transistor to be run, a hetero buffer layer made of a fourth semiconductor material having an electron affinity smaller than that of the first semiconductor material is formed on a side of the in-plane superlattice layer opposite to the electron supply layer. It is characterized by the following. Furthermore, in the above-mentioned field effect transistor, a non-doped channel layer made of a fifth semiconductor material having a higher electron affinity than the third semiconductor material is inserted between the in-plane superlattice and the electron supply layer. And

[0008]

In the conventional quantum wire FET, under the condition that the electron density is low, the quantum wire FET seeps into the electron buffer layer and the one-dimensional confinement cannot be maintained. In the present invention, the provision of the hetero buffer layer on the side of the in-plane superlattice layer opposite to the electron supply layer suppresses seepage of electrons into the buffer layer.
By doing so, it can be seen that one-dimensional confinement is realized even at a low current, and good noise characteristics are exhibited with improvement in electron transport.

However, in such a structure, electrons always behave as a one-dimensional gas regardless of the electron density. Therefore, not only under the gate, but also between the source and the gate and between the drain and the gate, the electrons travel only in the GaAs thin wire, and the source parasitic resistance and the drain parasitic resistance increase. Ideally, one-dimensional electron confinement is realized only under the gate, and the other parasitic region behaves as a two-dimensional gas. In order to satisfy this requirement, a first channel layer on which a quantum wire is formed and a second channel layer in which electrons behave as a two-dimensional gas are provided, and where a negative voltage is applied to the gate and the electron concentration is reduced. Only the electrons may be confined in the first channel layer. Specifically, in the structure described above, a non-doped channel layer may be provided at the interface between the electron supply layer and the in-plane superlattice layer. As a result, as the electron concentration decreases as a negative voltage is applied to the gate to lower the electron concentration, the electron distribution moves away from the gate and approaches the substrate side, so that the electron distribution is confined to the quantum wires constituting the in-plane superlattice. On the other hand, in a parasitic region having a high electron concentration, electrons are two-dimensionally distributed in the upper non-doped channel layer, so that an increase in parasitic resistance is suppressed.

[0010]

FIG. 1 shows an element structure of an FET according to a first embodiment of the present invention. 2A is a structural view of the element, FIG. 2B is a sectional view of the element on a plane (X1-X2-X3-X4) including the gate electrode, and FIG. It is sectional drawing of a superlattice layer. On a semi-insulating GaAs substrate 1, a non-doped GaAs buffer layer 2, a non-doped AlGaAs hetero buffer layer 3, an in-plane superlattice layer 4, a non-doped AlG
An aAs spacer layer 5, an n-type AlGaAs electron supply layer 6, and an n-GaAs cap layer 7 are formed.

FIG. 2 shows a potential profile of the quantum wire FET shown in FIG. 1 in the direction from the substrate to the gate electrode. FIGS. 2A and 2C show AlAs rods (4
It is a potential profile at the time of low electron density and at the time of high electron density in (Y1-Y2) on the line containing B), respectively. FIGS. 7B and 7D show potential profiles at the time of low electron density and at the time of high electron density, respectively, on the line (Z1-Z2) including the GaAs rod (4A). In the figure, the bottom of the E _C conduction band, E _F is the Fermi level, n represents an electron density distribution. As shown in FIG. 2, regardless of the electron density, electrons are confined in the in-plane superlattice 4 by the effect of the hetero buffer layer 3 and the GaAs rod 4
A one-dimensional electron gas is formed in A. As described above, in the quantum wire FET according to the present invention, not only at the time of high current but also at the time of low current, the one-dimensional confinement of carriers is maintained, and the electron transport characteristics are improved. Therefore, g _m at low current is improved as compared with the conventional FET, especially high frequency noise characteristics are improved.

Such an element is manufactured as follows. (001) GaAs inclined by 1 ° in the [1-10] direction
For example, a non-doped GaAs buffer layer of 1 μm and a non-doped Al _0.3 G
A _0.7 As hetero buffer layer 3 is sequentially grown to 500 Å (hereinafter referred to as A). Here, since a substrate inclined by 1 ° is used, 162 A
Periodic steps occur. According to this step, Al
By growing the As and GaAs alternately plane superlattice layer _{(GaAs) 0.5 (AlAs) 0.5} 4 to 150A
Only form. Subsequently, the non-doped AlGaAs spacer layer 5 is 30 A, the n-type Al _0.3 Ga _0.7 As electron supply layer (doping concentration 3 × 10 ¹⁸ / cm ³ ) is 270 A,
n-type GaAs cap layer (doping concentration 5 × 10 ¹⁸ /
cm ³ ) 7 on the n-type GaAs cap layer 7 to be sequentially grown to 500 A.
Is formed by vapor deposition, and an ohmic contact is made by alloying. Here, a source electrode and a drain electrode are arranged on both ends of a semiconductor rod forming an in-plane superlattice. Further, a gate electrode 9 is formed in a recess formed by removing the n-type GaAs layer 7 by etching. Thus, the FET of FIG. 1 is completed.

FIG. 3 shows an element structure of an FET according to a second embodiment of the present invention. FIG. 1A is an element structure diagram, and FIG. 1B is an element cross-sectional view along a plane (X1-X2-X3-X4) including a gate electrode. On a semi-insulating GaAs substrate 1, a non-doped GaAs buffer layer 32, a non-doped AlGa
As hetero buffer layer 33, in-plane superlattice layer 34 forming a first channel, second channel layer 35 made of non-doped GaAs, n-type AlGaAs electron supply layer 36, n-
A GaAs cap layer 7 is formed.

FIG. 4 shows a potential profile of the FET shown in FIG. 3 in the direction from the substrate to the gate electrode. FIGS. 4A and 4C show potential profiles at the time of low electron density and at the time of high electron density, respectively, on the line including the AlAs rod (34B) (Y1-Y2 in FIG. 3B). FIGS. 7B and 7D show GaAs rods (34).
3A is a potential profile on a line including A) (Z1-Z2 in FIG. 3B) at a low electron density and at a high electron density, respectively.

Under the condition of high electron density, FIG.
As shown in (D), since the electrons approach the gate electrode side, the electrons emerge from the in-plane superlattice and are distributed toward the second channel layer 35, so that a two-dimensional electron gas is formed. On the other hand, under the condition of low electron density, as shown in FIGS. 4A and 4B, the center of gravity of the electron distribution moves to the substrate side.
The electrons are confined in the in-plane superlattice 34, and a one-dimensional electron gas is formed in the GaAs rod 34A. Thus, in the second embodiment according to the present invention, by applying an appropriate negative voltage to the gate, the electrons undergo one-dimensional confining only under the gate, and behave as a two-dimensional electron gas in places where the electron density is high. . Therefore, since a high mobility and a high drift speed associated with the one-dimensional confinement are realized under the gate, it behaves as a two-dimensional gas in a parasitic region having a high electron density, so that an increase in parasitic resistance can be avoided.

Such an element is manufactured as follows. (001) GaAs inclined by 1 ° in the [1-10] direction
For example, a non-doped GaAs buffer layer 32 of 1 μm and a non-doped Al
_{A 0.3} Ga _0.7 As layer 33 is sequentially grown at 500 A. Here, since a substrate inclined by 1 ° is used, a step of 162 A period occurs on the crystal plane. By alternately growing AlAs and GaAs along this step, the in-plane superlattice layer (GaAs) _0.75 (AlAs)
_0.25 34 is formed by 50A. Subsequently, the non-doped GaAs channel layer 35 is 50 A, the n-type AlGaAs electron supply layer (doping concentration 3 × 10 ¹⁸ / cm ³ ) 36 is 200 A, and the n-type GaAs cap layer (doping concentration 5
× 10 ¹⁸ / cm ³ ) 7 is sequentially grown to 500A.

After the source electrode 8S and the drain electrode 8D are formed on the n-type GaAs cap layer 7 by vapor deposition, ohmic contact is made by alloying. Here, a source electrode and a drain electrode are arranged on both ends of a semiconductor rod forming an in-plane superlattice. Further, a gate electrode 9 is formed in a recess formed by removing the n-type GaAs layer 7 by etching. Thus, the FET of FIG. 3 is completed.

In the above embodiment, AlGaAs / GaAs
Although the present invention has been described using the s system, AlGaAs / In
GaAs / GaAs strained lattice system and AlInAs / Ga
The present invention is also applicable to an FET using another material system such as an InAs / InP system.

[0019]

As is apparent from the above detailed description,
According to the present invention, by providing the hetero buffer layer on the substrate side of the in-plane superlattice layer, one-dimensional confinement can be realized even at a low current. Furthermore, in such a structure, by providing a non-doped channel layer on the gate side of the in-plane superlattice layer, it is possible to avoid an increase in parasitic resistance due to the thinning of the channel. An optimum FET as an element can be obtained.

[Brief description of the drawings]

FIG. 1 is an element structure diagram of a first embodiment of an FET according to the present invention.

FIG. 2 is a band profile diagram in the first embodiment.

FIG. 3 is a device structural view of a second embodiment of the FET according to the present invention.

FIG. 4 is a band profile diagram in the second embodiment.

FIG. 5 is an element structure diagram of a conventional FET.

FIG. 6 is a band profile diagram in a conventional example.

[Explanation of symbols]

1 S. I. GaAs substrate 2, 32, 35, 52 i-GaAs layer 3, 5, 33 i-AlGaAs layer 4, 34, 54 (AlAs) (GaAs) in-plane superlattice layer 4A, 34A, 54A i-GaAs rod 4B, 34B , 54B i-AlAs rod 6, 36, 56 n-type AlGaAs electron supply layer 7 n-type GaAs layer 8S, 8D ohmic electrode 9 gate electrode

Claims (2)

(57) [Claims] An in-plane superlattice layer in which rods made of a first semiconductor material and rods made of a second semiconductor material having an electron affinity smaller than that of the first semiconductor material are alternately arranged on a semiconductor substrate. And an electron supply layer made of a third semiconductor material doped with an n-type impurity, sequentially stacked, and a field-effect transistor that allows electrons to travel in a longitudinal direction of a rod made of the first semiconductor material, A field effect transistor comprising: a hetero buffer layer made of a fourth semiconductor material having an electron affinity smaller than that of the first semiconductor material on a side of the in-plane superlattice layer opposite to the electron supply layer. 2. A non-doped channel layer comprising a fifth semiconductor material having an electron affinity higher than that of the third semiconductor material, between the in-plane superlattice layer and the electron supply and supply. 2. The field effect transistor according to 1.