JPH04299869A - Field effect transistor - Google Patents

Abstract

PURPOSE:To obtain an FET structure capable of maintaining one-dimensional confinement of electrons even in the case of low current and exhibiting excellent electron conveyance characteristics. CONSTITUTION:A superlattice layer 4 in a surface is constituted by alternately arranging rods 4A and rods 4B composed of materials of different electron affinity. In an FET wherein electrons are made to transit in the longitudinal direction of these rods, a hetero buffer layer 3 is formed on the side opposite to an electron supply layer 6 of the superlattice layer 4. Independently of a gate voltage, electrons locally exist in the superlattice layer 4, and form one- dimensional electron gas.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to the structure of a field effect transistor (FET) using a quantum wire as a channel.
In particular, it relates to an epitaxial layer structure that makes it possible to improve its performance.

0002

2. Description of the Related Art FIG. 5 shows an example of a quantum wire FET according to the prior art. The figure (A) is a device structure diagram, the figure (B) is a cross-sectional view of the element in the plane (X1-X2-X3-X4) including the gate electrode, and the figure (C) is an in-plane diagram of the same plane. FIG. 3 is a cross-sectional view of a superlattice layer. Such a quantum wire FET was described by Tsubaki et al. in Electronics Letters.
cs Lett. ), Volume 24, No. 20, 1267
Page, 1988. This FET is composed of a semi-insulating (S.I.) GaAs substrate 1, a non-doped GaAs layer 52 constituting a buffer layer, an in-plane superlattice layer 54, and an n-type AlGaAs layer 56 as an electron supply layer.

Here, as the GaAs substrate 1, [1-10
] Using a (001) GaAs substrate tilted by 1° in the direction,
An in-plane superlattice 54 in which non-doped GaAs rods 54A and non-doped AlAs rods 54B are alternately formed is fabricated by using a metal organic chemical vapor deposition (MOCVD) method. On the electron supply layer 56 is n-type Ga.
A cap layer 7 made of As is formed, and a source electrode 8S and a drain electrode 8D are formed on the cap layer 7 by vapor deposition to make ohmic contact with the channel. Furthermore, a gate electrode 9 is formed in the recessed portion formed by removing the cap layer 7.

0004

[Problems to be Solved by the Invention] FIG. 6 shows a potential profile in the direction from the substrate to the gate electrode of the conventional quantum wire FET shown in FIG. Figure 6(A), (
C) is a potential profile on a line including the AlAs rod 54B (Y1-Y2 in FIG. 5(B)) at low electron density and at high electron density, respectively. Same figure (B),
(D) is on the line including the GaAs rod 54A (Fig. 5(B)
These are the potential profiles at low electron density and high electron density in Z1-Z2), respectively. In the figure, EC is the bottom of the conduction band, EF is the Fermi level, and n represents the electron density distribution. Under conditions of high electron density, as shown in FIGS. 6(C) and (D), electrons approach the vicinity of the hetero interface, so the electrons are localized toward the GaAs rod 54A, forming a one-dimensional electron gas. Ru. On the other hand, under conditions of low electron density, the confinement decreases as shown in FIGS. 6A and 6B, and electrons begin to travel within the buffer layer 52 and behave as a two-dimensional gas.

In this way, the quantum wire FET according to the prior art
exhibits good electron transport characteristics at high currents due to the one-dimensionality of carriers, but at low currents it exhibits similar characteristics to conventional two-dimensional electron gas FETs (2DEGFETs). Generally, when using a FET as a high-frequency, low-noise device, it is essential that the transfer conductance (gm) at low currents be high. There was a problem that it was not reflected.

The present invention provides an epitaxial layer structure that maintains one-dimensional carrier confinement even at low currents and exhibits good electron transport properties by modifying the epitaxial layer structure of quantum wires. It is.

[0007]

[Means for Solving the Problems] A field effect transistor of the present invention comprises, on a semiconductor substrate, a rod made of a first semiconductor material and a second semiconductor material having a smaller electron affinity than the first semiconductor material. An in-plane superlattice layer in which rods are arranged alternately and an electron supply layer made of a third semiconductor material doped with an n-type impurity are sequentially laminated to supply electrons in the longitudinal direction of the rods made of the first semiconductor material. In the running field effect transistor, a heterobuffer layer made of a fourth semiconductor material having a lower electron affinity than the first semiconductor material is formed on the opposite side of the in-plane superlattice layer from the electron supply layer. It is characterized by Furthermore, in the above field effect transistor, a non-doped channel layer made of a fifth semiconductor material having a higher electron affinity than the third semiconductor material is inserted between the in-plane superlattice and the electron supply layer. shall be.

[0008]

[Operation] In the conventional quantum wire FET, under conditions where electron density is low, electrons seep into the electron buffer layer and one-dimensional confinement is no longer maintained. In the present invention, by providing a hetero-buffer layer on the side of the in-plane superlattice layer opposite to the electron supply layer, leakage of electrons into the buffer layer is suppressed. It can be seen that by doing this, one-dimensional confinement is achieved even at low currents, and as electron transport is improved, good noise characteristics are exhibited.

However, in such a structure, electrons always behave as a one-dimensional gas, regardless of the magnitude of the electron density. Therefore, electrons travel only in the GaAs thin wire not only under the gate but also between the source and the gate and between the drain and the gate, resulting in an increase in the source parasitic resistance and the drain parasitic resistance. Ideally, one-dimensional electron confinement is achieved only under the gate, and the other parasitic regions behave as a two-dimensional gas. To satisfy this requirement, a first channel layer where quantum wires are formed and a second channel layer where electrons behave as a two-dimensional gas are provided, and a negative voltage is applied to the gate to reduce the electron concentration. Only electrons need to be confined in the first channel layer. Specifically, in the structure described above, a non-doped channel layer may be provided at the interface between the electron supply layer and the in-plane superlattice layer. By doing this, as the electron concentration decreases by applying a negative voltage to the gate, the electron distribution moves away from the gate and approaches the substrate side, so that it is confined in the quantum wires forming the in-plane superlattice. On the other hand, in a parasitic region with a high electron concentration, electrons are two-dimensionally distributed in the upper non-doped channel layer, so an increase in parasitic resistance is suppressed.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the element structure of an FET according to a first embodiment of the present invention. The figure (A) is a device structure diagram, the figure (B) is a cross-sectional view of the element in the plane (X1-X2-X3-X4) including the gate electrode, and the figure (C) is an in-plane diagram of the same plane. FIG. 3 is a cross-sectional view of a superlattice layer. On a semi-insulating GaAs substrate 1, a non-doped GaAs buffer layer 2, a non-doped AlGaAs hetero buffer layer 3, an in-plane superlattice layer 4, a non-doped AlG
An aAs spacer layer 5, an n-type AlGaAs electron supply layer 6, and an n-GaAs cap layer 7 are formed.

FIG. 2 shows a potential profile in the direction from the substrate to the gate electrode of the quantum wire FET shown in FIG. Figures 2(A) and (C) show AlAs rods (4B
) are the potential profiles at low electron density and high electron density at (Y1-Y2), respectively. Figures (B) and (D) are potential profiles on the line (Z1-Z2) including the GaAs rod (4A) at low and high electron densities, respectively. In the figure, EC is the bottom of the conduction band, EF is the Fermi level, and n represents the electron density distribution. As shown in FIG. 2, regardless of the magnitude of the electron density, electrons are confined in the in-plane superlattice 4 due to the effect of the hetero buffer layer 3, and a one-dimensional electron gas is formed in the GaAa rods 4A. As described above, in the quantum wire FET according to the present invention, one-dimensional carrier confinement is maintained not only at high current but also at low current, and the electron transport characteristics are improved. Therefore, gm at low current is improved compared to conventional FETs, and especially high frequency noise characteristics are improved.

[0012] Such an element is manufactured as follows. (001) GaAs tilted by 1° in the [1-10] direction
For example, a non-doped GaAs buffer layer with a thickness of 1 μm and a non-doped Al0.3 layer is formed on the substrate by MOCVD growth.
A Ga0.7As hetero buffer layer 3 of 500 angstroms (hereinafter referred to as A) is sequentially grown. Here, 1
Since we use a substrate tilted by 1°, there is a 1°
A step of 62 A periods occurs. By growing AlAs and GaAs alternately along this step,
In-plane superlattice layer (GaAs) 0.5 (AlAs) 0.5
4 by 150A. Continue to use non-doped Al
GaAs spacer layer 5 is 30A, n-type Al0.3Ga
0.7 As electron supply layer (doping concentration 3×1018
/cm3)6 at 270A, n-type GaAs cap layer (
Doping concentration 5×1018/cm3)7 at 500A
After a source electrode 8S and a drain electrode 8D are formed by vapor deposition on the n-type GaAs cap layer 7, which is grown in sequence, ohmic contact is made by alloying. Here, a source electrode and a drain electrode are arranged on both ends of the semiconductor rod forming an in-plane superlattice. Further, a gate electrode 9 is formed in the recessed portion formed by etching away the n-type GaAs layer 7. In this way, the FET of FIG. 1 is completed.

FIG. 3 shows the element structure of an FET according to a second embodiment of the present invention. 3A is an element structure diagram, and FIG. 1B is a sectional view of the element in a plane (X1-X2-X3-X4) including the gate electrode. On the semi-insulating GaAs substrate 1, a non-doped GaAs buffer layer 32 and a non-doped AlGa
As hetero buffer layer 33, in-plane superlattice layer 34 forming a first channel, second channel layer 35 made of undoped GaAs, n-type AlGaAs electron supply layer 36, n-
A GaAs cap layer 7 is formed.

FIG. 4 shows a potential profile in the direction from the substrate to the gate electrode of the FET shown in FIG. FIGS. 4A and 4C are potential profiles at low electron density and high electron density, respectively, on the line including the AlAs rod (34B) (Y1-Y2 in FIG. 3B). (B) and (D) are GaAs rods (34A
) on the line (Z1-Z2 in FIG. 3(B)) at low electron density and high electron density, respectively.

Under the condition of high electron density, FIGS. 4(C) and (D
), as the electrons approach the gate electrode side,
Electrons exit from the in-plane superlattice and become distributed toward the second channel layer 35, forming a two-dimensional electron gas. on the other hand,
Under conditions of low electron density, as shown in FIGS. 4A and 4B, the center of gravity of the electron distribution moves toward the substrate, so electrons are confined in the in-plane superlattice 34 and the GaAs rods 34
A one-dimensional electron gas is formed in A. In this way, in the second embodiment of the present invention, by applying an appropriate negative voltage to the gate, electrons undergo one-dimensional confinement only under the gate, and behave as a two-dimensional electron gas in areas with high electron density. . Therefore, while achieving high mobility and high drift velocity associated with one-dimensional confinement under the gate, it behaves as a two-dimensional gas in the parasitic region with high electron density, making it possible to avoid an increase in parasitic resistance.

[0016] Such an element is manufactured as follows. (001) GaAs tilted by 1° in the [1-10] direction
For example, a non-doped GaAs buffer layer 32 with a thickness of 1 μm and a non-doped Al0 layer is formed on the substrate 1 by MOCVD growth.
．． A 3 Ga0.7 As layer 33 of 500 A is sequentially grown. Here, since we are using a substrate tilted by 1°,
Steps with a period of 162A occur on the crystal plane. Along this step, an in-plane superlattice layer (GaAs) of 0.75 (A
lAs) 0.2534 by 50A. Subsequently, the non-doped GaAs channel layer 35 was heated to 50A, n-type A.
lGaAs electron supply layer (doping concentration 3×1018/
cm3) 36 at 200A, n-type GaAs cap layer (
Doping concentration 5×1018/cm3)7 at 500A
grow sequentially.

A source electrode 8S and a drain electrode 8D are formed on the n-type GaAs cap layer 7 by vapor deposition, and then ohmic contact is established by alloying. here,
A source electrode and a drain electrode are respectively disposed on both ends of the semiconductor rod forming an in-plane superlattice. Furthermore,
A gate electrode 9 is formed in the recessed portion formed by etching away the n-type GaAs layer 7. Thus, the FE in Figure 3
T is completed.

In the above embodiments, AlGaAs/GaA
Although the present invention has been explained using the s system, AlGaAs/In
GaAs/GaAs strained lattice system and AlInAs/Ga
It is also applicable to FETs using other material systems such as InAs/InP systems.

[0019]

[Effect of the invention] As is clear from the above detailed explanation,
According to the present invention, by providing a heterobuffer layer on the substrate side of the in-plane superlattice layer, one-dimensional confinement is realized even at low current. Furthermore, in such a structure, by providing a non-doped channel layer on the gate side of the in-plane superlattice layer, it is possible to avoid an increase in parasitic resistance due to thinning of the channel, resulting in low high-frequency noise. An optimal FET as an element can be obtained.

[Brief explanation of drawings]

FIG. 1 is an element structure diagram of a first embodiment of an FET according to the present invention.

FIG. 2 is a band profile diagram in the first embodiment.

FIG. 3 is an element structure diagram of a second embodiment of the FET according to the present invention.

FIG. 4 is a band profile diagram in a second embodiment.

FIG. 5 is an element structure diagram of an FET according to the prior art.

FIG. 6 is a band profile diagram in a conventional example.

[Explanation of symbols]

1 S. I. GaAs substrate 2, 32, 35, 52 i-GaAs layer 3, 5, 33
i-AlGaAs layers 4, 34, 54 (AlAs) (GaAs) in-plane superlattice layers 4A, 34A, 54A i-GaAs rods 4B, 3
4B, 54B i-AlAs rod 6, 36, 56
n-type AlGaAs electron supply layer 7 n-type GaAs layer 8S, 8D ohmic electrode 9 gate electrode

Claims (2)

[Claims] 1. An in-plane superlattice layer in which rods made of a first semiconductor material and rods made of a second semiconductor material having a lower electron affinity than the first semiconductor material are alternately arranged on a semiconductor substrate. and an electron supply layer made of a third semiconductor material doped with an n-type impurity are sequentially laminated, and the field effect transistor causes electrons to travel in the longitudinal direction of the rod made of the first semiconductor material, A field effect transistor comprising a heterobuffer layer made of a fourth semiconductor material having a lower electron affinity than the first semiconductor material on a side of the in-plane superlattice layer opposite to the electron supply layer. 2. A non-doped channel layer made of a fifth semiconductor material having a higher electron affinity than the third semiconductor material is provided between the in-plane superlattice layer and the electron supply/transfer layer. 1. The field effect transistor according to 1.