JP2660965B2 - Method for manufacturing at least two multilayer chip inductors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting internal conductors and external terminals of monolithic chip inductors, transformers and other electronic thick film devices.

[0002]

2. Description of the Related Art Although monolithic multilayer chip devices have been known in the past, there is a demand for a monolithic multilayer chip device which can be easily manufactured in large quantities and has high operational reliability.

[0003]

Accordingly, it is a primary object of the present invention to provide an improved monolithic multilayer chip device and a method of manufacturing the same. Another object of the present invention is to provide an improved monolithic multilayer chip device having a plurality of coil conductor layers stacked one above the other, sandwiched between ferrite layers, and having end cap terminals at both ends. To provide. It is another object of the present invention to provide an improved monolithic multi-layer chip device that can be manufactured in large quantities as a single sheet material and subsequently cut as individual devices.

It is another object of the present invention to provide an improved monolithic multilayer chip device that is simple in structure, easy to manufacture, and reliable in operation, and a method of manufacturing the same. Yet another object of the present invention is to eliminate excess silver, reduce capacitance, reduce eddy currents, suppress delamination, increase self-resonant frequencies, and cut when cutting individual devices from a wafer. It is an object of the present invention to provide an improved monolithic multilayer chip device having a wide maximum allowable position error width and a method of manufacturing the same.

[0005]

SUMMARY OF THE INVENTION The monolithic multilayer chip device of the present invention can be an inductor, transformer, or any other electronic thick film device, but is a preferred embodiment of the present invention. A description will be given in connection with the chip inductor. However, the present invention is not limited to this embodiment, but encompasses all other embodiments within the spirit and scope of the present invention. A monolithic multilayer chip device according to the present invention for solving the above-mentioned object comprises a plurality of sub-assemblies stacked one above another. A laminated bottom subassembly located at the bottom of the inductor includes a bottom ferrite layer having a leading edge, a trailing edge, and both sides, a first end adjacent the leading edge of the bottom ferrite layer, and a leading edge of the bottom ferrite layer. A bottom coil conductor (also simply referred to as a "coil") having a second end inwardly spaced from the bottom and printed on the bottom ferrite layer. If desired, the required number of additional intermediate subassemblies can be printed on this bottom subassembly. Each such additional intermediate subassembly comprises a ferrite layer having through-holes or openings and a coil conductor printed on top of the ferrite layer. A first end of each coil conductor is aligned over a communication opening of a ferrite layer therebelow, and a second end of the coil conductor is aligned with a communication opening of a ferrite layer thereover. The ends of the coil conductors are connected to each other by a conductor (conductive filler) filled in the communication opening. A preferred conductor for this purpose is a silver filler printed over each communication opening to fill the communication opening and establish an electrical connection between the two coil conductors above and below it. The stacked top subassembly is printed on the top surface of the subassembly stack. The laminated top subassembly comprises a top ferrite layer having a through hole therethrough and a top coil conductor laminated on top of the top ferrite layer. A first end of the top coil conductor is aligned with a communication opening in the top ferrite layer and connected to a coil conductor therebelow by a conductive filler filled in the communication opening. The second end of the top coil conductor is
Adjacent to one of the edges of the top subassembly and above one edge of one of the bottom ferrite layers. This arrangement allows end caps or terminals to be placed over both ends of the entire assembly or monolithic multilayer chip inductor, respectively. One end cap is in electrical contact with the first end of the bottom coil conductor and the other end cap is in electrical contact with the second end of the top coil conductor. Further, a top cap ferrite layer is printed over the top subassembly.

A plurality of monolithic multilayer chip inductors having the above configuration can be manufactured simultaneously by the method of the present invention. According to the method of the present invention, first,
A sheet of Mylar or other material with a low coefficient of adhesion is coated on the bottom ferrite layer. Next, a plurality of first (bottom) coil conductors are printed on the bottom ferrite layer. These first coil conductors are printed on the bottom ferrite layer in such a manner that one end of the coil conductor is adjacent one side edge of the bottom ferrite layer. Both ends of these first coil conductors are brought into electrical contact with the end cap terminals when each inductor is completed. These plurality of first coil conductors are arranged on the bottom ferrite layer such that both ends of each conductor adjacent to both ends of the bottom ferrite layer are adjacent to both ends of the other first coil conductors. In a next step, a second ferrite layer having a plurality of communication openings aligned on the inner end (output end) of the corresponding first coil conductor is printed on the first coil conductor. Next, a silver conductive filler is filled into each of the communication openings of the second ferrite layer, and one second is placed on the second ferrite layer.
The second coil conductor of the group is printed. One end of each second coil conductor is aligned with a corresponding one of the communication openings in the second ferrite layer. This second ferrite layer and the plurality of second coil conductors printed thereon constitute a group of intermediate subassemblies.

[0007] If desired, an additional group of intermediate subassemblies can be printed on the intermediate subassemblies in a similar manner. Print a group of top coil conductors on top of the top ferrite layer. Each end of a group of top coil conductors is
Adjacent to one edge of the top ferrite layer. As in the case of the bottom ferrite layer, these groups of top coil conductors are:
Each conductor is disposed on the top ferrite layer in such a manner that both ends adjacent to the edge of the top ferrite layer are also adjacent to both ends of the other top coil conductor. Finally, a top cap ferrite layer is printed over the top group of top coil conductors. A separate screen with cut lines is printed on the top cap ferrite layer with the marking ink. The entire assembly is then peeled off from the mylar sheet and cut into individual elements with a cutter (razor) blade. These elements are mounted on an alumina substrate for sintering. During sintering, no two elements come into contact. Sintering is performed in a furnace at a temperature of 900 ° C. for 2 hours. At that time, in order to prevent the occurrence of blisters and cracks, sufficient care is taken so that the organic binder in each element is burned out. After the sintering step, the resulting assembly or wafer is removed from the alumina substrate.
After cutting the entire assembly into individual monolithic multilayer chip inductors (individual wafers) and firing, the exposed conductor ends on the periphery of each completed chip inductor are the outer ends of the bottom coil conductors, Only the bottom end and the outer or top end of the top coil conductor. All but the bottom and top ends of all coil conductors are completely encased in the laminated ferrite of the completed individual monolithic multilayer chip inductor. Furthermore, each coil conductor is aligned with the ferrite layer of the monolithic multilayer chip inductor in plan view.

[0008] Since the coil conductors are arranged such that the ends of each conductor adjacent to the edge of the ferrite layer are all adjacent to each other, a cutting line passes between the two conductor ends. In the conventional method, when the wafer is cut, a portion of the conductor is left in a portion adjacent to one cutting line. The remaining conductors increase the capacitance, increase the self-resonant frequency, and also cause a short circuit problem. Further, in the present invention, the size of the cutting allowable area is almost twice as large as that of the prior art, and it is almost impossible to miscut (cut an erroneous portion) the conductor material with a cutter blade.

[0009] Terminals are attached to different edges (preferably both edges) of the individual inductors obtained as described above. One terminal is electrically connected to the output end of the top coil conductor, and the other terminal is electrically connected to the input end of the bottom coil conductor.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of the present invention will be described in relation to a case where the present invention is applied to a chip inductor.
The invention is not limited to the embodiments described here. Referring to the accompanying drawings, the monolithic (integral) multilayer chip inductor 10 of the present invention is an assembly including a plurality of subassemblies 20, 30, 44, and 58 stacked vertically. Monolithic multilayer chip inductor ("multilayer chip inductor" or "chip inductor"
Or simply “inductor” or “element”) 10
The laminated bottom sub-assembly 20 of FIG.
It consists of a bottom coil conductor 24 printed on top of the ferrite layer. The bottom coil conductor 24 is
The bottom ferrite layer 22 has a front edge 14, a rear edge 16 and side edges 18. The outer end 26 of the coil conductor 24 is flush with the front edge 14 of the bottom ferrite layer 22 (aligned in the same plane) and is exposed to the outside when the assembly or chip inductor 10 is completed. . The remaining portions of the bottom coil conductor 24 other than the outer end are the side edges 18 and the rear edge 1 of the bottom ferrite layer 22.
6 (retracted).

On the bottom subassembly 20, a first intermediate subassembly 30 is printed. First intermediate subassembly 30
Consists of a first intermediate ferrite layer 32 having a through-hole or opening 34 and a first intermediate coil conductor 36 printed on the top surface of the ferrite layer 32. The through connection hole 34 is
The bottom coil conductor 24 is aligned right above the coil inner end 28. The first intermediate coil conductor 36 has a coil inner end 38 aligned above the communication hole 34 and an outer end 2 of the bottom coil conductor 24.
6 has a coil outer end 40 that is spaced inwardly from the front edge 14 of the subassembly 20.

In the present invention, each ferrite layer is preferably printed by several multiple printings until its total thickness in a normal state (dry state) becomes approximately 25 μm, but without losing the advantages of the present invention. Ferrite layers having a thickness other than 25 μm can also be used. However, the thickness of each ferrite layer is determined by setting a conductive filler (conductor) 42 for setting an electrical connection between the inner end 38 of the first intermediate coil conductor 36 and the inner end 28 of the bottom coil conductor 24 to the communication hole 34. It must be thick enough to allow for filling.

On the first intermediate subassembly 30, a second intermediate subassembly 44 is printed. The second intermediate subassembly 44 comprises a second intermediate ferrite layer 46 having a through-hole or opening 48 and a second intermediate coil conductor 50 printed on the top surface of the ferrite layer. The second intermediate coil conductor 50 has an inner coil end 54 and an outer coil end 52 aligned over the communication hole 48. The communication hole 48 is filled with the conductive filler 56 and is aligned on the outer coil end 40 of the first intermediate coil conductor 36. Thus, Fira 56
Sets an electrical connection between the outer coil end 40 of the first intermediate coil conductor 36 and the outer coil end 52 of the second intermediate coil conductor 50. The entire second intermediate coil conductor 50 is arranged inside the periphery of the second intermediate ferrite layer 46.

On top of the second intermediate subassembly 44, a laminated top subassembly 58 is printed. Top subassembly 58
Consists of a top ferrite layer 60 having a through-hole or opening 62 and a top coil conductor 64 printed on top of the ferrite layer. The top coil conductor 64 has an inner coil end 66 aligned over the communication hole 62 and an outer coil aligned with the trailing edge of the top ferrite layer 60 and also aligned over the trailing edge 16 of the bottom ferrite layer 22. It has an end 68. The conductive hole 69 is filled in the communication hole 62, and establishes an electrical connection between the inner end 66 of the top coil conductor 64 and the outer end 54 of the second intermediate coil conductor 50.

A top cap ferrite layer 70 has been printed over the top subassembly 58 and covers the top subassembly 58. However, the inner coil end 66 of the top coil conductor 64 is exposed between the edge of the top ferrite layer 60 and the edge of the top cap ferrite layer 70.

When the assembly is completed, the bottom coil conductor 24
Starting from the outer end 26, passing through the inner end 28, to the inner end 38 of the first intermediate coil conductor 36 from the first filler 42,
The second filler 56, the coil outer end 52, the coil inner end 54, and the third filler 6 pass through the outer end 40 of the first intermediate coil conductor 36.
9. A continuous electric path to the coil inner end 66 and the coil outer end 68 is set. This electrical path is provided by the bottom coil conductor 2
It should be noted that it extends from 4 to the top coil conductor 64 in the same rotational direction (clockwise in FIG. 1). The number of the intermediate coil subassemblies 30, 44 can be any number. Also, the inductor or assembly 10 may, depending on the value of the required inductance,
The intermediate coil sub-assemblies 30 and 44 may be omitted, and may be constituted by only the bottom sub-assembly 20 and the top sub-assembly 58.

Referring to FIG. 2, a pair of terminals 7
2,74 are placed over the leading edge 14 and trailing edge 16 of the assembly 10 by printing or other means. Terminals 72, 7
4 may be a metal end cap or a printed conductive material printed over the front edge 14 and the rear edge 16 of the inductor 10.
Terminal 72 is in electrical contact with outer end 68 of top coil conductor 64 and terminal 74 is connected to outer end 26 of bottom coil conductor 24.
To make electrical contact.

The monolithic multilayer chip inductor 10 thus obtained is shown in FIGS.
4 to 18 show a method of manufacturing a plurality of inductors 10 at the same time. 4 to 18, FIG.
Parts similar to those shown in FIG. 3 are indicated by the same reference numerals. Referring to FIG. 4, 50.8 mm × 5 mm using an adhesive suitable for microelectronics.
0.8mm x 0.254mm (thickness) (2in x 2in
× 0.010 inch) thick mylar sheet (not shown)
Is adhered to the upper surface of a soda-lime glass substrate (not shown). In addition to Mylar, plastic or other materials such as polyethylene having a low adhesion coefficient can be used. Polyvinyl alcohol or the like is applied to the upper surface of the mylar-coated substrate as a release material, and the polyvinyl alcohol is dried. Then, a ferrite base or bottom cap 22 shown in FIG. 4 is printed on the mylar.

After printing the bottom cap 22 made of ferrite, a plurality of bottom coil conductors (hereinafter simply referred to as "coils") 24 (FIG. 5) are printed on the bottom cap or ferrite layer 22. At that time, the outer end 26 of each coil 24 is made wider than other portions of the coil,
The plurality of coils 24 are printed so as to be located at the center of the bottom cap 22. Figures 16, 17, 18
15 is an enlarged view of a plurality of top coil conductors 64 of the top ferrite layer 60 shown in FIG. Bottom coil conductor 24
Are also arranged in the same pattern as the arrangement of the top coil conductors 64 described in detail below. FIG. 17 shows an arrangement pattern of coil conductors according to the prior art. The dotted lines in FIGS. 17 and 18 indicate where the coil conductor cuts the printed ferrite layer. As can be seen from the figure, when the ferrite layer is cut,
In the prior art, a small portion of the coil conductor 24 is left at the leading edge 16 of the adjacent element 10. The remaining conductive material increases the capacitance, increases the self-resonant frequency, and also causes a short circuit problem. The present invention solves these problems by inverting the coil conductors of the alternating elements 10 in the same column by 180 ° in the arrangement pattern of the coil conductors. Such conductor arrangement patterns are shown in FIGS.
Is shown in relation to The part of the element 10 connected to the external terminal 74 or 72 is connected to the part located directly above or below the element. In other words, each pair of elements 10 and 10 in the same column is in an electrically short-circuited state until they are disconnected and separated. Another advantage of this arrangement pattern is that the size of the cutting allowance area is almost twice that of the prior art, and there is virtually no possibility of miscutting the conductor material with a cutter blade. It is. A pair of silver crosses 75 are printed on the ferrite layer 22 (see FIG. 5).

After printing the plurality of coils 24, a first intermediate ferrite layer 32 (FIG. 6) of the first intermediate subassembly 30 is printed on the coils 24. The first intermediate ferrite layer 32 has a plurality of communication holes 34 aligned on the inner ends 28 of the corresponding coils 24, respectively. The crosses 75, 75 of the ferrite layer 22 are aligned with a pair of open cross windows 76 formed in the first intermediate ferrite layer 32 so that the first intermediate ferrite layer 32 can be properly aligned with the coil 24. It has been made like that.

Next, as shown in FIG. 7, a plurality of first conductive fillers 42 are aligned with the corresponding communication holes 34 (see FIG. 6), and the first conductive fillers 42 are completely filled therewith.
2 and a cross 78 is printed on a silver cross 75 (see FIG. 5) aligned with the cross window 76 (see FIG. 6).

Next, as shown in FIG. 8, a plurality of first intermediate coil conductors 36 are fitted with their inner ends 38 over corresponding openings (communication holes) 34 to form first fillers 42.
(See FIG. 7) Printed on first intermediate ferrite layer 32 with proper alignment to make electrical contact. At the same time, four crosses 79 are printed at the four corners of the ferrite layer 32.

If necessary, the first intermediate subassembly 30 of FIG.
As many second intermediate subassemblies 44 (FIG. 9
To 11) can be laminated. That is, as shown in FIG. 9, a second intermediate ferrite layer 46 having a plurality of communication holes 48 and a cross window 82 aligned on the cross 79 is printed on the first intermediate subassembly 30. Then, FIG.
As shown at 0, a second conductive filler 56 is printed on each corresponding communication opening 48 (see FIG. 9),
A cross 84 is printed on the cross window 82 (see FIG. 9). Next, as shown in FIG. 11, the second intermediate coil conductor 50 and the four crosses 86 are printed on the second intermediate ferrite layer 46 in the same manner as in the case of the first intermediate subassembly 30.

The final or top subassembly 58 is shown in FIGS. Top subassembly 58 includes a top ferrite layer 60 having a communication hole 62. The top ferrite layer 60 also has two cross windows 83 that match two of the four crosses 86 of the second intermediate ferrite layer 46. As shown in FIG. 13, a plurality of conductive fillers 69 are printed on the ferrite layer 60 so as to be aligned with and completely fill the corresponding communication holes 62 (see FIG. 12), and the cross window 82 (FIG. A cross 85 is printed on the ferrite layer 60 so as to match (see 12).

Next, as shown in FIG. 14, a plurality of top coil conductors 64 are aligned with their inner ends 66 above the corresponding openings (communication holes) 62 (see FIG. 12), and the top ferrite layer 60 is formed. Print on top, four crosses 88
Are printed on the four corners of the top ferrite layer 60. The outer end 68 of each top coil conductor 64 is wider than the other parts,
Adjacent to the trailing edge of each inductor 10 to be formed.

The top coil conductors 64 are arranged in a pattern similar to the arrangement of the bottom coil conductors 24 described above. FIG.
6, 17, and 18 are enlarged views of the plurality of top coil conductors 64 of the top ferrite layer 60 shown in FIG. FIG.
7 shows the arrangement pattern of the coil conductor of the prior art. The dotted lines in FIGS. 17 and 18 indicate where the coil conductor cuts the printed ferrite layer. As can be seen from the figure, when the ferrite layer is cut, the coil conductor 6
Four small portions 100 are left at the trailing edge 16 of the adjacent element 10. The remaining conductive material increases the capacitance, increases the self-resonant frequency, and also causes a short circuit problem. The present invention solves these problems by reversing the orientation of the coil conductors 64 of the alternating elements 10 in the same column by 180 ° in the arrangement pattern of the coil conductors 64. Such conductor arrangement patterns are shown in FIGS. 16 and 18 in connection with the coil conductor 64. The part of the element 10 connected to the external terminal 74 or 72 is connected to the part located directly above or below the element. In other words, each pair of elements 10 and 10 in the same column is in an electrically short-circuited state until they are disconnected and separated. Another advantage of this arrangement pattern is that the size of the cutting allowance area is almost twice that of the prior art, and there is virtually no possibility of miscutting the conductor material with a cutter blade. It is. The ferrite layer 60 has a pair of silver crosses 88.
Print The matching of each layer in FIGS.
6, 82, 83 with matching crosses 75, 78, 7
9, 84, 85, 86, 88.

The final ferrite top cap 70 is
This is shown in FIG. The top cap 70 is a non-porous sheet without an opening. On top cap 70, a separate screen having only a plurality of cutting lines 92 is printed with marking ink.

Alternatively, as shown in FIG. 14, a plurality of cut lines 90 are printed around the group of top coil conductors 64, and a ferrite top cap 70 having a plurality of cut line windows instead of cut lines 92. Can be matched to the top ferrite layer 60. By aligning the windows with their respective cutting lines 90, the top cap 70 can be properly aligned with the rest of the assembly, and when the assembly is completed, each cutting line 90 is exposed.

Next, in a preferred method, after the above-described assembly is dried, the assembly is peeled from the mylar-coated substrate and cut into individual elements with a cutter blade. At that time, the cutter blade is aligned with the cutting line 92 and cut along the thick portion, that is, the outer end 68 of each coil conductor 64 and the thick outer end 26 of each coil conductor 24. Outer end 68 and outer end 26 are the only portions of all coil conductors that are exposed by cutting the assembly with a diamond blade.
Both the bottom and top coil conductors 24, 64 and all other parts of the intermediate coil conductors 36, 50 are completely covered by the laminated ferrite layers. If properly matched before the cutting step, each coil conductor is aligned with the ferrite layer of the inductor 10 in a plan view.

The cut elements 10 are placed on an alumina substrate (not shown) for sintering. Sintering is
This is performed in a box furnace at a temperature of 900 ° C. for 2 hours. In doing so, great care is taken to burn out the organic binder in the assembly to prevent blisters and cracks from occurring.

Alternatively, the entire assembly may be fired before cutting the assembly into individual components. After the firing step, the obtained wafer is mounted on a wafer holder, and the wafer is cut into dice by a dicing saw with a precision diamond blade commonly used in the semiconductor IC industry to obtain individual chip inductors.

After inspecting each of the individual inductors 10 thus obtained, terminals or end conductors 72, 74 are attached to the inductor 10. Preferably, these terminals have a multilayer structure including a silver terminal portion, a nickel-plated end cap, and tin-lead plating coated on the end cap.

As noted above, the present invention provides a simple, efficient, and reliable manufacturing method for manufacturing a monolithic multilayer chip inductor 10.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments illustrated here, and various embodiments may be made without departing from the spirit and scope of the present invention. It is to be understood that various changes and modifications can be made.
The present invention can be applied to any other electronic thick film element that needs to connect the internal conductor and the external terminal.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view of a monolithic multilayer chip inductor of the present invention.

FIG. 2 is a perspective view of the assembled monolithic multilayer chip inductor of the present invention, with its terminal portion shown in an exploded view.

FIG. 3 is a side view taken along line 3-3 in FIG. 2;

FIG. 4 is a schematic diagram illustrating a first step of the method of the present invention for simultaneously manufacturing a plurality of inductors.

FIG. 5 is a schematic diagram showing the next step of the above method of the present invention.

FIG. 6 is a schematic diagram showing the next step of the above method of the present invention.

FIG. 7 is a schematic diagram showing the next step of the above method of the present invention.

FIG. 8 is a schematic diagram showing a further next step of the above method of the present invention.

FIG. 9 is a schematic diagram showing the next step of the above method of the present invention.

FIG. 10 is a schematic diagram showing the next step of the above method of the present invention.

FIG. 11 is a schematic diagram showing the next step of the method of the present invention.

FIG. 12 is a schematic diagram showing the next step of the method of the present invention.

FIG. 13 is a schematic diagram showing a further next step of the above method of the present invention.

FIG. 14 is a schematic diagram showing a further next step of the above method of the present invention.

FIG. 15 is a schematic diagram showing a further next step of the above method of the present invention.

FIG. 16 is an enlarged view of FIG. 14;

FIG. 17 is an enlarged view taken along line 18-18 of FIG. 16 showing the arrangement of conductive layers arranged according to the prior art.

FIG. 18 is an enlarged view taken along line 18-18 of FIG. 16 showing the arrangement of the conductive layers in a preferred embodiment of the present invention.

[Explanation of symbols]

10: Electronic thick film element (monolithic multilayer chip inductor) 14: Front edge 16: Rear edge 18: Side edge 20: Laminated bottom subassembly 22: Bottom ferrite layer 24: Bottom coil conductor 26: Outer end 28: Inner End 30: first intermediate subassembly 32: first intermediate ferrite layer 34: communication hole (communication opening) 36: first intermediate coil conductor 38: inner end 40: outer end 42: first conductive filler (conductor) 44: Second intermediate subassembly 46: Second intermediate ferrite layer 48: Communication hole (communication opening) 50: Second intermediate coil conductor 52: Outer end 54: Inner end 56: Second conductive filler (conductor) 58: Laminated top sub Assembly 60: Top ferrite layer 62: Communication hole (communication opening) 64: Top coil conductor 66: Inner end 68: Outer end 69: Conductive filler (conductor) 70: Top cap ferrite layer 72, 74: End Cap (terminal)

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Thomas L. inventor. Bake United States Nebraska 68602, Columbus, Tens Avenue 766 (72) Inventor Scott Di. Zwick United States of America 68602, Nebraska, Eighteen Street, Columbus 2614 (56) References JP-A-62-118505 (JP, A)

Claims (2)

(57) [Claims] 1. A method for manufacturing at least two multilayer chip inductors (10), comprising printing a bottom ferrite layer (22) on a substrate and positioning the bottom ferrite layer in juxtaposition with one another. The first bottom coil conductor (24) and the second bottom coil conductor (2
4) printing a bottom coil conductor layer consisting of: 4) printing a first intermediate ferrite layer (32) over the first bottom coil conductor (24) and the second bottom coil conductor (24); A first intermediate coil conductor (3
6) and a second intermediate coil conductor (36). The first intermediate coil conductor (36) and the second intermediate coil conductor (36) are respectively formed by the first bottom coil conductor (24) and the second intermediate coil conductor (36). 2 Print so as to be located on the bottom coil conductor (24), and cover the first intermediate coil conductor (36) and the second intermediate coil conductor (36) with the second intermediate ferrite layer (46 or 6).
0) is printed, and a first top coil conductor (64) and a second top coil conductor (64) are printed so as to cover the first intermediate coil conductor (36) and the second intermediate coil conductor (36), respectively. The first top coil conductor and the second top coil conductor
Each has an outer end (68), and the outer end of the first top coil conductor and the outer end of the second top coil conductor are the first top coil conductor (64) and the second top coil conductor. And a top ferrite layer covering the first top coil conductor and the second top coil conductor, the top ferrite layer covering the first top coil conductor and the second top coil conductor. Forming a spiral first inductance coil by connecting the first bottom coil conductor of the bottom coil conductor layer, the first intermediate coil conductor of the intermediate coil conductor layer, and the first top coil conductor. Connecting a second bottom coil conductor of the bottom coil conductor layer, a second intermediate coil conductor of the intermediate coil conductor layer, and the second top coil conductor to form a helical second inductance coil; Coil conductor Connecting the second bottom coil conductor of the layer, the second intermediate coil conductor of the intermediate coil conductor layer, and the second top coil conductor to form a helical second inductance coil; Along the printed bottom ferrite layer (22), the first intermediate ferrite layer (3).
2), a second intermediate ferrite layer (46 or 60) and a top ferrite layer (70), and an outer end (68) and a second top coil conductor (64) of the uncoupled first top coil conductor (64). The first and second inductance coils are separated by cutting an outer end (68) of the first and second coils, respectively, and each of the first and second inductance coils has a side edge cut by the cutting operation. Form a solid, thereby forming the outer end (6) of the first top coil conductor (64).
8) and exposing outer ends (68) of the second top coil conductors (64) at the one side edge of the first laminated assembly and the one side edge of the second laminated assembly, respectively; Three-dimensionally, the first top coil conductor (6
A first terminal (73) is mounted in electrical contact with the exposed outer end (68) of 4), and the second top coil conductor (6) is attached to the second laminated assembly.
4) A method of manufacturing a multilayer chip inductor, comprising attaching a second terminal (72) so as to make electrical contact with the exposed outer end (68). 2. A method for producing at least two multilayer chip inductors (10), comprising: coil conductors (24, 36, 5) connected in series with one another.
0,64) to form a pair of inductance coils consisting of a plurality of stacked conductor layers (8,11,14), each pair of inductance coils comprising:
A coil end (68), wherein the coil end and the coil end of the pair of inductance coils are connected to each other across a cutting line (90) extending between the pair of inductance coils. Wherein both of the pair of inductance coils are completely wrapped with ferrite material (22, 32, 60, 70), and the ferrite material is interposed between the stacked conductor layers of each of the inductance coils; Along the cutting line (90), the ferrite material and the connected coil end (68) are cut to include each one of the pair of inductance coils, each cut by the cutting operation. Forming separate first and second stack assemblies each having one side edge, wherein the cut one side edge of each of the first and second stack assemblies is the plurality of the plurality of stack assemblies; Weight Formed in the ferrite material at least covers several layers of conductor layers, wherein each coil end (68), a method for manufacturing a multilayer chip inductor which comprises exposing the cut portions by the cutting operation.