JP2648099B2 - Nonvolatile semiconductor memory device and data erasing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a data erasing method thereof, and more particularly, to a nonvolatile semiconductor memory device having an electrically rewritable memory cell having a charge storage layer and a control gate, and its data. It relates to the erasing method.

[0002]

2. Description of the Related Art A conventional technique relating to a nonvolatile semiconductor memory device is disclosed, for example, in Japanese Patent Laid-Open No. 2223097/1990.

Referring to FIG. 5 showing a configuration example of this conventional nonvolatile semiconductor memory device, this nonvolatile semiconductor memory device has a word line 6 output from an X decoder 71.
2 is connected to the control gate electrodes of the memory cells 58 and 60, and the word line 63 is connected to the control gate electrodes of the memory cells 59 and 61. The drain electrodes of memory cells 58 and 59 are connected to digit line 64, the drain electrodes of memory cells 60 and 61 are connected to digit line 65, and digit lines 64 and 65 are connected to Y decoder 72 and transistor 66, respectively. , 67 via a data read circuit 74 and a write voltage application circuit 7
3 is connected. Each of the source electrodes of the memory cells 58, 59, 60 and 61 is connected to a source voltage application circuit 70.
Connected to

An X decoder 71 and a Y decoder 72 select a memory cell transistor to be operated according to an address signal 76, and a data read circuit 74 determines the data content of the selected memory cell and outputs the data to a data bus 75.

[0005] The write voltage application circuit 73 is a circuit for supplying a high voltage to be applied to the drain electrode when writing data to the selected memory cell, and is opened except during data writing.

A source voltage applying circuit 70 is a circuit for applying a potential of a source electrode in each operation mode of the memory cell, and supplies a ground potential at the time of reading and writing data, and supplies a high voltage at the time of erasing data. . In this example, the memory cell transistors 58, 59, 60 and 61
It is assumed that selection circuit transistors 66 and 67 are N-type MOS transistors.

Next, the operation of the nonvolatile semiconductor memory device will be described.

In the case of reading data, for example, when reading data from the memory cell 58, the X decoder 71 sets the word line 62 to the power supply potential and the word line 63 to the ground potential. Further, the transistor 66 is turned on and the transistor 67 is turned off by setting the output 68 of the Y decoder 72 to the power supply potential and the output 69 to the ground potential, so that the digit line 64 is connected to the data read circuit 74 and the digit line 65 Is released. At this time, the write voltage application circuit 73 is opened, and the source voltage application circuit 70 supplies the ground potential to each of the source electrodes of the memory cells 58, 59, 60 and 61. Here, the 0 level (hereinafter abbreviated as “0”) and 1 level (hereinafter abbreviated as “1”) discrimination voltages of the data read circuit 74 are 5 V in terms of the threshold value Vt of the memory cell to be read. If the threshold value Vt of the memory cell 58 is 1 V, “1” is output from the data read circuit 74 to the data bus 75 if the threshold value Vt is 7 V.

As described above, the case where the threshold value Vt of the memory cell is lower than the discrimination voltage of the data read circuit and "1" is output from the data read circuit 74 is called an erased state, and conversely, the threshold of the memory cell. A state where the value Vt is high and “0” is output from the data read circuit 74 is called a write state. Moving the threshold value Vt of the memory cell from the erased state to the written state is called data writing, and moving the memory cell from the written state to the erased state is called data erasing.

Next, an operation for writing data to a memory cell will be described.

When writing data to the memory cell 58,
Each memory cell (58 to 6) is supplied by the source voltage application circuit 70.
The ground potential is applied to the source electrode of 1). The data read circuit 74 is opened, and the output 6 from the Y decoder 72 is output.
By setting 8 to the power supply potential and the output 69 to the ground potential, the write voltage application circuit 73 is connected to the digit line 64, and the high voltage (12V) is applied to the drain electrode of the memory cell 58.
Is applied. Digit line 65 is opened because transistor 67 is off. Then, the word line 62 selected by the output from the X decoder 71 has a high voltage (12
V) is output, and the unselected word lines 63 are set to the ground potential.

Referring to FIG. 6 schematically showing a potential distribution in a sectional view of the memory cell 58 in this state, the semiconductor substrate 82 and the source electrode 77 are set to the ground potential, and the control gate 78 is connected to the threshold voltage of the transistor. Since a positive voltage higher than Vt is applied, a channel 83 is formed in the channel region of the memory cell transistor, and the source electrode 77 and the drain electrode 81 conduct. Here, since the drain potential is high, the movement of carriers in the depletion layer 86 near the drain electrode 81 is accelerated, and carriers (hereinafter, referred to as hot carriers) 84 and 85 having high energy due to impact ionization are generated. Occur. In the hot carriers, electrons 84 are injected and accumulated in the floating gate 79 by an electric field between the floating gate 79 controlled by the potential of the control gate 78 and the depletion layer 86 near the drain electrode 81.

However, the injection of the electrons 85 ends when the potential difference between the floating gate 79 and the drain electrode depletion layer 86 becomes “0” due to the accumulation of the electrons 85. With the above operation, the threshold value Vt of the memory cell is increased (to about 7 V), and data is written.

Next, an operation for erasing data in a memory cell will be described.

When erasing data in the memory cell 58,
If transistors 66 and 67 are turned off by outputs 68 and 69 of Y decoder 72, digit line 6
Each of 4 and 65 is released from the data read circuit 74 and the write voltage application circuit 73, and applies a high voltage (12V) to each of the source electrodes of each of the memory cells 58, 59, 60 and 61. The word lines 62 and 63 output from the X decoder 71 are set to the ground potential.

Referring to FIG. 7, which schematically shows a potential distribution in a cross-sectional view of the memory cell in this state, each electrode of the memory cell transistor opens the drain electrode 91, and connects the semiconductor substrate 92 and the control gate 88 with each other. Since each is set to the ground potential and the source electrode 87 is set to the high potential (12 V), the PN between the semiconductor substrate 92 and the source electrode 87 is increased.
Avalanche breakdown occurs in the junction diode, and hot carriers 94 in the depletion layer 93 near the source.
And 95 occur.

In the hot carriers generated at this time, holes 95 are formed in the floating gate 89 controlled by the potential of the control gate 88 and the depletion layer 9 near the source electrode.
The electric field is injected into the floating gate 89 by the electric field between them. Floating gate 89 and depletion layer 93 near the source
Since the electric field between the holes 95 is relaxed by the injection of the holes 95, the injection of the holes 95 is terminated at the time when the electric field becomes “0”, that is, the potential difference between the floating gate 89 and the depletion layer 93 near the source. It is the time when it becomes "0".

With the above operation, the threshold value Vt of the memory cell is moved to a low state (about 0.5 V) to erase data.

[0019]

However, during the "erasing of data" in the operation of the above-described nonvolatile semiconductor memory device, there are the following problems.

This problem will be described with reference to FIG.
When "erasing data", that is, when moving the threshold value Vt of the memory cell transistor in the negative direction, the distribution 28 of the threshold value Vt of the memory cell after erasing is based on the charge (the amount of holes) accumulated in the floating gate. ), The amount of accumulation is determined by the electric field between the floating gate controlled by the control gate potential and the depletion layer near the source.

Therefore, when there is a difference between the floating gate and the depletion interlayer electric field near the source of each of the plurality of cell transistors arranged in the memory cell region (for example, when there is a difference in the gate oxide film thickness), the hole The threshold value Vt at the time of erasing the memory cell transistor according to the accumulated amount
Causes a variation 23. Specifically, when the potential of the control gate of the memory cell transistor at the time of erasing is the ground potential, the distribution of the threshold Vt at the time of erasing is 2
8 varies from (-1.0V) to (-1.5V),
A depletion type memory cell (a cell whose threshold value Vt is equal to or lower than the ground potential, that is, an excessively erased cell 27) is generated.

Since the over-erased cell 27 is always on at the time of reading memory data, regardless of whether the address is selected or not, it does not function as a normal memory cell and causes a malfunction of the circuit.

For example, when the memory cell 59 shown in FIG. 5 is an over-erased cell, and the word line 63 is not selected (ground potential), if the transistor 66 is turned on by the Y decoder 72, the digit line 64 is connected. In this case, a current flows, data "1" is always output to the data bus 75, and there is a problem that the device does not operate as a normal memory device.

That is, in the conventional method of erasing a non-volatile memory device, if the variation in the movement amount of the threshold Vt becomes large, an excessively erased cell is generated, and the function as a normal memory cell is impaired. There was a problem that it would.

[0025]

According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: a drain and a source comprising a diffusion layer having a conductivity type opposite to that of the semiconductor substrate on a semiconductor substrate of one conductivity type; A memory cell transistor comprising a charge storage layer formed through an insulating film of the above, and a control gate formed through the charge storage layer and a second insulating film, and applying a voltage to a source or a drain of the memory cell transistor. A non-volatile semiconductor memory device that performs erasure by applying an erase voltage to be applied to the semiconductor substrate and a PN junction of a source or a drain of the memory cell transistor to generate avalanche breakdown. When applying a control voltage higher than the potential of the substrate, the charge storage layer and the source
Potential to relax the electric field near the depletion layer by the depletion layer
Is applied to the control gate .

Further, in the data erasing method of the nonvolatile semiconductor memory device according to the present invention, there is provided a method for erasing a drain and a source comprising a diffusion layer of a conductivity type opposite to that of the semiconductor substrate on a semiconductor substrate of one conductivity type; During operation of a memory cell transistor including a charge storage layer formed through the insulating film and a control gate formed through the charge storage layer and the second insulating film, a source or a drain of the memory cell transistor In a data erasing method for a nonvolatile semiconductor memory device for erasing by applying an erasing voltage to be applied to the semiconductor substrate and a PN junction of a source or a drain of the memory cell transistor to cause avalanche breakdown, When applying a control voltage higher than the potential of the semiconductor substrate to the control gate ,
The depletion due to the depletion layer between the charge storage layer and the source
A method for applying a potential for relaxing an electric field near a layer to the control gate .

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A nonvolatile semiconductor memory device according to a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. Referring to FIG. 1, the nonvolatile semiconductor memory device comprises memory cells 1, 2, 3, and 4, Lines 5 and 6 and digit lines 7 and 8
, An X decoder 12, a selection circuit including a Y decoder 15, and transistors 9, 10, a write voltage application circuit 16, a data read circuit 17, a data bus 11, and a source voltage application circuit 14. It is.

Further, in this nonvolatile semiconductor memory device, a positive arbitrary potential higher than the ground potential is applied to the control electrode of each memory cell transistor (1 to 4) when erasing memory cell data, and the X decoder is used in other operations. There is a positive potential applying device 13 for transmitting the output of 12 to the word lines 5 and 6 as it is, and the word lines 5 and 6 are connected to the X decoder 12 via the positive potential applying device 13 respectively.

Next, the operation of the nonvolatile semiconductor memory device according to the first embodiment of the present invention will be described.

First, the case of erasing memory cell data will be described.

When erasing memory cell 1, digit lines 7 and 8 are released from data read circuit 17 and write voltage application circuit 16 by Y decoder 15 and transistors 9 and 10, respectively.
The word line 5 is set to a potential (3 V) higher than the ground potential by the positive potential application circuit 13. The source voltage application circuit 14 supplies a high potential (12 V) to the source electrode of the memory cell transistor.

In this state, like the conventional nonvolatile semiconductor memory device, the nonvolatile semiconductor memory device of the present invention causes avalanche breakdown between the source electrode and the substrate, and the floating gate controlled by the control gate potential. Holes are injected into the floating gate by the depletion interlayer electric field near the gate and the source to perform erasure.

Here, as described in the conventional example, the amount of holes accumulated in the floating gate, that is, the threshold value Vt of the memory cell after erasing is controlled between the floating gate and the depletion layer near the source controlled by the control gate potential. Since it is determined by the electric field, the potential of the control gate is increased, and the electric field of the depletion interlayer near the floating gate and the source is relaxed. I can do it.

FIG. 3 is a characteristic diagram showing the dependence of the threshold value Vt of one memory cell on the gate voltage at the time of erasing. The horizontal axis of the figure shows the erasing time, and the vertical axis shows the threshold value Vt of the memory cell. Each of the solid lines 100, 101, and 102 shows the characteristics when the gate voltage at the time of erasing is 0 V (ground potential), 1 V, and 2 V.

The measured structure of the memory cell is that of an N-type MOS transistor having a gate length of 0.8 μm, a gate width of 1.68 μm, and an oxide film thickness between floating gates of 22 nm. In this memory cell structure, it can be seen that when the control gate potential at the time of erasing is set higher by 1 V, the convergence value of the threshold Vt also increases by 1 V (see FIG. 3). In a conventional nonvolatile semiconductor memory device in which a large number of memory cells having this structure are arranged, as shown in FIG.
When the potential of the control gate at the time of erasing is set to the ground potential, the distribution 28 of the threshold Vt after erasing is (-1.0
V) to 1.5 V, and the over-erased cell 27 is generated, whereas the nonvolatile semiconductor memory device of the present invention sets the potential of the control gate at the time of erasing to 2 V to perform erasing. In this case, the amount of movement of the threshold Vt due to erasure decreases from the value 22 to the value 21, the distribution 29 of the threshold Vt after erasure rises by 2 V relatively, and the variation 24 from 1.0 V to 3 .5 V and the over-erased cells disappear.

If the voltage 26 for discriminating "1" and "0" data from the read circuit is 5 V, data can be read without any problem.

Next, a nonvolatile semiconductor memory device according to a second embodiment of the present invention will be described. Referring to FIG. 4 showing a circuit configuration of the positive potential applying circuit 13 and the X decoder 12 of the nonvolatile semiconductor memory device of the second embodiment of the present invention, the X decoder 12 of the nonvolatile semiconductor memory device of this embodiment Inverters 33 and 34 receiving address signals 31 and 32 and NAND gates 35, 36, 37 and 38, respectively.

The positive potential application circuit 13 of the nonvolatile semiconductor memory device of this embodiment receives the output of the X decoder 12 and transfers the CMOS transfer signals 53, 54, 55 and 5
6 to be connected to word lines 49, 50, 51 and 52. The word lines 49, 50, 51 and 52 have CMOS transfers 41 and 4 respectively.
The output of the voltage follower circuit 48 is connected via 2, 43 and 44, and a voltage set by the reference voltage source 45 and the resistance ratio of the resistors 46 and 47 is applied to the non-inverting input terminal of the voltage follower circuit 48. Configuration. On / off of each of the transfer gates 41, 42, 43, 44, 53, 54, 55 and 56 is controlled by the control signal 39 and the inverter 40.

Next, the operation of the X decoder 12 and the positive potential applying circuit 13 in the erase mode will be described.

In the erase mode, the control signal 39 is set to the power supply potential. Thereby, the CMOS transfer 53,
Each of 54, 55 and 56 is turned off, and each of the CMOS transfer 41, 42, 43 and 44 is turned on. The reference voltage 45 and the voltage set by the resistors 46 and 47 are input to the non-inverting input terminal of the voltage follower circuit 48, and the same potential as the input voltage is supplied to the word lines 49, 50, 51 and 52, respectively. Is done.

That is, by arbitrarily selecting the reference voltage 45 and the resistors 46 and 47 and arbitrarily setting the potential of the non-inverting input terminal of the voltage follower circuit 48, the potentials of the word lines 49, 50, 52 and 53 are erased. Can be set to an arbitrary positive potential, and as a result, the control gate potential of the memory cell rises, so that the movement amount of the threshold value Vt in erasing can be limited.

In operation modes other than erasing,
When the control signal 39 is set to the ground potential, each of the CMOS transfers 41, 42, 43 and 44 is turned off, and the voltage follower circuit 48 connects the word lines 49, 50 and 5 to each other.
1 and 52, and CMOS
Since the transfer lines 53, 54, 55 and 56 are turned on, the word lines 49, 50, 51 and 52 are connected to the X decoder and normal address selection is performed.

In the configuration of the method of setting the input voltage of the non-inverting input terminal of the voltage follower circuit 48 of this embodiment, if the components of the resistors 46 and 47 are formed in the same manufacturing process, the resistance value changes due to manufacturing variations. However, since the relative ratio characteristics do not change, a stable input voltage can be obtained.

The method of setting the input voltage of the non-inverting input terminal of the voltage follower circuit 48 includes a circuit using a threshold voltage of a transistor and a step of forming a control gate and a floating gate in which memory cells are stacked. A circuit using the capacitance ratio of the capacitors formed in the same process can also be realized.

[0046]

As described above, in the nonvolatile semiconductor memory device and the erasing method of the present invention, the threshold Vt after erasing of the memory cell transistor is controlled by the positive potential applying device connected to the control gate. Accordingly, the occurrence of over-erased cells can be prevented, and it is possible to prevent the memory cells at the non-selected addresses from being turned on when reading the stored data of the nonvolatile memory, thereby preventing normal data reading from being disabled. .

The voltage applied to the control gate can be arbitrarily determined, including 5 V as a power supply voltage and 12 V as a write voltage, depending on the structure of the device constituting the nonvolatile memory and the target threshold Vt at the time of erasing. .

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a nonvolatile semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating a distribution of a threshold value Vt of a memory cell in the erasing method of the present invention and a conventional nonvolatile semiconductor memory device.

FIG. 3 is a diagram showing a gate voltage dependence upon erasure of a threshold value Vt when erasing a memory cell;

FIG. 4 is a detailed diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention;

FIG. 5 is a configuration diagram of a conventional nonvolatile semiconductor memory device.

FIG. 6 is a cross-sectional view schematically showing a potential distribution at the time of data writing of a memory cell transistor.

FIG. 7 is a cross-sectional view schematically showing a potential distribution at the time of data erasure of a memory cell transistor.

[Explanation of symbols]

1, 2, 3, 4, 58, 59, 60, 61 memory cell transistors 5, 6, 49, 50, 51, 52, 62, 63 word lines 7, 8, 64, 65 digit lines 9, 10, 66, 67 Selection transistor 11, 75 Data bus 12, 71 X decoder 13 Positive potential application circuit 14, 70 Source voltage application circuit 15, 72 Y decoder 16, 73 Write voltage application circuit 17 Data read circuit 18, 19 For Y decoder output selection Signal 20, 31, 32, 76 Address signal 21 Movement amount of Vt of memory cell by conventional erase method 22 Movement amount of Vt of memory cell by erase method of the present invention 23, 24, 25 Variation amount 26 “0”, “1” discrimination point of data read circuit 27 Over-erased cell 28, 29 Memo at the time of erasing in conventional and present invention Vt distribution of recell 30 Vt distribution of memory cell at the time of data writing 33, 34, 40 Inverter 35, 36, 37, 38 NAND gate for X decoder 39 Control signals 41, 42, 43, 44, 53, 54, 55 , 55, 5
6 CMOS transfer 45 Reference voltage 46, 47 Resistance element 48 Voltage follower circuit 68, 69 Y decoder output selection signal 74 Data read circuit 77, 87 Source electrode 78, 88 Control gate 79, 89 Floating gate 80 Insulating oxide film 81, 91 Drain Electrodes 82, 92 Semiconductor substrate 83 Channel 84, 85, 94, 95 Hot carrier 86 Depletion layer near drain 100, 101, 102 Gate voltage at erasing is 0 V,
Change in threshold voltage Vt of memory cell at 2V and 3V

Claims (2)

(57) [Claims] And a charge storage layer formed on a semiconductor substrate of one conductivity type with a diffusion layer of a conductivity type opposite to that of the semiconductor substrate via a semiconductor substrate and a first insulating film. A memory cell transistor comprising a charge storage layer and a control gate formed via a second insulating film, wherein an erase voltage applied to a source or a drain of the memory cell transistor is applied to the semiconductor substrate and the source of the memory cell transistor. Alternatively, in a nonvolatile semiconductor memory device performing erasure by applying an avalanche breakdown by applying to a PN junction portion of a drain, when applying a control voltage higher than the potential of the semiconductor substrate to the control gate during the erasing , Charge storage layer and the source
Potential to relax the electric field near the depletion layer by the depletion layer
A non-volatile semiconductor memory device having a positive potential application circuit for applying a voltage to the control gate . And a charge storage layer formed on a semiconductor substrate of one conductivity type with a diffusion layer of a conductivity type opposite to that of the semiconductor substrate via a semiconductor substrate and a first insulating film. When operating a memory cell transistor including a charge storage layer and a control gate formed via a second insulating film, an erase voltage applied to the source or drain of the memory cell transistor is applied to the semiconductor substrate and the memory cell transistor. In a data erasing method for a nonvolatile semiconductor memory device for erasing data by applying an avalanche breakdown to a PN junction of a source or a drain, a control voltage higher than a potential of the semiconductor substrate is applied to the control gate during the erasing. At the time of
Near the depletion layer due to the depletion layer between the load accumulation layer and the source
Applying a potential to alleviate the electric field to the control gate .