JPH05282884A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To improve controllability of an erasing level, to set to an optimum erasing level and to prevent excess erasing by applying a high voltage to a source at the time of erasing, and also applying a voltage of a predetermined level to a control gate. CONSTITUTION:Voltage applying means for applying a high voltage VS from a voltage generator to a source S of a memory transistor MT similarly to a conventional example and also applying a voltage VG of a predetermined level to a control gate CG is provided. At the time of erasing, the voltage VG is applied to the gate CG and hence a threshold voltage VTM(t) becomes VTM(t)0+alpha.VG. Thus, the voltage VG is optimally set to prevent excess erasing. Here, the VTM(t)0 indicates a threshold voltage VTM(t) in the case of VG=OV, the alpha is a constant to be decided from a structure of the transistor. The VTM(t), the VTM(t)0 indicate that the threshold voltage is a function of time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device having a structure in which electrically writable and erasable floating gate type memory transistors are arranged.

[0002]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device having a memory transistor capable of electrically writing and erasing, a Fowler-Nordhe is used for writing and erasing.
The method using an im tunnel current has been common. However, in this method, since the memory transistor after writing is in the depletion state due to its operating characteristics,
In order to enable selective reading, it was necessary to provide a selection transistor for each bit. Therefore, a 1-bit memory cell is composed of a selection transistor and a memory transistor, which increases the cell area and hinders the increase in capacity.

As one countermeasure against this, Fla
A sh EEPROM has been proposed.

This cannot be rewritten on a byte-by-byte basis as in the conventional EEPORM, and although it is a batch erasing type, it has attracted attention as a method for connecting a large capacity cell such as an ultraviolet erasing type EPROM and "electrical erasing". ing.

FIG. 5A shows such a Flash EEP.
FIG. 3 is a cross-sectional view of a memory transistor called a self-aligned gate type that can minimize the cell area in the ORM.

The memory transistor MT of this example has an n ⁺ type source region 2 and an n ⁺ type source region 2 near the surface of a P type semiconductor substrate 1.
^{A +} type drain region 3 is provided, and a floating gate electrode 5 is provided on a part of the source region 2 and the drain region 3 on the semiconductor substrate 1 via a first gate insulating film 41. In this structure, the control gate electrode 6 is formed via the second gate insulating film 42. The floating gate electrode 5 and the control gate electrode 6 are formed in a self-aligned manner in the channel length direction.

The operating principle of the memory transistor MT will be briefly described.

The writing operation is a normal ultraviolet erasing type EPRO.
Similar to M, a high voltage is applied to the drain region 3 and the control gate electrode 6, and hot electrons generated in the pinch-off region in the channel are injected into the floating gate electrode 5 by a so-called hot electron injection method. The threshold voltage V _{TM of} MT is increased.

In the erasing operation, as shown in FIG. 5B, a high voltage V _S from a voltage generating circuit (not shown) is applied to the source S with the control gate CG grounded, and the Fowler is turned on.
-The electrons in the floating gate electrode 5 are emitted using the Nordheim type tunnel current. At this time, the relationship between the application time of the high voltage V _S and the threshold voltage V _TM (t) as a time function of the memory transistor MT is defined by the IEEE ISSCC.
89 "A 90ns 100K erase / program cycle Megabit flash memory (A
90ns 100K Erase / Program C
Cycle Megabit Flash Memol
y) "FIG. 5 of" V. Kynett et. al.
Although it is also shown in FIG. That is, the change (V _TM (t)) of the threshold voltage V _TM with respect to the time t has a large change in the initial stage, and the change is very small from a certain point (hereinafter referred to as “bending point TP”). .

At the time of this erasing operation, since the memory transistor MT does not have a selection gate unlike the conventional EEPROM, it is not allowed to reach the depletion state due to "excessive erasing", and negative charges are accumulated in the floating gate electrode 5. It was necessary to stop the erase operation in the remaining state. That is, FIG. 5 (c)
In the above, it was necessary to set the range within the period T4.

Further, in the erase characteristic, as shown in FIG. 6, when the inflection point TP is further above the erase upper limit EU, the margin for "excessive erase" is large as T6, but the erase upper limit EU is large.
Until the end of the erase, that is, the time required to complete the erase is T5, which is very large, and the erase operation speed becomes slow.

[0012]

In this conventional nonvolatile semiconductor memory device, the controllability of erasing in the erasing operation has been a serious problem.

As described above, when erasing the contents of the memory transistor MT, it is necessary to stop the erasing before it becomes a depletion type in principle. I had to stop erasing. At this time, the lower limit of erasing is limited by the "turn-on phenomenon" at the time of writing.

That is, when considering the memory cell matrix, the potential of the floating gate is raised and the channel is made conductive just by applying a high voltage to the drain like a non-selected memory transistor on the same digit line at the time of writing. It may happen. This is called the "turn-on phenomenon". If this phenomenon occurs in the state where the memory cell matrix is configured, the voltage of the digit line decreases due to the turn-on current, and writing cannot be performed sufficiently. There was a problem.

In order to avoid this "turn-on phenomenon", the erase level must be stopped at a sufficiently high value. However, even if the lower limit of the erase level becomes high, the upper limit is defined by the read condition, and the existence of the "turn-on phenomenon" consequently narrows the allowable range of the erase level. It was

As the capacity of a memory has recently been increased, the number of memory transistors connected to one digit line is increased although the variation in erase level is inevitably increased. -The "on phenomenon" will impose stricter restrictions.

Therefore, in the erasing operation of the conventional nonvolatile semiconductor memory device, the controllability of the erasing level is difficult, and it has been a factor that hinders an increase in capacity from the viewpoint of operation.

Further, when the bending point TP is above the upper limit EU of erasing, there is a problem that the time until reaching the upper limit EU of erasing becomes long and the erasing operation speed becomes slow.

The object of the present invention is to improve the controllability of the erase level during the erase operation, to set the optimum erase level, to facilitate a large capacity, and even when the bending point is above the upper limit of erase. A non-volatile semiconductor memory device capable of increasing the erase operation speed is provided.

[0020]

A nonvolatile semiconductor memory device according to the present invention includes a source region and a drain region of opposite conductivity type formed on a semiconductor substrate of one conductivity type, and the semiconductor between the source region and the drain region. A non-volatile memory transistor in which a floating gate electrode formed on a substrate via a first gate insulating film and a control gate electrode formed on the floating gate electrode via a second gate insulating film are arranged in a nonvolatile manner. In the semiconductor memory device, a voltage application unit is provided for applying an erase voltage to the source region and applying a voltage of a predetermined level and a predetermined polarity to the control gate electrode during an erase operation.

[0021]

Embodiments of the present invention will now be described with reference to the drawings.

1 (a), 1 (b) and 1 (c) are a cross-sectional view of a memory transistor of a first embodiment of the present invention, a circuit diagram during its erase operation and an erase characteristic diagram, respectively.

The structure of this memory transistor MT is shown in FIG.
This is similar to the memory transistor MT of the conventional nonvolatile semiconductor memory device shown in (a).

This embodiment is different from the conventional nonvolatile semiconductor memory device shown in FIGS. 5B and 5C in that the source S of the memory transistor MT is connected to the voltage generating circuit as in the conventional example. the high voltage V _S is applied with a voltage V _G of a predetermined level from the voltage generating circuit to the control gate CG of the
A voltage applying means (partly omitted in the drawing) for applying is provided, and the erase characteristic is changed so that the erase level can be easily controlled.

Next, the memory transistor MT of this embodiment
The operation will be described.

First, regarding the write operation, a high voltage V _S is applied to the drain region 3 and the control gate electrode 6 as in the conventional example, and hot electrons generated in the pinch-off region in the channel are injected into the floating gate electrode 5. To do. The so-called hot electron injection is performed to raise the threshold voltage V _TM of the memory transistor.

In the erase operation, as shown in FIG. 1B, a high voltage V _S is applied to the source S and a predetermined level voltage V _G is applied to the control gate CG. By applying the voltage V _G to the control gate CG, the threshold voltage V _TM (t) becomes V
_{TM (t) 0 + α ·} V G becomes, can be arbitrarily set by the value of the voltage V _G (Note: V _TM (t) ₀ represents the threshold voltage V _TM (t) in the case of V _G = 0V, alpha is A constant determined by the structure of the memory transistor, and V _TM (t) and V _TM (t) ₀ are
It shows that the threshold voltage is a function of time).

The margin for "over-erase" in the erase operation is better as the period T1 when the threshold voltage V _TM (t) is between the erase upper limit EU and the erase lower limit EL is longer, and the "speed" of the erase operation is higher. Is a threshold voltage V _TM (t)
The shorter the time t until the erase upper limit EU reaches, the better.

For example, the voltage V _G applied to the control gate CG during the erase operation is optimally set, and as shown in FIG. 1C, the inflection point TP of the threshold voltage V _TM (t) is set near the erase upper limit EU. By setting it, the margin can be maximized against "over-erasing" without sacrificing "speed". Specifically, the margin for “excessive erasing” is much longer than the period T4 of FIG. 1 (c) in the conventional example, which is the period T4 of FIG. 5 (c).
The effect is tremendous.

FIG. 2 is a circuit diagram for simultaneously erasing the contents of each memory transistor of this embodiment.

In this way, each memory transistor MT1
The source S of 1, MT12, MT21, MT22 is erased by applying the high voltage V _S to the source S and the voltage V _G to the control gate CG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, each of a plurality of memory transistors MT11, MT12, MT21, MT22 arranged in a predetermined unit number (two in this embodiment) of memory transistors (MT11, MT21), (MT12, MT22). The voltages V _G 1 and V _G 2 of corresponding predetermined levels are applied to the control gate CG.

As described above, in the case of the memory cell matrix in which a plurality of memory transistors are arranged, there is a large variation in the erase characteristics as a whole, and the margin for "excessive erase" tends to be small. Since the erasing characteristics can be optimized by the voltage V _G applied to the control gate CG for each set, it is possible to further increase the margin for “excess erasing”.

FIGS. 4A and 4B are a circuit diagram and an erase characteristic diagram, respectively, during the erase operation of the memory transistor of the third embodiment of the present invention.

In this embodiment, the bending point T in the erase characteristic is
As shown in FIG. 6, P is applied to the memory transistor MT which is further above the upper limit EU of erasing.

In this embodiment, as shown in FIG. 4A, the voltage V _S is applied to the source S and the control gate CG is applied.
Applying a certain negative voltage -V _G to. As a result, the threshold voltage V _TM (t) is to set the value of _{V TM (t) O + α} · (-V G) next to -V _G to an appropriate value, the optimum erasing characteristic as shown in FIG. 4 (b) Becomes That is, the time required to reach the erase upper limit EU, that is, the time until the erase is completed can be shortened to T2 while the margin for "excessive erase" remains large at T3. This embodiment is naturally applicable to the memory cell matrix shown in FIGS. 2 and 3 in which a plurality of memory transistors MT are arranged.

That is, the erase operation in the case of the memory cell matrix of FIG. 2 is performed by the memory transistors MT11 and MT1.
2, MT21, a high voltage V _S is applied to the source S of the MT22, performed by applying a negative voltage (-V _G) as a certain voltage V _G to the control gate CG of the memory transistor. At this time, the drains D of these memory transistors are in a floating state. As described above, in the case of a memory cell matrix in which a plurality of memory transistors MT are arranged, the variation in the erase characteristic as a whole may be large and the margin with respect to the erase speed may be small, but in the present invention, it is applied to the control gate CG. The erasing speed can be increased because the erasing characteristics can be optimized by the negative voltage V _G.

Further, in FIG. 3, the gate voltage V _G applied during the erase operation is set to the memory transistors MT11 and MT.
Negative V _G 1 to the control gate CG of 21, the memory transistors MT21, MT22 negative V _G to the control gate CG of the
As described in 2, it is possible to apply the gate voltage V _G separately so that the erase characteristics are optimized. In this way, by dividing and applying the gate voltage, each divided memory transistor can be optimized, so that the effect of improving the erasing characteristic is further improved for the entire memory cell matrix.

[0040]

As described above, according to the present invention, a high voltage is applied to the source region and a voltage of a predetermined level is applied to the control gate electrode during the erase operation. Since the change of the threshold voltage of 1 with respect to time can be set to the optimum state, there is an effect that the controllability of the erase level is improved, and therefore the capacity can be easily increased.

When the bending point in the erase characteristic is above the erase upper limit, by applying a negative voltage to the control gate electrode, the time until the erase upper limit is reached can be shortened and the erase operation speed can be increased. Has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a memory transistor of a first embodiment of the present invention, a circuit diagram at the time of its erase operation, and an erase characteristic diagram.

FIG. 2 is a circuit diagram during an erase operation according to the first embodiment of this invention.

FIG. 3 is a circuit diagram during an erase operation according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram and an erase characteristic diagram during an erase operation of a memory transistor according to a third embodiment of the present invention.

FIG. 5 is a cross-sectional view of a memory transistor of a first example of a conventional nonvolatile semiconductor memory device, a circuit diagram at the time of its erase operation, and an erase characteristic diagram.

FIG. 6 is an erase characteristic diagram of a memory transistor of a second example of a conventional nonvolatile semiconductor memory element.

[Explanation of symbols]

1 semiconductor substrate 2 source region 3 drain region 4 insulating film 5 floating gate electrode 6 control gate electrode 41, 42 gate insulating film CG control gate D drain FG floating gate MT11, MT12, MT21, MT22 memory transistor S source

Claims (2)

[Claims] 1. A source region and a drain region of opposite conductivity type formed on a semiconductor substrate of one conductivity type, and a first gate insulating film formed on the semiconductor substrate between the source region and the drain region. In a nonvolatile semiconductor memory device in which a memory transistor including a floating gate electrode and a control gate electrode formed on the floating gate electrode via a second gate insulating film is arranged,
A non-volatile semiconductor memory device comprising: a voltage application unit that applies an erasing voltage to the source region and also applies a voltage of a predetermined level and a predetermined polarity to the control gate electrode. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage applying means is configured to apply a voltage of a predetermined level and a predetermined polarity for each predetermined unit number of memory transistors.