JPH04129095A - Erasing method for semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the variance in erase characteristic of a semiconductor storage device by applying a positive voltage to a control gate simultaneously with application of a high voltage to the source or the drain of a non-volatile storage element. CONSTITUTION:A substrate 1 is set to a reference potential, and enough positive potential to migrate electrons stored in a floating gate 5 to a channel area as the tunnel current flowing through a tunnel insulating film 7 is applied to at least one of a source 2 and a drain 3. A positive voltage slightly higher than the threshold voltage of the non-volatile memory element before write is applied to a control gate 4. Since the channel area between the source 2 and the drain 3 is made conductive in the process of reduction of the threshold voltage, the electric field applied to the tunnel insulating film 7 is distributed on almost all of the surface. Thus, the variance in erase characteristic among storage elements is reduced to prevent the degradation in characteristic of the semiconductor memory device.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of the erasing method of a semiconductor memory device, the purpose of this invention is to provide an erasing method of a semiconductor memory device that reduces variations in the erasing characteristics of the semiconductor memory device. In an erasing method for a semiconductor memory device that electrically erases information written in a semiconductor memory device having a nonvolatile memory element having a floating gate interposed between a control gate and a channel region of an effect transistor, With the substrate of the semiconductor memory device as a reference potential, at least one of the source and the train,
A positive potential sufficient to move the electrons accumulated in the floating gate to the channel region as a tunnel current flowing through the tunnel insulating film is applied to the control gate to perform the write operation. The configuration is such that a positive voltage slightly higher than the threshold voltage of the nonvolatile memory element before it is applied is applied.

[Industrial Application Field 1] The present invention aims to improve the erasing method of semiconductor memory devices, and more specifically, to improve the erasing method of semiconductor memory devices. The present invention relates to an improvement in nonvolatile memory elements that store information in binary format, which reduces variations in erase characteristics when erasing stored information by removing electrons injected into the floating gate.

[Conventional technology]

FIG. 4 shows a cross-sectional view of a nonvolatile memory element constituting a semiconductor memory device. 1 is a substrate, 2 is a source, and 3
is a train, 4 is a control gate, 5 is a floating gate, 6 is a gate interlayer insulating film, and 7 is a tunnel insulating film.

When writing information, either set the potential of the train 3 floating and apply a positive potential of about 20V to the control gate 4 with the source 2 as a reference potential, or set the source 2 as a reference potential and connect the train 3 and the control gate 4. By applying positive potentials of about 8 V and about 20 V, respectively, electrons are injected into the floating gate 5 as a tunnel current flowing through the tunnel insulating film 7. Even if the applied voltage is removed, the electrons injected into the floating gate 5 are stored for a long time, and information is stored semi-permanently.

To erase the written information, it is necessary to remove the electrons accumulated in the floating gate 5. To remove these electrons, the potential of the train 3 is made floating, and the control gate 4 is set as a reference. A method is used in which a positive potential of about 12 V is applied to the source 2 and the electrons accumulated in the floating gate 5 are caused to flow out to the source 2 as a tunnel current flowing through the tunnel insulating film 7. .

[Problem to be solved by the invention]

FIG. 3 shows the relationship between the erasing time t, w and the change in threshold voltage VTH when erasing information written in a non-volatile memory element constituting a semiconductor memory device using the above method. , V TMI is the threshold voltage before writing, and VtW is the threshold voltage after writing. As shown in the figure, the threshold voltage V ? llll has the characteristic of rapidly decreasing as it approaches the erased state, that is, the threshold voltage V before writing, so a slight change in the erase time can cause the threshold voltage during erasing to increase. It has the disadvantage of being variable. Furthermore, if the erasing time is too long, the threshold voltage becomes negative, resulting in a disadvantage that the memory element becomes a deplesicon type.

The purpose of the present invention is to eliminate these drawbacks,
An object of the present invention is to provide an erasing method for a semiconductor memory device that reduces variations in erasing characteristics of the semiconductor memory device.

[Means to solve the problem]

The above purpose is to control the control gate (4) and channel region (8) of an n-channel enhancement field effect transistor.
In a semiconductor memory device erasing method for electrically erasing information written in a semiconductor memory device having a nonvolatile memory element with a floating gate (5) interposed between the
With the substrate (1) of the semiconductor memory device as a reference potential,
At least one of the source (2) and the train (3),
Applying a positive voltage sufficient to move the electrons accumulated in the floating gate (5) to the channel region (8) as a tunnel current flowing through the tunnel insulating film (7), and , by an erasing method of a semiconductor memory device in which a positive voltage slightly higher than the threshold voltage (Vt, I+) of the nonvolatile memory element before the writing is applied to the control gate (4). achieved.

[Effect]

When a high voltage is applied to the source 2 or train 3 of the non-volatile storage element to erase the written information,
The electric field is concentrated between the region 'opposing the floating gate 5 of the source 2 or train 3 and the floating gate 5, and the electric field strength across the tunnel insulation #7 in this region becomes high.
The electrons accumulated in the floating gate 5 are transferred to the tunnel insulating film 7.
The tunnel current rapidly flows through the source 2 or train 3 as a tunnel current, and the threshold voltage rapidly decreases with time, as shown by the curve connecting points A and B in FIG. However, if a positive voltage slightly higher than the threshold voltage V TMI of the nonvolatile memory element before writing is applied to the control gate 4, the source 2 and Since the channel region between the train 3 becomes conductive, the electric field across the tunnel insulation 11!7 is distributed over the entire surface, and the electric field is no longer concentrated locally. Since the electric field strength across the film 7 becomes lower, the tunnel current through which the electrons accumulated in the floating gate 5 pass through the tunnel insulating film 7 decreases, and the threshold voltage of the memory element becomes as shown in FIG. It gradually decreases like a curve connecting points B and C. Therefore, by erasing with an erasing time corresponding to a region where the threshold voltage decreases slowly, it is possible to reduce variations in the threshold voltage after erasing even if the erasing time varies somewhat.

〔Example〕

Hereinafter, a method for erasing a semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings.

See FIG. 2 FIG. 2 is a sectional view of a nonvolatile memory element forming a semiconductor memory device. To give an example of a specific structure, l is a p-type silicon substrate, 7 is an approximately 100% artificial tunnel insulating film, 5 is a floating gate made of approximately 2000% polycrystalline silicon, 6 is a gate interlayer insulating film of about 300 mm thickness, and 4 is a control gate made of polycrystalline silicon with a thickness of about 3.000 mm. 2 is a source, 3 is a train, and in both cases, using the gates 4 and 5 as masks, arsenic ions are implanted at an energy of 70 KeV and a dose of 4X 10
It is formed by ion implantation with 1 scs-''.

8 is a channel region.

A method for erasing a semiconductor memory device in a written state, that is, in a state in which electrons are accumulated in the floating gate 5, will be explained below.

The substrate 1 is set to a reference potential, the train 3 is made floating, and the control gate 4 and source 2 are connected to 2 and 12, respectively.
A positive potential of V is applied for 100 milliseconds. As a result, the threshold voltage of the nonvolatile memory element returned to the value before writing, and the variation in threshold voltage between the memory elements became small enough to be practically acceptable.

Note that with the source 2 floating, the control gate 4
and train 3 with positive potentials of 2v and 12V, respectively.
It goes without saying that the voltage may be applied for 0 milliseconds.

The voltage applied to the source 2 or the train 3 only needs to be a voltage sufficient to move the electrons stored in the floating gate 5 to the channel region 8 as a tunnel current flowing through the tunnel insulation M7. Further, the voltage applied to the control gate 4 is preferably selected to be slightly higher than the threshold voltage VtW+ of the nonvolatile memory element before writing is performed.

〔Effect of the invention〕

As explained above, in the method of erasing a semiconductor memory device according to the present invention, by applying a high voltage to the source or train of the nonvolatile memory element constituting the semiconductor memory device and simultaneously applying a positive voltage to the control gate, Since the slope of the threshold voltage drop with respect to the erase time can be made gentler, even if the erase time varies slightly, the fluctuation width of the threshold voltage after erasing can be suppressed to a small extent, which improves the erase characteristics between each memory element. It becomes possible to reduce the variation in the characteristics of the semiconductor memory device and prevent the characteristics of the semiconductor memory device from deteriorating.

[Brief explanation of drawings]

FIG. 1 is a graph showing the relationship between erasing time and threshold voltage when using the erasing method for a semiconductor memory device according to the present invention. FIG. 2 is a diagram showing voltages applied to a nonvolatile memory element in the erasing method for a semiconductor memory device according to the present invention. FIG. 3 is a graph showing the relationship between erasing time and threshold voltage when using the prior art erasing method for a semiconductor memory device. FIG. 4 is a cross-sectional view of the nonvolatile memory element. Semiconductor substrate, source, train, control gate, floating gate, gate interlayer insulation film, tunnel insulation film, channel region.

Claims (1)

[Claims] [1] A semiconductor memory having a nonvolatile memory element formed by a floating gate (5) interposed between a control gate (4) and a channel region (a) of an n-channel enhancement field effect transistor. In an erasing method for a semiconductor memory device in which information written in the device is electrically erased, a substrate (1) of the semiconductor memory device is set as a reference potential, and at least one of a source (2) and a train (3) is connected to the substrate (1) of the semiconductor memory device. A positive potential sufficient to move the electrons accumulated in the floating gate (5) to the channel region (8) as a tunnel current flowing through the tunnel insulating film (7) is applied to the control gate. (4) is the threshold voltage (V_T_) of the nonvolatile memory element before the writing is performed.
A method for erasing a semiconductor memory device, characterized by applying a positive voltage slightly higher than M_1).