JP2646829B2 - High breakdown voltage thin film transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a thin film transistor used for driving a printer head, an electroluminescence display, and the like, and in particular, has a high breakdown voltage and can improve transistor characteristics. The present invention relates to a high breakdown voltage thin film transistor.

(Prior Art) Regarding the configuration of a conventional high breakdown voltage thin film transistor,
This will be described with reference to the cross-sectional view of the conventional thin film transistor shown in FIG.

As shown in FIG. 6, chromium (C
r) and a gate insulating film 3 of silicon nitride (SiNx) covering the gate electrode 2;
A first amorphous semiconductor layer 4 of amorphous silicon (a-Si) deposited on the gate insulating film 3 and SiNx for protecting the first amorphous semiconductor layer 4 provided on the gate electrode 2 portion. Channel protective film 5 and a second amorphous semiconductor layer 6 of n ⁺ amorphous silicon (n ⁺ a-Si) for ohmic contact provided on the first amorphous semiconductor active layer 4 and mixed with a high concentration of impurities. And a chromium (Cr) diffusion preventing layer 7 for preventing the aluminum (Al) wiring metal layer 8 provided on the second amorphous semiconductor layer 6 from diffusing into the second amorphous semiconductor layer 6. The second amorphous semiconductor layer 6, the diffusion preventing layer 7, and the wiring metal layer 8 divided by the channel protective film 5 constitute a source electrode 9 and a drain electrode 10, respectively. What is generally called an “inverted stagger type” is known.

In response to a high voltage applied to the drain electrode 10, a channel region (region length L1) above the gate electrode 2
In addition, the resistance is increased by providing an offset region (region length L2) between the gate electrode 2 and the drain electrode 10,
It was a high breakdown voltage thin film transistor.

(Problems to be Solved by the Invention) However, in the above-mentioned conventional high-breakdown-voltage thin-film transistor, a high-breakdown-voltage thin film transistor driven at a high voltage of 300 V or more as an inverter such as an electrostatic plotter has a channel region length L1 and an offset region length L2. There has been a problem that the optimization has not been sufficiently studied and the characteristics of the high breakdown voltage thin film transistor cannot be further improved.

The present invention has been made in view of the above circumstances,
It is an object of the present invention to provide a high-breakdown-voltage thin film transistor that can be driven at 0 V to 500 V and has a channel region length and an offset region length optimized.

(Means for Solving the Problems) According to the present invention for solving the problems of the conventional example, a gate electrode, a gate insulating film, a first amorphous semiconductor layer, and a channel protective film are formed on a substrate, and the channel protection is performed. A second amorphous semiconductor layer as a source electrode and a drain electrode, a diffusion prevention layer, and a metal layer are formed with the film interposed therebetween, and an end of the gate electrode on the drain electrode side from an end of the channel protective film on the source electrode side. A region from the end of the channel protective film on the drain electrode side to the end of the gate electrode on the drain electrode side as an offset region. Area length 14 ~ 20μ
m, wherein the length of the offset region is 20 to 30 μm.

(Action) According to the present invention, the region length (channel region) from the end of the channel protective film on the source electrode side to the end of the gate electrode on the drain electrode side is 14 to 20 μm, and the channel on the drain electrode side is Since the region length of the region (offset region) from the end of the protective film to the end of the gate electrode on the drain electrode side is set to 20 to 30 μm and the channel voltage and the offset region length are optimized, the high breakdown voltage thin film transistor is used. Transistor characteristics can be obtained and the HIGH / LOW ratio of the inverter can be increased.

(Example) An example of the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory sectional view of a high breakdown voltage thin film transistor according to one embodiment of the present invention. Parts having the same configuration as in FIG. 6 will be described with the same reference numerals.

As shown in FIG. 1, the high-breakdown-voltage thin film transistor of this embodiment includes a gate electrode 2 formed of chromium (Cr) or the like on a substrate 1 of glass or the like, and a silicon nitride film (SiNx) covering the gate electrode 2. ), A first amorphous semiconductor layer 4 of amorphous silicon (a-Si) deposited on the gate insulating film 3, and a first amorphous semiconductor provided on the gate electrode 2 portion. A channel protection film 5 of SiNx for protecting the layer 4 and n ⁺ amorphous silicon (n ⁺ a-Si) for ohmic contact provided on the first amorphous semiconductor layer 4 and containing a high concentration of impurities. Of the second amorphous semiconductor layer 6 and the second
A diffusion prevention layer 7 of chromium (Cr) for preventing the metal layer 8 for wiring of aluminum (Al) provided on the amorphous semiconductor layer 6 from diffusing into the second amorphous semiconductor layer 6 is formed. The second divided by
The amorphous semiconductor layer 6, the diffusion preventing layer 7, and the wiring metal layer 8 constitute a source electrode 9 and a drain electrode 10, respectively, and are of "inverted stagger type".

Then, in response to a case where a high voltage is applied to the drain electrode 10, a channel region (region length L1) above the gate electrode 2
In addition, the resistance is increased by providing an offset region (region length L2) between the gate electrode 2 and the drain electrode 10, thereby forming a high breakdown voltage thin film transistor.

The channel region in this embodiment refers to a region from the end of the channel protective film 5 on the source electrode 9 side to the end of the gate electrode 2 on the drain electrode 10 side, and the offset region refers to the channel on the drain electrode 10 side. The region from the end of the protective film 5 to the end of the gate electrode 2 on the drain electrode 10 side.

Next, a method of manufacturing the high-breakdown-voltage thin-film transistor of this embodiment will be described.

First, Cr is vapor-deposited on the substrate 1 of glass or the like to about 500 °. The gate electrode 2 is formed through a photolithography process. On top of this, about 3000 Si of SiNx as the gate insulating film 3, about 500 を of a-Si as the first amorphous semiconductor layer 4 and about 1500 Si of SiNx as the channel protective film 5 by the plasma CVD (P-CVD) method. Continuous deposition.

A resist is applied to this upper portion, and is exposed and developed to form a resist pattern, and a pattern of the channel protective film 5 is formed according to the resist pattern. In this case, the channel region length and the offset region are calculated and the channel protective film is calculated.
25 size shall be decided.

A phosphine-doped n ⁺ amorphous silicon (n ⁺ a) is formed on this as a second amorphous semiconductor layer 6.
-Si) is deposited to a thickness of about 1000 ° by the P-CVD method. On this, Cr serving as the diffusion preventing layer 7 is deposited by about 1500 °.
A photoresist is applied thereon, a resist pattern is formed so as to open the upper portion of the channel protective film 5, and Cr of the diffusion preventing layer 7 and n ⁺ a-Si of the second amorphous semiconductor layer 6 are etched.

On top of that, a metal layer 8 for wiring of aluminum (Al) is
A film of about 1 μm is deposited by magnetron sputtering, and a photoresist is applied thereon. The wiring metal layer 8 is patterned and etched by a photolithography process and an etching process so as to open the upper central portion of the channel protective film 5, and the shapes of the drain electrode 10 and the source electrode 9 are formed.

Thus, the high-breakdown-voltage thin-film transistor of this embodiment is manufactured.

Next, the channel region length L1 and the offset region length L2 in the high breakdown voltage thin film transistor at a high voltage of 300 V to 500 V
2 will be described with reference to FIGS.

FIG. 2 is a diagram showing the L2 dependence of the ON and OFF current values. When a voltage of 400 V is applied between the source electrode 9 and the drain electrode 10, the gate electrode when the offset region length L2 is made variable. ON current (I ON) when the voltage of 2 (Vg) is 20V
The change in the OFF current (I OFF) when the voltage (Vg) of the gate electrode 2 is 0 V is shown in FIG.
This is indicated by the dotted line at the bottom of the figure. In FIG. 2, the channel region length L1 = 17 μm and the channel width W = 352 μm.

According to FIG. 2, the ON current (I ON) decreases when the offset region length L2 exceeds the boundary of 20 to 30 μm, and the OFF current (I OFF) decreases when L2 exceeds 20 μm. When L2 is 20 μm or less, the OFF current (I
OFF) increases. Therefore, it is appropriate to set the offset region length L2 to 20 to 30 μm.

FIG. 3 is a diagram showing the L1 dependency of the ON resistance value (Rt) of the transistor after stress. When the channel region length L1 is variable, 400 V is applied between the source electrode 9 and the drain 10 of the high breakdown voltage thin film transistor. 3 shows the ON resistance value (Rt) of the transistor after the transistor is turned off and stressed by applying the voltage for 30 minutes. In FIG. 3, the offset region length L2 = 25 μm and the channel width W = 352 μm.

According to FIG. 3, when the channel region length L1 is increased, Rt
It can be seen that the value decreases and becomes small and constant above 17 μm. Therefore, the channel region length L1
Is preferably set to 17 μm or more, but considering the high density of the transistor, the channel region length L1 is preferably as small as possible.

From the above description, the optimal value is that the channel region length L1 is 17μ
m, the offset region length L2 is 25 μm, and considering allowance, L1 is 14 to 20 μm and L2 is 20 to 30 μm.

Channel region length L1 is 17 μm, offset region length L2 is 25
Figure 4 shows the gate voltage (Vg) -drain current (Ids) characteristics when optimized to μm, and the gate voltage (Vg)
FIG. 5 shows the drain voltage (Vds) / drain current (Ids) characteristics when V is set to 6 V, 10 V, and 15 V.

From FIGS. 4 and 5, it can be seen that the high breakdown voltage thin film transistor in which the device parameters are optimized exhibits good transistor characteristics.

Further, the high breakdown voltage thin film transistor having this optimum value can obtain good transistor characteristics even when operated up to 500V.

The configuration of the high-breakdown-voltage thin-film transistor of this embodiment is as follows.
The invention can be applied to a “stagger type” transistor.

According to the present embodiment, the channel region length L1 of the high-breakdown-voltage thin film transistor that is driven at a high voltage of 300 V to 500 V in practice is set to 14 to
Since the channel region length L1 and the offset region length L2 are optimized by setting 20 μm and the offset region length L2 to 20 to 30 μm, good transistor characteristics can be obtained in a high withstand voltage condition, and the inverter high / low ratio can be obtained. Has the effect of being able to take large amounts.

(Effect of the Invention) According to the present invention, the region length (channel region) from the end of the channel protective film on the source electrode side to the end of the gate electrode on the drain electrode side is set to 14 to 20 μm, The region length of the region (offset region) from the end of the channel protective film to the end of the gate electrode on the drain electrode side is set to 20 to 30 μm, and the high breakdown voltage thin film transistor has an optimized channel region length and offset region length. This has the effect that good transistor characteristics can be obtained and the HIGH / LOW ratio of the inverter can be increased.

[Brief description of the drawings]

FIG. 1 is an explanatory cross-sectional view of a high-breakdown-voltage thin-film transistor according to one embodiment of the present invention, FIG. 2 is a diagram showing L2 dependence of ON and OFF current values, and FIG.
Diagram showing L1 dependence of ON resistance value (Rt), FIG. 4 shows gate voltage and drain current characteristics of high breakdown voltage thin film transistor using optimized device parameter values, and FIG. 5 shows optimization FIG. 6 is a diagram showing drain voltage / drain current characteristics of a high breakdown voltage thin film transistor using the obtained device parameter values, and FIG. 6 is a sectional explanatory view of a conventional high breakdown voltage thin film transistor. DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... 1st gate electrode 3 ... Gate insulating film 4 ... 1st amorphous semiconductor layer 5 ... Channel protective film 6 ... 2nd amorphous semiconductor layer 7 ... Diffusion prevention layer 8 ... Wiring Metal layer 9 Source electrode 10 Drain electrode

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-83941 (JP, A) JP-A-63-226071 (JP, A) JP-A-58-115864 (JP, A) JP-A-63-1988 221677 (JP, A) JP-A-4-125970 (JP, A) JP-A-4-154128 (JP, A)

Claims (1)

(57) [Claims] A gate electrode, a gate insulating film, a first electrode,
An amorphous semiconductor layer and a channel protection film are formed, a second amorphous semiconductor layer as a source electrode and a drain electrode, a diffusion prevention layer, and a metal layer are formed with the channel protection film interposed therebetween; and the channel protection film on the source electrode side is formed. A region from the end of the gate electrode on the drain electrode side to the end of the gate electrode on the drain electrode side, and a region from the end of the channel protective film on the drain electrode side to the end of the gate electrode on the drain electrode side. A high-breakdown-voltage thin-film transistor comprising: an offset region, wherein the region length of the channel region is 14 to 20 μm, and the region length of the offset region is 20 to 30 μm.