JPH04154174A - High withstand voltage thin film transistor - Google Patents

Abstract

PURPOSE:To drive at 300-500V in practice by forming the length of a channel region 14-20mum, forming the length of an offset region 20-30mum, and optimizing the lengths of the channel region and the offset region. CONSTITUTION:A source electrode 9 and a drain region 10 are formed of a second amorphous semiconductor layer 6, a diffusion preventive layer 7 and a wiring metal layer 8 divided by a channel protective film 5 in a gate insulating film 3, a first amorphous semiconductor layer 4 formed on a substrate 1. A channel is formed in a region from the end of the film 5 at the side of the electrode 9 to the end of a gate electrode 3 at the side of the electrode 10, and the length of the region is formed 14-20mum. An offset region is formed in a region from the end of the film 5 at the side of the electrode 10 to the end of the electrode 2 at the side of the electrode 10, and the length of the region is formed 20-30mum. Thus, the lengths of the channel region and the offset region are optimized to obtain excellent transistor characteristics, and HIGH/ LOW ratio of an inverter can be increased.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a thin film transistor used for driving printer heads, electroluminescent displays, etc., and in particular has a high breakdown voltage and is capable of improving transistor characteristics. This article relates to high-voltage thin film transistors that can be used.

(Prior Art) The structure of a conventional high-voltage thin film transistor will be described with reference to a cross-sectional diagram of a conventional thin film transistor shown in FIG.

As shown in FIG. 6, chromium (C'
), a gate insulating film 3 made of a silicon nitride film (SiNx) covering the gate electrode 2, and a gate insulating film 3 made of amorphous silicon (a-Si) deposited on the gate insulating film 3. A first amorphous semiconductor layer 4 , a channel protection film 5 of SiNx for protecting the first amorphous semiconductor layer 4 provided above the gate electrode 2 portion, and a SiNx channel protection film 5 provided on the first amorphous semiconductor active layer 4 A second layer of n+ amorphous silicon (n''a-5i) for ohmic contact mixed with high concentration of impurities.
A chromium (Cr) diffusion prevention layer that prevents the amorphous semiconductor layer 6 and the aluminum (AI) wiring metal layer 8 provided on the second amorphous semiconductor layer 6 from diffusing into the second amorphous semiconductor layer 6. A second amorphous semiconductor layer 6, a diffusion prevention layer 7, and a wiring metal layer 8, each of which is divided by a channel protective film 5, constitute a source electrode 9 and a drain electrode 10, respectively. What is known as "Kata" is known.

In response to the case where a high voltage is applied to the drain electrode 10, a channel region (region length Ll) above the gate electrode 2 is provided.
) In addition to this, an offset region (region length L2) is provided between the gate electrode 2 and the drain electrode 10 to increase resistance and provide a high breakdown voltage thin film transistor.

(Problems to be Solved by the Invention) However, in the above conventional high voltage thin film transistor, the channel region length L1 and the offset region length L2 are There has been a problem in that optimization has not been sufficiently studied and the characteristics of high voltage thin film transistors cannot be further improved.

The present invention has been made in view of the above-mentioned circumstances, and is practical.
An object of the present invention is to provide a high voltage thin film transistor that can be driven from 0V to 500V and has an optimized channel region length and offset region length.

(Means for Solving the Problems) The present invention for solving the problems of the conventional example described above includes forming a gate electrode, a gate insulating film, a first amorphous semiconductor layer, and a channel protective film on a substrate, A second amorphous semiconductor layer, a diffusion prevention layer, and a metal layer are formed as a source electrode and a drain electrode with the film in between, and from the end of the channel protection film on the source electrode side to the end of the gate electrode on the drain electrode side. In a high-voltage thin film transistor, the region from the end of the channel protective film on the drain electrode side to the end of the gate electrode on the drain electrode side is an offset region. Area length 14~20μ
m, the offset region has a region length of 20 to 30 μm.

(Function) According to the present invention, the length of the region (channel region) from the end of the channel protection film on the source electrode side to the end of the gate electrode on the drain electrode side is set to 14 to 20 μm, and the channel protection film on the drain electrode side The length of the region (offset region) from the end of the protective film to the end of the gate electrode on the drain electrode side is set to 20 to 30 μm, resulting in a high breakdown voltage thin film transistor with optimized channel region length and offset region length. It is possible to obtain excellent transistor characteristics, and the HIGH/LOW ratio of the inverter can be increased.

(Example) An example of the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory cross-sectional view of a high voltage thin film transistor according to an embodiment of the present invention. Components having the same configuration as those in FIG. 6 will be described with the same reference numerals.

As shown in FIG. 1, the high voltage thin film transistor of this embodiment includes a gate electrode 2 formed of chromium (Cr) or the like on a substrate 1 such as glass, and a silicon nitride film (S) covering the gate electrode 2. amorphous silicon (a-S) deposited on the gate insulating film 3;
i) first amorphous semiconductor layer 4 and the first amorphous semiconductor layer 4 provided above the gate electrode 2 portion;
and a second layer of n+ amorphous silicon (n''a-5i) for ohmic contact mixed with a high concentration of impurity, provided on the first amorphous semiconductor layer 4 to protect the The amorphous semiconductor layer 6 and the wiring metal layer 8 of aluminum (AI) provided on the second amorphous semiconductor layer 6 are connected to the second amorphous semiconductor layer 6.
A diffusion prevention layer 7 of chromium (Cr) is formed to prevent diffusion into the amorphous semiconductor layer 6, and a channel protective film 5 is formed.
The second amorphous semiconductor layer 6, the diffusion prevention layer 7, and the wiring metal layer 8, which are formed separately, constitute the source electrode 9 and the train electrode 10, respectively, and are of an "inverted stagger type."

In response to the case where a high voltage is applied to the drain electrode 10, a channel region (region length Ll) above the gate electrode 2 is provided.
) In addition to this, an offset region (region length L2) is provided between the gate electrode 2 and the drain electrode 10 to increase the resistance and provide a high breakdown voltage thin film transistor.

The channel region in this embodiment refers to the region from the end of the channel protective film 5 on the source electrode 9 side to the end of the gate electrode 2 on the drain electrode 10 side, and the offset region refers to the channel region on the train electrode 10 side. This refers to the region from the end of the protective film 5 to the end of the gate electrode 2 on the drain electrode 10 side.

Next, a method for manufacturing the high voltage thin film transistor of this example will be described.

First, Cr is evaporated to a thickness of about 500 Å on a substrate 1 made of glass or the like. Gate electrode 2 is formed through a photolithography process. On top of that, SiNx is deposited as a gate insulating film 3 of approximately 3000A using the plasma CVD (P-CVD) method.
The first amorphous semiconductor layer 4 is made of a-5i with a thickness of about 500
A, about 150 SiNx as the channel protective film 5
Continuous film deposition at approximately 0A.

A resist is applied on top of this, exposed and developed to form a resist pattern, and a pattern of the channel protective film 5 is formed according to the resist pattern. In this case, the channel protective film 25 is calculated by calculating the channel region length and offset region.
The size shall be determined.

A second amorphous semiconductor layer 6 is formed on top of this, and a phosphine-doped n+ amorphous silicon (n
"a-3i)" is deposited as a film of about 1000A by P-CVD method.On top of this, a film of about 150A of Cr, which will become the diffusion prevention layer 7, is deposited.
Deposit about 0A. Apply photoresist on top of it,
A resist pattern is formed so as to open the upper part of the channel protection film 5, and Cr of the diffusion prevention layer 7 and n''a-3i of the second amorphous semiconductor layer 6 are etched.

On top of that, a wiring metal layer 8 of aluminum (AI) is placed.
A film of about 1 μm is deposited by C magnetron sputtering, and a photoresist is applied thereon.

The wiring metal layer 8 is patterned and etched using a photolithography process and an etching process so as to open the upper central part of the channel protection film 5, thereby forming the shapes of the drain electrode 10 and the source electrode 9.

In this way, the high voltage thin film transistor of this example is manufactured.

Next, optimization of the channel region length L1 and offset region length L2 in a high voltage thin film transistor at a high voltage of 300 V to 500 V will be explained using FIGS. 2 to 5.

FIG. 2 is a diagram showing the L2 dependence of ON and OFF current values, when a voltage of 400 μ is applied between the source electrode 9 and the drain electrode 10 and the offset region length L2 is varied. When the voltage (Vg) of the gate electrode 2 is 20V, (7) the change in ON current (ION) is shown by the broken line at the top of Figure 2, and the OFF current when the voltage (Vg) of the gate electrode 2 is Ov. The change in (I OFF ) is shown by the dotted line at the bottom of FIG. In FIG. 2, the channel region length Ll-
17 μm, and channel width W-352 μm.

According to Fig. 2, the offset region length L2 is 20 to 30μ.
When the limit exceeds m, the ON current (ION)
decreases and when L2 becomes 20 μm or more, the OFF current (I OFF ) decreases and becomes constant, and L2 becomes 20 μm or more.
It can be seen that when the thickness is less than μm, the OFF current (I OFF ) increases. Therefore, the offset region length L2 is set to 20~
It is appropriate to set it to 30 μm.

FIG. 3 is a diagram showing the L1 dependence of the ON resistance value (Rt) of the transistor after stress. When the channel region length L1 is made variable, 400 V is applied between the source electrode 9 and the drain 10 of the high voltage thin film transistor. The figure shows the ON resistance value (Rt) of the transistor after stress is applied to the transistor by applying a voltage of 30 minutes to turn the transistor into an OFF state. In FIG. 3, the offset region length L2-25 μm and the channel width W-352 μm.

According to FIG. 3, when the channel region length L1 is increased, R
It can be seen that t decreases and becomes small and constant at 17 μm or more. Therefore, it is appropriate to set the channel region length L1 to 17 μm or more through a stress test, but in consideration of increasing the density of transistors, it is preferable that the channel region length L1 is as small as possible.

From the above explanation, the optimal value is that the channel region length L1 is 17μ.
m1 offset region length L2 is 25 μm, and considering the allowance, Ll is 14 to 20 μm5 L2 is 20 to 3
It becomes 0 μm.

Channel region length L1 is 17 μm1 Offset region length L2
Gate voltage (Vg) when optimized to 25μm
Figure 4 shows the drain current (Ids) characteristics, and Figure 5 shows the drain voltage (VdS) and drain current (Ids) characteristics when the gate voltage (Vg) is 6V, 10V, and 15V. It is.

It can be seen from FIGS. 4 and 5 that the high breakdown voltage thin film transistor with optimized device parameters exhibits good transistor characteristics.

In addition, the high voltage thin film transistor with this optimum value is
Even when operated at 500V, good transistor characteristics can be obtained.

Note that the configuration of the high voltage thin film transistor of this embodiment can also be applied to a "stagger type" transistor.

According to this embodiment, the channel region length L of a high voltage thin film transistor that is practically driven at a high voltage of 300V to 500V
1 is 14 to 20 μm, and offset region length L2 is 20 to 3
Since the channel region length L1 and offset region length L2 are optimized by setting them to 0 μm, it is possible to obtain good transistor characteristics in a high breakdown voltage situation, and the inverter's H
This has the effect of increasing the IGH/LOW ratio.

(Effects of the Invention) According to the present invention, the length of the region (channel region) from the end of the channel protective film on the source electrode side to the end of the gate electrode on the drain electrode side is set to 14 to 20 μm, and The length of the region (offset region) from the end of the channel protective film to the end of the gate electrode on the drain electrode side is set to 20 to 30 μm, resulting in a high voltage thin film transistor with optimized channel region length and offset region length. This has the effect that good transistor characteristics can be obtained and the HIGH/LOW ratio of the inverter can be increased.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional explanatory diagram of a high voltage thin film transistor according to an embodiment of the present invention, FIG. 2 is a diagram showing the L2 dependence of ON and OFF current values, and FIG. 3 is an ON resistance value of the transistor after stress. A diagram showing the L1 dependence of (Rt), Figure 4 is a diagram showing the gate voltage/drain current characteristics of a high voltage thin film transistor using optimized device parameter values, and Figure 5 is a diagram showing the optimized device FIG. 6 is a diagram showing the drain voltage/drain current characteristics of a high voltage thin film transistor using parameter values, and is an explanatory cross-sectional view of a conventional high voltage thin film transistor. 1...Substrate 2-...First gate electrode 3...Gate insulating film 4...First amorphous semiconductor layer 5...
Channel protective film 6... Second amorphous semiconductor layer 7...
・Diffusion prevention layer 8...Metal layer for wiring 9...Source electrode 10...Drain electrode

Claims (1)

[Claims] A gate electrode, a gate insulating film, a first amorphous semiconductor layer, and a channel protective film are formed on a substrate, and second electrodes serving as a source electrode and a drain electrode are formed with the channel protective film in between.
An amorphous semiconductor layer, a diffusion prevention layer, and a metal layer are formed, a region from an end of the channel protection film on the source electrode side to an end of the gate electrode on the drain electrode side is defined as a channel region, and a region on the drain electrode side is defined as a channel region. In a high voltage thin film transistor in which an offset region is a region from an end of the channel protective film to an end of the gate electrode on the drain electrode side, the channel region has a region length of 14 to 20 μm, and the offset region has a region length of 14 to 20 μm. A high voltage thin film transistor characterized by having a thickness of 20 to 30 μm.