JP2636843B2 - Image data expansion device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of recording and displaying image data represented by a two-dimensional distribution of pixels having an image component and pixels having no image component, the bit data corresponding to pixels constituting an image. The present invention relates to an image data expansion device that converts (extends) output bit data for a plurality of pixels in each of the vertical and horizontal directions.

2. Description of the Related Art For example, in facsimile communication, a sender scans a document with a scanner to obtain image data, encodes and compresses the image data, and transmits the image data. It reproduces and prints out an image based on this image data.

When the document is read by the scanner, when the image density is near the binarization threshold, the binarized data becomes black (1) or white (0). The notch (1 dot = 1 pixel) is protruded or dented. Such a notch causes disturbance in the figure of the reproduced image.

FIG. 5a shows an image obtained by reading the CCITT standard image No. 1 at 8 dots / mm at 8.5 times magnification. In this image, notches (projections and dents) are seen in both the main scanning direction (horizontal direction) and the sub-scanning direction (vertical direction). Correction of such protrusions and dents is desired.

On the other hand, in facsimile transmission and reception, copying, and image editing, image enlargement and density conversion are often performed.
For example, in a facsimile, in order to reduce the transmission / reception time, an original is read at 8 pixels / mm in the main scanning direction and 4 pixels / mm in the sub scanning direction, and the sub scanning direction is set to 8 pixels / mm on the receiving side.
The data is extended to mm, and recording is performed at 8 dots / mm in both the main scanning direction and the sub-scanning direction. In other image processing, for example, text editing or copying, in order to enlarge an image or to convert low-density pixel data (pixel division number per unit length is small) into high-density pixel data (pixel division number per unit length). To record or display.

In this type of enlargement or density conversion, if the original image data is expanded at the desired magnification as it is, stepwise irregularities in oblique lines become conspicuous, and in the expansion, a smoothing process of oblique lines on the image is performed. For example, if the image shown in FIG. 5a is magnified 2 × 2 as it is, the figure shown in FIG. 5b will be obtained, and the step-shaped uneven notch in the oblique line will be visually recognized greatly.

Therefore, it is sufficient to determine the notch from the original image data and delete it, but it is practically impossible to determine the notch 100% accurately. If the notch detection probability is increased, a non-notch is erroneously determined as a notch, and an image portion that is not a notch is erased.

It is an object of the present invention to provide an image data expansion device that suppresses a notch in image data expansion processing and improves image quality.

In order to achieve the above object, the present invention provides an image data expansion apparatus for converting original image bit data having a predetermined pixel density into output image bit data for a plurality of pixels in each of vertical and horizontal directions, comprising: The memory means, bit data corresponding to the pixel of interest to be converted on the original image, and bit data corresponding to each of at least eight pixels adjacent to the pixel of interest are used as reference patterns, and An image pattern data reading means for sequentially updating and sequentially reading, and detecting whether or not the target pixel is a notch pixel on the original image from the reference pattern. In the case of a notch pixel, the same bit data as the data is generated. Extended data generating means for generating bit data different from the pixel of interest and suppressing the notch in at least one of the columns and rows of the area, and generating the same bit data as the pixel of interest in the other pixels; Extended data memory means for storing the bit data generated by the data generating means.

According to this, the notch in the original image data is determined on the image plane having 9 or more pixels, and the bit data of the target pixel without the notch is extended to the same bit data as the bit data of the target pixel for a plurality of pixels in each of the vertical and horizontal directions. Is done.

When the pixel of interest is a notch, the bit data of the pixel of interest is bit data that suppresses the notch that is different from the pixel of interest in at least one of the columns and rows of a plurality of pixels in each of the vertical and horizontal directions. It is expanded to bit data of a plurality of pixels to which the same bit data as the pixel is addressed.

Since the number of the same bit data as the bit data of the notch is small, the notch is compressed and inconspicuous in the extended image data thus obtained. Most commonly, image data is expanded to several pixels for each pixel,
In the present invention, the notch detection is relatively accurate because the reference is also made to the adjacent pixel data surrounding each pixel data of the original image data to be expanded. Even if notch detection is an error, the original pixel data (black: image information is present) is not completely erased (white: no image information is present), so that normal image information is not erased.

A typical expansion of image data is to expand the dot data of one pixel into two pixels in the main scanning direction and two pixels in the sub-scanning direction (four times the number of dot data). That is, one pixel of the original image data is expanded to data of four pixels. In the quadruple expansion, in the present invention, the expansion of the notch is two pixels. The extension direction of the notch is set to an inconspicuous direction depending on whether the notch is oriented horizontally (main scanning direction) or vertically (sub scanning direction). That is, only one horizontal row or one vertical row of the 4 × 4 pixel area is the same as the notch bit data, and the other columns are bit data different from the notch bit data.

Also, it is preferable to suppress the notch as inconspicuously as possible, corresponding to the image information distribution around the notch,
In the preferred embodiment of the quadruple expansion of the present invention, notches are expanded (bit data of a notch pixel is expanded to the same bit data of two pixels) as shown in Table 1 below. In an image area that is not determined to be a notch, the set magnification is expanded (bit data of one pixel is expanded to the same bit data of four pixels).

Note) In Table 1 below, P is the pixel of interest to be expanded on the original image data and has image information (black: 1).

Q is a pixel of interest to be expanded on the original image data and has no image information (white: 0).

W is a pixel adjacent to the target pixel and has no image information (white: 0).

B is a pixel adjacent to the target pixel and has image information (black: 1).

? Is a pixel adjacent to the pixel of interest, regardless of whether it has image information (black: 1) or not (white: 1).

The left column of Table 1 is a reference pattern used to determine the presence or absence of a notch on the original image data. The reference pattern is composed of pixels a to i, and e is a pixel of interest to be subjected to the current extension processing. The right column is the notch extension pattern, and the number of pixels is 4
The image information (the same bit data) is extended to pixels j, k, m, and n, but is extended to two pixels.

According to this, according to the direction of the notch, the notch image data is expanded only in the direction in which it is most inconspicuous.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

FIG. 1a shows a first embodiment of the present invention. Referring to FIG. 1a, this apparatus is roughly divided into an image pattern generator 100, a reference pattern extracting circuit 200, an extended data generating circuit.
300, an output buffer memory 400 and a read / write control circuit 500. FIG. 2a shows a simplified block diagram of the data flow of this device.

2a, the pattern generator 100 is the image pattern generator 100 shown in FIG. 1a, the 3 × 3 register (matrix register) 200 is the reference pattern extraction circuit 200 shown in FIG. 1a, and the logic circuit 300 is 1a, buffer memory 400 corresponds to output buffer memory 400 shown in FIG. 1a, and controller 500 corresponds to read / write control circuit 500 shown in FIG. 1a. . That is, the 3 × 3 register 200 is output from the pattern generator 100.
The reference pattern data PPM is extracted according to the formula (1), and the operation of Table 1 is performed by the logic circuit 300, and the extended data EPM (FIG.
(Right column of the table) and temporarily store it in the buffer memory 400. The controller 500 controls the flow of data and these components, and outputs image pattern extension data from the buffer memory 400 to an output interface to a printer or the like as necessary.

Referring again to FIG. 1a, the read / write control circuit 500
In response to a character designation signal from an input device such as a keyboard (not shown) connected to a microprocessor (CPU) 18, a host processor of a base unit, or a text memory,
In the original mode, the image pattern original data is expanded in the horizontal double mode, the image pattern expanded data is expanded twice in the horizontal direction, and in the vertical double mode, the image pattern original data is expanded in the vertical direction twice. In the full-width mode, the image pattern expanded data obtained by expanding the original image pattern data in both the vertical and horizontal directions is output to an output device such as a CRT display unit (not shown), a dot printer, a bit memory (page memory), a facsimile, a computer, or the like. Output to the information processing device.

The image pattern generator 100 has the required number of characters.
Stores 24 × 24 bit image pattern original data per character. In fact, this image pattern generator 10
Although each image pattern original data stored in 0 has a linear form, here, for convenience of explanation, the image pattern original data (ODP) is a bit data of 24 × 24 bits as shown in FIG. 1i. Are arranged two-dimensionally, and the
As shown in the figure, one line (horizontal arrangement) 3-byte data
Assume that it is stored in 24 lines. Therefore, in the following, the image pattern original data corresponding to the designated character
Any byte any line of ODP is called the first Iθ byte, if for example the second byte of the third line, is referred to as a third _two bytes. In addition, each image pattern original data OD
P is designated by a character address from the CPU 18 of the read / write control circuit 500, and each line of the designated image pattern original data ODP is designated by a line address from the CPU 18.

Reading is performed for each line specified by the line address, and the read data (line data) is read.
Is supplied to the data selector 15 of the reference pattern extraction circuit 200.

The data selector 15 immediately transfers the received line data to the multiplexer 16 of the extended data generating circuit 300 in the original mode, but in other modes (horizontal double mode, vertical double mode or full double mode), the line data is received. The data is transferred to a parallel-in / serial-out shift register (hereinafter, referred to as a P / S register) 2. This P / S
Register 2 are each 8-bit P / S register 2 _1, made of a 2 ₂ and 2 ₃ of the series connection, and has a P / S register a total of 24 bits (3 bytes).

Data selector 15, depending on the specification of CPU 18, double-width, when the double-height or full combination angle mode is set, the first byte of the received line data to 2 _1, the second byte in the 2 _2, the third byte 2 ₃ distributes respectively.

The line data stored in the P / S register 2 is stored as serial 24-bit data in the shift register 5 in the next stage.
Is forwarded to

The shift register 5 includes a shift register of 8 bits from the head 5 _1, and also a 8-bit shift register 5 _2, and 9-bit shift register 5 ₃ Series total of 25 bits of the shift register by connecting, as described below 1 in
After data input for the line is completed, dummy data (white data: 0) is input to the 25th bit. Register 5, at least the top of the register 5 first bit of _1, the serial-in / parallel-out shift register the second bit and the third bit can be output in parallel (hereinafter, referred to as S / P register)
It has become. The shift register 4 and the shift register 3 have exactly the same configuration as the shift register 5, and these shift registers 3, 4, and 5 are connected in series to form a 25 × 3 bit shift register as a whole. Are synchronously activated with the register 2. Therefore, the bit data of the same bit number stored in each of the shift registers 3, 4, and 5 is shifted by one line, and the bit data stored in the shift register 4 is stored in the shift register 3. The data is read out one line after the bit data that is present. That is, the above-described 3 × 3 matrix register can be configured by the S / P registers of the shift registers 3, 4, and 5 that output the first bit, the second bit, and the third bit, respectively, in parallel.

This will be described in detail with reference to FIG. 1g.
Bit data (target data) e corresponding to the target pixel e is stored in the second bit of the shift register 4 (4 ₁ ).
The bit includes bit data d corresponding to the pixel on the left of the pixel of interest e.
However, in the third bit, bit data f corresponding to the pixel on the right of the target pixel e is stored.

Since each bit data stored in shift register 3 has exactly one line before the data of each bit data stored in the shift register 4, respectively, the first bit of the shift register 3 (3 ₁₎ Shows bit data a corresponding to the upper left pixel of the pixel of interest e, and bit data b corresponding to the pixel immediately above the pixel of interest e in its second bit.
However, bit data c corresponding to the upper right pixel of the target pixel e is stored in the third bit.

Since each bit data stored in the shift register 5 is exactly one line later than each bit data stored in the shift register 4, the first bit of the shift register 5 (5 ₁ ) Has bit data g corresponding to the lower left pixel of the pixel of interest e, its second bit has bit data h corresponding to the pixel immediately below the pixel of interest e,
In the third bit, bit data i corresponding to the lower right pixel of the target pixel e is stored.

Therefore, the reference pattern data PPM two-dimensionally arranged as shown in FIG. 1h is extracted. The reference pattern data PPM is provided to the information distribution pattern detection circuit 6 of the extension data generation circuit 300.

FIG. 1b shows the configuration of the information distribution pattern detection circuit 6.
The detection circuit 6 includes AND gates AN1 to AN13 for determining whether each of (1) to (13) in Table 1 is satisfied, a circuit 61 for performing oblique line smoothing at the time of data expansion, OR gates OR1 to OR10, and AND gates AN14 to AN14. It consists of AN17 and delay circuit DLY.

When each of (1) to (13) in Table 1 is satisfied, each of the AND gates AN1 to AN13 outputs “1”, and the OR gates OR1 to OR4 output the extended data j,
Output k, m and n. Isolated point (No. 9 in Table 1)
Column) is detected by the AND gate AN9, the output "1" of the AN9 is inverted to "0" by the inverter IN1 and applied to the AND gates AN14 to AN17, whereby the extended data j, k,
m and n are all set to “0 (white). The oblique line smoothing circuit 61 is an image data expansion smoothing circuit disclosed in Japanese Patent Application No. 61-28647 filed by the present applicant. In the case of image information distributions other than (1) to (13) shown in Table 1, corresponding extended data (j, k, m, n) of 2 × 2 pixels per target pixel are generated, and Thus, OR gates OR5 to OR8 provide OR gates OR5 to OR8 with a notch of the original image data of 2 pixels (Table 1), a pixel of the other portion at 4 pixels, and a stepped unevenness of the hatched portion at 1 pixel. Outputs the extended data j, k, m, n smoothed in a stepwise unit.

The delay circuit DLY is a D-flip-flop array, and is activated in synchronization with the shift registers 2, 3, 4, and 5. Accordingly, the DLY output is the pixel d of the immediately preceding target data (that is, the pixel d to the left of the target pixel e in the original image pattern).
(Corresponding) extension data.

In this manner, the information distribution pattern detection circuit 6
The first bit is determined by each bit data of the reference pattern data PPM.
The notch extension data in the table is calculated to generate extension data j, k, m, and n of the immediately preceding target data (that is, corresponding to the pixel on the left of the target pixel in the original image pattern).

Referring back to FIG. 1a. Information distribution pattern detection circuit 6
, Ie, the extended data j, k, m and n are 4-bit parallel data, but the bit data j is 4-bit
S / P register (serial-in / parallel-out shift register) 7 and 8-bit S / P register 11, bit data k to 4-bit S / P register 8, bit data m to 4-bit S / P registers 9 and 8 Bit S / P register 12
And the bit data n are applied to a 4-bit S / P register 10, respectively. S / P registers 7, 8, 9, 10, 11, and 12
Are shifted by the same shift pulse, and are shifted one bit to the left for each parallel output of the extension data j, k, m, n.

In S / P register 7 and 8, the first bit of the register 7: (bit data stored and j ₁ are synonymous less) output first bit input latch 13, register 8
The first bit (k ₁ ) output of the register 13 is input to the second bit input of the latch 13, the second bit (j ₂ ) output of the register 7 is input to the third bit input of the latch 13, and the second bit (k ₂ ) of the register 8 The output is alternately connected to the fourth bit input of the latch 13,... That is,
Each time the expansion of the original data for four pixels is completed, the latch 13 expands the first data (data corresponding to the pixel four before the pixel of interest at that time: data corresponding to the fourth pixel on the left side). Upper left data, upper right data, and third data (similar data for the previous two pixels) obtained by expanding the upper left data, upper right data, and the second data (the same for the previous three pixels) The upper left data, the upper right data, and the fourth data (the data corresponding to the immediately preceding pixel: the data corresponding to the left neighboring pixel) are also extended with the upper left data and the upper right data. , The data of the upper line of the extended data can be synthesized.

In the S / P registers 9 and 10, the first bit (m ₁ ) output of the register 9 is input to the first bit input of the latch 14, and the first bit (n ₁ ) output of the register 10 is input to the second bit input of the latch 14. And the second bit (m ₂ ) output of register 9 is latched.
The second bit (n ₂ ) of register 10 is input to the third bit input of 14
The output is alternately connected to the fourth bit input of the latch 14,..., And so on. That is, each time the expansion of the original data for four pixels is completed, the latch 14 expands the lower left data, lower right data, 2
Lower left data and lower right data obtained by expanding the third data (the data corresponding to the three pixels before the same), lower left data and lower right data obtained by expanding the third data (the data corresponding to the two pixels before the same) , The fourth data (similarly, the data for the immediately preceding pixel: data for the pixel on the left) is lined up with lower left data and lower right data. Can be synthesized.

Therefore, the latches 13 and 14 are connected to the S / P registers 7, 8, 9
And 10 are latched every time the extended data obtained by processing 4 bits (4 pixels of interest) are input,
The upper line data (contents of 13) and the lower line data (contents of 14) of the synthesized extended data (4 pixels of interest × 4 pixels: 16 bits) are output to the multiplexer 16.

The S / P registers 11 and 12 store 8 bits (the target pixel 8
Extended data (j _{1 to} j ₈ , m ₁ to
Each time m ₈ ) is input, the data of the upper line (contents of 11) and the data of the lower line (contents of 12) are output to the multiplexer 16 as parallel data.

The multiplexer 16 selects the original line data of the image pattern original data ODP from the data selector 15 in the original mode, and selects the upper line data of the extended data from the latch 13 in the double-width mode, in accordance with an instruction from the CPU 18. Then, in the vertical double mode, the parallel data of the S / P registers 11 and 12 are selected, and in the full double mode, the data of the upper and lower lines of the extended data from the latches 13 and 14 are selected.

The output buffer memory 400 is composed of four 24 × 24 bit buffer memories I, II, III, and IV (areas), and is not activated in the original mode, but is expanded from the latch 13 selected by the multiplexer 16 in the double-width mode. The data on the upper line of the data is sequentially stored in buffers I and II to create extended double-width image pattern data. In the double-long mode, the parallel data from the S / P register 11 selected by the multiplexer 16 is transferred to the odd-numbered line. And S /
Parallel data from P register 12 is transferred to even-numbered lines,
And alternately store the data in the buffers I and III to create extended double-width image pattern data. In the full-width mode, data of the upper line of the extended data from the latch 13 selected by the multiplexer 16 is stored in odd-numbered lines and latched. 14
Is stored in the buffers I, II, III, and IV alternately in the even-numbered lines, to create full-width image pattern extended data. That is, the extension data is two-dimensionally arranged in the output buffer memory 400 to create the image pattern extension data.

In the following, for convenience of description, the write area of the buffer memory 400 is specified for each byte by a line number and a write byte address, similarly to the ODP shown in FIG. 1j.

The CPU 18 of the read / write control circuit 500 controls each unit as described in the above brief description, and creates extended image pattern data from the original image pattern data ODP corresponding to the designated character. The system controller 19 is a decoder for transferring a read command, a data select command, a write command, a shift command, and the like to the components of the CPU 18, and illustration of signal lines is omitted. The pulse generator 20 generates a shift pulse, and applies the shift pulse intermittently to each of the above-mentioned registers in accordance with a shift command of the CPU via the system controller 19, but illustration of this signal line is also omitted.

The counter 1 (21) is a 25-ary counter that counts shift pulses applied to the shift registers 3, 4, and 5. The counter 2 (22) is an octal counter that counts the shift pulses applied to the S / P registers 7, 8, 9, 10, 11, and 12, and can also output a signal every 4 counts. Also serves as.

Hereinafter, the control executed by the CPU 18 will be described in detail with reference to the flowcharts shown in FIGS. 1c, 1d, 1e, and 1f. The following description is a subroutine executed after a character is designated by an input device (host processor: not shown).

In S1 (first step, S is omitted in the flowchart: the same applies hereinafter), each register, counter, register, and the like are cleared (reset), and in S2, the character address corresponding to the designated character is stored in the image pattern generator 100. Set to.

If the mode is the original mode, the process proceeds from S3 to S4, where the image pattern original data ODP is read out as usual and transferred to the output device side.

In the modes other than the original mode (vertical double width mode, horizontal double width mode, full double width mode), the process proceeds to S5, where the parameter I corresponding to the line address is set to 0, and the parameter K corresponding to the number of times of writing to the output buffer memory is set.
To 0 and the number of write lines (output buffer memory
The parameter L corresponding to 400 write line numbers) is set to 1.

The counter 21 is cleared (0) at S6 and the parameter I is set at S7.
Is incremented by one (I: 0 → 1).

Since the value of I is 1 (I <25), the process proceeds from S8 to S9, where the parameter θ indicating the byte number of the line (designated line) to be read is set to 1, and the image pattern generator 100 and the data selector are set in S10. 15 to the _first byte of the image pattern original data ODP in the P / S register 2
Stored in 2 ₁ Thereafter, the process proceeds from S11 to S12, and stores the first _two bytes of the ODP 2 ₂ back to S10 by 1 up to theta, storing the first _three bytes of the ODP to 2 ₃ by the same loop.

When the writing of the first line of the ODP to the P / S register 2 is completed, the value of the parameter θ is 3, and the process exits this loop from S11. However, the value of I is still 1 (I <2). Proceed to S14.

S14 is a step in which the P / S register 2 and the shift registers 3, 4, and 5 are synchronously energized to count up the counter 21, and a loop consisting of S14-S15-S14-, ...,-S15 Is repeatedly executed until the value of the counter 21 becomes 25. In this loop, when the value of the counter 21 becomes 24, all the data of the first line of the ODP written in the P / S register 2 is transferred to the shift register 5 (2nd to 25th bits). Is executed, the data of the first line of the ODP is stored in the first bit to the 24th bit of the shift register 5, and the dummy data (0: white pixel) is stored in the 25th bit. During this time, the information distribution pattern detection circuit 6 sequentially outputs attention to the dummy data (“0”) when cleared in S1, and outputs the extended data.
Since the S / P registers 7 to 12 and below are not activated, they are irrelevant to the generation of the image pattern extension data.

Returning from S15 to S6, the counter 21 is cleared and the parameter I is incremented by one in S7. As a result, the value of I becomes 2, but since I <25, the parameter θ is again set in S9.
Is set to 1 and the second line of the ODP is written to the P / S register 2 in the same manner as described above in the loop of S10-S11-S12-.

Since I = 2, S14−S15−S14−,.
…, −S15 loop, this time shift register 5
The data of the first line of the ODP stored in the PDP is stored in the shift register 4 and the second line of the ODP stored in the P / S register 2 is stored in the shift register 4.
Line data is sequentially transferred to the shift register 5.

In this loop, when the value of the counter 21 becomes 24,
The second bit to the 25th bit of the shift register 4 have the data of the first line of the ODP, the first bit of the shift register 5 has the dummy data of the first line, and the second bit of the shift register 5 has the second bit.
The data of the second line of the ODP is stored in the bit to the 25th bit, respectively. That is, in the first loop of the ODP, when the value of the counter 21 becomes 24 in this loop, the data of the first line of the ODP is stored in the second bit to the 25th bit of the shift register 4 in the first bit of the shift register 5. , The dummy data of the first line is stored, and the data of the second line of the ODP are stored in the second to 25th bits of the shift register 5, respectively. That is, the data (1 ₁ ) of the first bit of the first line of the ODP is the target data. At this time, since the first bit to the 25th bit of the shift register 3 and the second bit of the shift register 4 store the dummy data (“0”) when cleared in S1, the reference pattern data PPM Is as shown in FIG. 1k. From this, it can be seen that the dummy data corresponds to a background pixel outside the original image pattern (white pixel; therefore, the following dummy data are all “0”).

Extension data (j obtained by focusing on the bit data 1 ₁ ODP,
k, m, n) are input to the delay circuit DLY (see FIG. 1b).

Thereafter, S14 is further executed to execute shift registers 2-5.
Is shifted by 1 bit, the data of the first line of the ODP is shifted to the first to 24th bits of the shift register 4, the dummy data of the first line is shifted to the 25th bit, and the data of the second line of the ODP is shifted. First bit of register 5
To a 24-bit dummy data of the second line to the 25th bit, (becomes 1 _second target data) to be stored respectively.

Return to S6, clear (0) the counter 21, and set I to 1 in S7.
Increment (2 → 3), set θ to 1 in S9,
In a loop consisting of S10-S11-S12-,..., -S12, the data of the third line of the ODP is written to the P / S register 2 as described above.

This time, since the value of the parameter I is 3, S1
Proceed from 3 to S16. After setting the value of the write byte address φ of the output buffer memory 400 to the value 1 indicating the start address in S16, the counter 22 is cleared (0) in S17 (FIG. 1c).

Attention data at this time is 1 ₂ (ODP first line the first bit data), information distribution pattern detection circuit 6, the extended data obtained by correcting the extension data when focusing on the bit data 1 ₁ (one before the data: j, k, m, n : hereinafter, since it outputs a will be referred to as "bit data 1 ₁ of extension data"), the S / P register 7-12 in S18 1
Take in the extended data of the bit data 1 ₁ urges bit synchronization. Here, the counter 22 is incremented by one.
Its value will be 1.

S19 is the same step to S14 described above, when doing this, attention data becomes 1 _3, 25th third line the first bit data of the ODP bit (3 ₁₎ of the shift register 5
Is written. Here, the counter 21 counts up by one, and its value becomes 1.

 The double height mode will be described later.

 Since the value of the counter 22 is 1, the process returns from S21 to S18.

In S18, the information distribution pattern detecting circuit 6 the S / P register 7 to 12 urges one bit synchronization is outputting captures extension data of bit data 1 _2. The value of the counter 22 becomes 2.

When you run S19, attention data becomes 1 _4, third line second bit data of the ODP to a 25-bit shift register 5 (3 ₂₎ is written. The value of the counter 21 becomes 2.

Returning S21 to the S18, the information distribution pattern detecting circuit 6 the S / P register 7 to 12 urges one bit synchronization is outputting captures extension data of bit data 1 _3. counter
The value of 22 becomes 3.

When you run S19, attention data becomes 1 _5, third line third bit data of the ODP to a 25-bit shift register 5 (3 ₃₎ is written. The value of the counter 21 becomes 3.

Returning S21 to the S18, the information distribution pattern detecting circuit 6 the S / P register 7 to 12 urges one bit synchronization is outputting captures extension data of bit data 1 _4. Thus, the upper extension data is aligned to an extension of the bit data 1 ₁ to 1 ₄ in the latch 13, the lower side of the extension data extended bit data 1 ₁ to 1 ₄ are aligned in the latch 14 (7 & 8 and 13, 9 & 10 and
14 connections as described above). Here counter 22
Is incremented by 1 so that the value is 4.

When you run S19, attention data becomes 1 _6, the third line the fourth bit data of the ODP to a 25-bit shift register 5 (3 ₄₎ are written. The value of the counter 21 becomes 4.

Since the value of the counter 22 has become 4, the process proceeds from S21 to S22. Since extension data in the latch 13 and the latch 14 extends the bit data 1 ₁ to 1 ₄ are aligned to latch biasing them in S22.

In the full double mode, in S24, the upper 8-bit parallel data of the extended data from the latch 13 is transferred to the first line of the output buffer memory 400 [the (2L-1) th line: L
= 1] in the first byte (φ = 1) and the lower 8-bit parallel data from the latch 14 is written to the first byte (second L line: L = 1) of the output buffer memory 400. Write to φ = 1).

In the case of the double-width mode, in S25, the upper 8-bit parallel data of the extended data from the latch 13 is transferred to the first byte (φ = 1) of the first line (L line: L = 1) of the output buffer memory 400. Write to.

Since the write byte φ is incremented by one in S24 or S25, the value becomes 2.

In S26, when the value of the parameter K indicating the number of times of writing to the output buffer memory 400 is increased by 1, the value becomes 1, and the process returns from S27 to S17.

The above-mentioned repetition will continue for a while, but the data fetching and writing are complicated, so that they will be briefly described.

Clears counter 22 in S17 and S18-S19-S20-S21-
...-Loop of S21.

The extension data of a bit data 1 ₅ 7-10, register 5
Incorporate 3 ₅ to a 25-bit. The data of interest is ₁₇ , the counter 21 is 5, and the counter 22 is 1.

The extended data of bit data ₁₆ is stored in register 5
Incorporate 3 ₆ 25 bits. The target data is ₁₈ , the counter 21 is 6, and the counter 22 is 2.

The extended data of bit data ₁₇ is stored in 7 to 10 in register 5
It incorporates 3 ₇ to the 25-bit. The target data is ₁₉ , the counter 21 is 7, and the counter 22 is 3.

The extended data of bit data ₁₈ is stored in register 5
Incorporate 3 ₈ to a 25-bit. The target data is 1 ₁₀ , the counter 21 is 8, and the counter 22 is 4.

S18-S19-S20-S21 -...-Exits the loop of S21.

In the full-width mode, the upper extension data of the bit data ₁₅ to ₁₈ is written to the second byte of the first line of the output buffer memory 400, and the lower extension data is written to the second byte of the second line.

In the double-width mode, the upper extension data of the bit data ₁₅ to ₁₈ is written to the second byte of the first line of the output buffer memory 400.

The write byte address φ becomes 3, and the parameter K becomes 2.

Clear counter 22 and S18-S19-S20-S21 -...
-It becomes a loop of -S21.

The extended data of bit data ₁₉ is stored in registers 5 to 7.
It incorporates 3 ₉ to the 25-bit. The target data is 1 ₁₁ , the counter 21 is 9 and the counter 22 is 1.

The extension data of a bit data 1 ₁₀ 7-10, incorporate 3 ₁₀ to a 25-bit register 5. The target data is 1 ₁₂ , the counter 21 is 10, and the counter 22 is 2.

7-10 extension data of bit data 1 ₁₁ captures the 3 ₁₁ to a 25-bit register 5. The target data is 1 ₁₃ , the counter 21 is 11, and the counter 22 is 3.

The extended data of the bit data 1 _{12 is} loaded into 7 to 10 and 3 ₁₂ is loaded into the 25th bit of the register 5. The target data is 1 ₁₄ , the counter 21 is 12, and the counter 22 is 4.

S18-S19-S20-S21 -...-Exits the loop of S21.

In full double angle mode, writes the upper extension data of bit data 1 _{9-1 12} to the first line third byte of the output buffer memory 400, and writes the lower extension data to the second line a third byte.

The double-width mode, the upper extension data of bit data 1 _{9-1 12,} written in the first line third byte of the output buffer memory 400.

The write byte address φ becomes 4 and the parameter K becomes 3.

Clear counter 22 and S18-S19-S20-S21 -...
-It becomes a loop of -S21.

The extension data of a bit data 1 ₁₃ 7-10, incorporate 3 ₁₃ to a 25-bit register 5. The target data is 1 ₁₅ , the counter 21 is 13, and the counter 22 is 1.

The extension data of a bit data 1 ₁₄ 7-10, incorporate 3 ₁₄ to a 25-bit register 5. The target data is 1 ₁₆ , the counter 21 is 14, and the counter 22 is 2.

The extension data of a bit data 1 ₁₅ 7-10, incorporate 3 ₁₅ to a 25-bit register 5. The target data is 1 ₁₇ , the counter 21 is 15, and the counter 22 is 3.

The extension data of a bit data 1 ₁₆ 7-10, incorporate 3 ₁₆ to a 25-bit register 5. The attention data is 1 ₁₈ , the counter 21 is 16, and the counter 22 is 4.

S18-S19-S20-S21 -...-Exits the loop of S21.

In all double angle mode writes an upper extension data of bit data 1 _{13-1 16} to the first line the fourth byte of the output buffer memory 400, and writes the lower extension data in the second line the fourth byte.

The double-width mode upper extension data of bit data 1 _{13-1 16,} written in the first line the fourth byte of the output buffer memory 400.

The write byte address φ becomes 5, and the parameter K becomes 4.

Clear counter 22 and S18-S19-S20-S21 -...
-It becomes a loop of -S21.

The extension data of a bit data 1 ₁₇ 7-10, incorporate 3 ₁₇ to a 25-bit register 5. The target data is 1 ₁₉ , the counter 21 is 17, and the counter 22 is 1.

The extension data of a bit data 1 ₁₈ 7-10, incorporate 3 ₁₈ to a 25-bit register 5. The target data is 1 ₂₀ , the counter 21 is 18, and the counter 22 is 2.

7-10 extension data of bit data 1 ₁₉ captures the 3 ₁₉ to a 25-bit register 5. The data of interest is ₁₂₁ , the counter 21 is 19, and the counter 22 is 3.

The extension data of a bit data 1 ₂₀ 7-10, incorporate 3 ₂₀ to a 25-bit register 5. The data of interest is ₁₂₂ , the counter 21 is 20, and the counter 22 is 4.

S18-S19-S20-S21 -...-Exits the loop of S21.

In all double angle mode writes an upper extension data of bit data 1 ₁₆ to 1 ₂₀ to the first line fifth byte of the output buffer memory 400, and writes the lower extension data to the second line fifth byte.

The double-width mode upper extension data of bit data 1 ₁₆ to 1 _20, written in the first line fifth byte of the output buffer memory 400.

The write byte address φ becomes 6, and the parameter K becomes 5.

Clear counter 22 and S18-S19-S20-S21 -...
-It becomes a loop of -S21.

The extension data of a bit data 1 ₂₁ 7-10, incorporate 3 ₂₁ to a 25-bit register 5. The data of interest is ₁₂₃ , the counter 21 is 21, and the counter 22 is 1.

The extension data of a bit data 1 ₂₂ 7-10, incorporate 3 ₂₂ to the 25 bits of the register 5. The data of interest is 1 ₂₄ , the counter 21 is 22, and the counter 22 is 2.

The reference pattern data PPM when the data of interest is 1 ₂₄ (that is, the right corner pixel of the original image pattern is the pixel of interest) is the first
l Shown in the figure. In this case, the bit data a, b and c are S1
, F is the dummy data of the first line, and i is the dummy data of the second line.

The extension data of a bit data 1 ₂₃ 7-10, incorporate 3 ₂₃ to the 25 bits of the register 5. The target data is dummy data of the first line, the counter 21 is 23, and the counter 22 is 3
become.

Capturing extension data of bit data 1 ₂₄ 7-10.
In this case, extension data of the bit data 1 ₂₄ is thus undergoing correction by the dummy data of the first line as described above, since the dummy data is "0", in fact, the influence of the dummy data No (no amendment).

Incorporate 3 ₂₄ to a 25-bit register 5. Attention data 2 _1, counter 21 is 24, the counter 22 is four.

In the case of attention data is 2 ₁ reference pattern data PPM
Is shown in FIG. 1m. In this case, the bit data a is dummy data by initialization in S1, b is dummy data on the first line, and g is dummy data on the second line.

S18-S19-S20-S21 -...-Exits the loop of S21.

In all double angle mode writes an upper extension data of bit data 1 _{21-1 24} to the first line sixth byte of the output buffer memory 400, and writes the lower extension data to the second line sixth byte.

The double-width mode upper extension data of bit data 1 _{21-1 24,} written in the first line sixth byte of the output buffer memory 400.

The write byte address φ becomes 7, and the parameter K becomes 6.

Since the value of the parameter K has become 6, the process goes through the loop from S17 to S27 and proceeds to S28 in FIG. 1f.

At this point, attention data is a 2 _1, information distribution pattern is the detection circuit 6 outputs the extended data of the dummy data in the first line, which registers 7 This extended data is meaningless In step S28, the registers 2 to 5 are synchronously shifted by one bit without being taken into. Thus, the dummy data of the third line is written to a 25-bit register 5, the attention data becomes 2 _2.

In S29, the value of the parameter K is set to 0, and in S30, the parameter L is incremented by one. As a result, the value of L becomes 2, and the process returns from S31 to S6.

In step S7, parameter I is incremented by 1 and its value is set to 4
Then, the process proceeds to S8 and S9, and the fourth line of the ODP is written to the P / S register 2 in the loop of S10-S11-S12 -...- S11.

After that, the process proceeds to S13, S16, and S17.
Capturing extension data of bit data 2 _1.

Below, in the same manner as described above, the sequential bit data 2 _{2-2
Twenty-four} extended data are created and written to the third and fourth lines of the output buffer memory 400 in the full double mode, and to the second line in the horizontal double mode (L = 2).

Although the 1n drawing shows the reference pattern data PPM to note bit data 2 _24, c is the dummy data of the first line, f is the dummy data in the second line, i is the dummy data of the first line.

The above processing is repeated, and when the value of the parameter I becomes 25 in S7, the process directly proceeds from S8 to S16. That is, since no data is written to the P / S register 2, the contents are all 0s. In this case, attention data is 23 _2, the value of the parameter L has become 23.

Thereafter, the data 23 ₁ to 23 ₂₄ in the loop of the above S17~S27
Is written to the 45th and 46th lines of the output buffer memory 400 in the full double mode and to the 23rd line in the horizontal double mode (L = 23). During this time, the dummy data is sequentially written to the register 5 as the data of the 25th line. Therefore, the data
24 When ₁ becomes the target data (Counter 21 = 24, Counter
22 = 4), as shown in FIG. 1p, a is dummy data on the 22nd line, d is dummy data on the 23rd line, g is dummy data on the 24th line, and h and i are data on the 25th line. It becomes the written dummy data.

Next, when it comes to S7, the value of I becomes 26, and directly from S8 to S16
Proceed to. Attention data at this time is 24 _2, the value of the parameter L has a 24.

Thereafter, in the loop of S17 to S27, data 24 _{1 to} 25 ₂₄
Is written to the 47th and 48th lines of the output buffer memory 400 in the full double mode and to the 24th line in the horizontal double mode (L = 24). During this time, the dummy data is sequentially written to the register 5 as the data of the 26th line. Therefore, the data
When the 24 ₂₄ is a target data (counter 21 = 22, the counter 22 = 2), as shown in 1q view, c is dummy data of the 23 lines, f is the dummy data of the 24 lines, g is 25 Dummy data, h and i, written as line data
Becomes dummy data written as data on the 26th line.

When the writing of the extension data up to 24 _{24 into} the memory 400 is completed and the process proceeds to S26-S27-S28-S29-S30, the value of the parameter L becomes 25, so the process proceeds from S31 to S32.

In the full double mode, the areas I to I of the output buffer memory 400 are
Since the image pattern extension data is stored in V, the image pattern extension data is transferred to the output device (S33). In the double-width mode, the image pattern extension data is stored in the areas I and II of the output buffer memory 400. Transfer (S33),
The process returns to the main routine (not shown).

Next, the vertical double mode will be described. Since there is no horizontal expansion in the double-height mode, ODP data of 8 bits is required in order for the S / P registers 11 and 12 to have expanded data. In other words, instead of S21 described above with S35 (FIG. 1e), a loop of S18-S19-S20-S35-S18 -...- S35 is formed, and every time the value of the counter 22 becomes 8, The contents (upper side) of the register 11 are stored in the second (2
L-1) Write the contents (lower side) of the register 12 to the φ-th byte of the line and to the φ-th byte of the second L line of the output buffer memory 400, respectively.

One line of the ODP is 24 bits, and writing to the memory 400 is performed for every 8 bits of the ODP data. When the parameter K becomes 3, the double doubling process for one line is completed, and S38 to S39-S40-S41- Proceed to S42.

For S39, S40, S41 and S42, the above-mentioned S28, S29, S3
It is completely synonymous with 0 and S31, and the description is omitted here.

In the double height mode, since the image pattern extension data is stored in the areas I and III of the output buffer memory 400, it is transferred to the output device (S43), and the process returns to the main routine (not shown).

The above is the data extension processing operation of the image pattern data extension device shown in FIG. 1a.

FIG. 6 is an enlarged image pattern (full-size mode: quadruple in area) of FIG. 5a by this device. In other words, the image pattern representing the graphic in FIG. 5a is printed using extended data obtained by performing an extension process in the full-size mode. The oblique line becomes very smooth, and there is no deterioration in image resolution due to generation of unnecessary dots at the intersection of the vertical line and the horizontal line. This is disclosed in detail in Japanese Patent Application No. 61-28647,
This is based on the extended grain by the oblique line smoothing circuit 61 shown in FIG. 1b. The vertical and horizontal notches of the figure in FIG. 5a are suppressed and the figure is smooth at the notch part based on the expansion processing by the AND gate or the like in FIG. 1b which performs the expansion processing of Table 1. .

In the above-described first embodiment, the character pattern in the pattern memory 100 is enlarged by a full width (4 times in area) and a horizontal width (2 times in area).
In this case, the pattern memory 100 is used for data expansion on the facsimile receiving side. The data is changed to a memory, and the data read from the output buffer memory 400 is stored in a print data buffer memory (line buffer memory). 4 dots in the sub scanning direction
/ mm data is expanded to 8 dots / mm in the sub-scanning direction, and data is sent in the main scanning direction at 8 dots / mm, and the data is not expanded on the receiving side. Will be.

By the way, the first embodiment (the outline is shown in FIG. 2a,
In FIG. 1a), the information distribution pattern detection circuit 6 is constituted by a logic circuit, but may be a ROM table as shown in FIG. 2b. In this case, the extension data EPM is read with the bit data a to i as 9-bit addresses.

Next, a second embodiment of the present invention will be described. In the second embodiment, the reference pattern extracting circuit of the first embodiment (FIG. 1a) is used.
200, the extended data generation circuit 300, the output buffer memory 400, and the read / write control circuit 500 are replaced with one microcomputer or personal computer. That is, as shown in FIG.
A computer 31 is connected between 30 and the output device 32. In this case, the image pattern generator 30 is a pattern memory that stores 24 × 24 bit image pattern original data for a predetermined number of characters as shown in FIG. FIG. 4 shows a program (BASIC language) executed by the computer 31 in this case. Note that various computers such as a microcomputer, a personal computer, and a minicomputer can be used as the computer 31, but the description will be continued below assuming that the microcomputer is used.

Next, the preconditions of the program shown in FIG. 6 and the arithmetic processing by its execution will be described.

First: In this process, a black pixel is indicated by “0” and a white pixel is indicated by “1”. That is, the case where the output device 32 is a CRT display unit is targeted.

Second: The image pattern original data in this processing is read from the image pattern generator 30 in correspondence with the designated character, and its 0th line, 25th line, 0th column, and 25th line
After the process of adding column dummy data, that is, the process of adding 1-bit dummy data edges around the original image pattern data ODP in FIG. 1i, the data stored in the RAM in the microcomputer 31 And

Third Each bit data of the image pattern original data stored in the RAM is represented by A (,). In this regard, see FIG. 2c. FIG. 2c shows the same reference pattern data PPM shown in FIG. 1h, but the hatched portion is the data of interest (e). If this attention data is A (I, J), (I = 1, 2, 3,..., 23, 24; J = 1, 2, 3,.
24), the upper left corresponding data of the target pixel is A (I−1, J−1), the corresponding data directly above the target pixel is A (I−1, J), and the upper right corresponding data of the target pixel is A (I−1). , J + 1), the corresponding data to the left of the pixel of interest is A (I, J−1), the data to the right of the pixel of interest is A (I, J + 1), and the corresponding data to the lower left of the pixel of interest is A (I + 1, J−1). ), The corresponding data immediately below the target pixel is A (I + 1, J), and the corresponding data at the lower right of the target pixel is A (I + 1, J + 1).

FIG. 4: The program shown in FIG. 4 shows a process for creating image pattern extended data obtained by expanding the image pattern original data by two times vertically and horizontally (corresponding to the above-described full-width mode), and outputs the image pattern extended data to an output device. The control to be transferred is not specifically shown.

Fifth: The created image pattern extension data is stored in the RAM (corresponding to the above-described writing to the output buffer memory 400).

6th: Each bit data of the image pattern extension data is B
(,). That is, attention data A
In the extended data obtained by converting (I, J), the upper left bit data (data j in FIG. 1h) is B (I2, J2), and the upper right bit data (data k in FIG. 1h) is B (I2 , J2 + 1), the lower left bit data (data m in FIG. 1h) is B (I2 + 1, J2),
The lower right bit data (data n in FIG. 1h) is represented by B (I2 + 1,
J2 + 1) (no delay). The upper left data (j mentioned above) of the extended data of the immediately preceding target data [that is, A (I, J-1)] is B (I2, J2-2), and the upper right data is B
(I2, J2-1). In the program list shown in FIG. 4, addresses 930 to 1090 are the notch data extension processing shown in Table 1. In this, I and J at 940 and 950
Is set, and the extended data of the target pixel is calculated from 960 to 1080.

Effect As described above, the expansion device of the present invention detects a notch and expands the notch at a lower magnification than the non-notch portion. Therefore, the notch portion is suppressed in the expanded data, and the image has its characteristics. It is corrected to a reasonable shape that shows well. The notch detection is relatively accurate, and even if an error occurs in the notch detection, the data at that portion is not completely erased, so that normal image information is not erased.

[Brief description of the drawings]

FIG. 1a is a block diagram showing the configuration of the image pattern data expansion device according to the first embodiment of the present invention, and FIG. 1b is a logic circuit showing the configuration of the information distribution pattern detection circuit 6 of the device shown in FIG. 1a. FIGS. 1c, 1d, 1e and 1f are flowcharts showing the schematic operation of the microprocessor 18 of the apparatus shown in FIG. 1a. FIG. 1g is a plan view showing the principle of extracting the reference pattern data PPM by the shift registers 3, 4 and 5 of the device shown in FIG. 1a, FIG. 1h is a plan view showing the reference pattern data PPM and the extension pattern EPM, FIG. FIG. 1 and FIG. 1j are plan views showing the image pattern original data ODP. FIGS. 1k, 1l, 1m, 1n, 1p and 1q are plan views showing reference pattern data PPM including dummy data. FIG. 2a is a block diagram showing the outline of the configuration of the image pattern data expansion device shown in FIG. 1a, and FIG. 2b is a block diagram showing the outline of the configuration of a modification. FIG. 2c shows the reference pattern data PPM according to the second embodiment of the present invention.
FIG. 4 is a plan view showing the address of each bit data of FIG. FIG. 3 is a block diagram showing an outline of the configuration of an image pattern data expansion device according to a second embodiment of the present invention. FIG. 4 is a plan view showing a program list executed by the microcomputer 31 of the second embodiment. FIG. 5a is a plan view showing an image recorded based on the original image data. FIG. 5b is a plan view showing an image recorded based on extended data obtained by enlarging the original image data four times in area as it is. FIG. 6 is a plan view showing an image recorded based on data obtained by expanding the original image data in the first embodiment. 100: Image pattern generator (image pattern data memory means) 200: Reference pattern extraction circuit (image pattern data reading means) 300: Extended data generation circuit (extended data generation means) 400: Output buffer memory (extended data memory means) 500 : Read / write control circuit (image pattern data reading means) 2: Parallel in / serial out register 3,4,5: Shift register 6: Information distribution pattern detection circuit 7,8,9,10,11,12: Serial in / Parallel out register 13, 14: Latch 15: Data selector 16: Multiplexer 18: Microprocessor 19: System controller 20: Pulse generator 21, 22: Counter 30: Image pattern generator (image pattern data memory means) 31: Microcomputer (Image pattern data reading means, extended data generating means, extended data memory means) 32: Output device DLY : Delay circuit

Claims (2)

(57) [Claims] 1. An image data expansion device for converting original image bit data having a predetermined pixel density into output image bit data for a plurality of pixels in each of vertical and horizontal directions, an image data memory means for holding original image bit data; The bit data corresponding to the pixel of interest to be converted and the bit data corresponding to each of at least eight pixels adjacent to the pixel of interest are used as a reference pattern, and are sequentially updated by sequentially updating the pixel of interest. Image pattern data reading means to be read, detecting whether the target pixel is a notch pixel on the original image from the reference pattern, and when not a notch pixel, the same bit data as the bit data of the target pixel for a plurality of pixels in the vertical and horizontal directions. Occurs, and in the case of a notch pixel, at least a column and a row of a region of a plurality of pixels each in the vertical and horizontal directions. An extended data generating means for generating bit data different from the pixel of interest and suppressing the notch in the column, and generating the same bit data as the pixel of interest for the other pixels, and a bit data generated by the extended data generating means. An image data expansion device, comprising: an expansion data memory means for storing. 2. The image data expansion device according to claim 1, wherein the area of a plurality of pixels in each of the vertical and horizontal directions is 2 pixels or more × 2 pixels or more.