JP2015521804A - Thin film transistor manufacturing method - Google Patents

Abstract

A method for manufacturing a bottom gate / top contact metal oxide semiconductor thin film transistor, comprising: forming a gate electrode on a substrate; forming a gate dielectric layer to cover the gate electrode; Depositing a metal oxide semiconductor layer on the body layer, depositing a metal layer on the metal oxide semiconductor layer, and patterning the metal layer to form source and drain contacts. The step of patterning the metal layer includes a step of dry etching the metal layer and a step of patterning the metal oxide semiconductor layer thereafter. [Selection] Figure 1

Description

  The disclosed technology relates to a method of manufacturing a metal oxide semiconductor thin film transistor, and more particularly to a method of manufacturing a metal oxide semiconductor bottom gate / top contact thin film transistor and a thin film transistor obtained thereby.

Metal oxide semiconductors find potential applications in thin film electronics such as large area displays and circuits because they can achieve excellent electrical properties at low process temperatures. For example, thin film transistors (TFTs) using amorphous gallium-indium-zinc-oxide (a-GIZO) as an active layer have already been implemented. Achieving good mobility (μ) and good threshold voltage (V _TH ) control is the key to successfully replacing traditional amorphous Si TFT backplanes with amorphous metal oxide semiconductor TFT backplanes in displays. It is an important parameter.

  In the manufacturing process of bottom gate top contact (BGTC) metal oxide semiconductor thin film transistors, an etch stop layer is often used to protect the metal oxide semiconductor layer from plasma damage during further processing. In such a process, after forming the gate and gate dielectric layer on the substrate, a metal oxide semiconductor layer is deposited and patterned on the gate dielectric layer. Next, an etch stop layer is deposited on the metal oxide semiconductor layer, followed by patterning the etch stop layer. Next, a metal layer is deposited and patterned by dry plasma etching to form source and drain contacts. During patterning to form the source and drain contacts, the etch stop layer protects the underlying metal oxide semiconductor layer from damage caused by the metal etching process.

  In an alternative process flow, the use of an etch stop layer can be avoided by using a wet etch process to pattern the metal layer over the metal oxide semiconductor layer. However, finding an etchant with good etch selectivity between the metal layer and the metal oxide semiconductor layer is a challenge, which limits the combinations of materials that can be used.

  One embodiment of the present invention relates to a method for manufacturing a good metal oxide semiconductor thin film transistor in which patterning of a source contact and a drain contact on a metal oxide semiconductor layer is performed by dry etching, and it is not necessary to use an etch stop layer. .

  One aspect of the invention relates to a method of manufacturing a bottom gate / top contact metal oxide semiconductor thin film transistor, the method comprising: forming a gate electrode on a substrate; forming a gate dielectric layer covering the gate electrode; Depositing a metal oxide semiconductor layer on the gate dielectric layer. The method further includes depositing a metal layer or metal layer stack over the metal oxide semiconductor layer and patterning the metal layer or metal layer stack to form a source contact and a drain contact of the thin film transistor. The step of patterning the metal layer or the metal layer stack includes a step of dry etching the metal layer or the metal layer stack, and a step of patterning the metal oxide semiconductor layer, for example, immediately thereafter. The method may further include additional processes such as depositing a passivation layer and / or an annealing step. An annealing step is preferably applied to cure the damage formed by the plasma process during device fabrication and / or for obtaining good passivation.

  The metal oxide semiconductor layer may be, for example, an amorphous IGZO (indium / gallium / zinc / oxide) layer. However, the present disclosure is not limited to this, and other metal oxide semiconductor layers such as InZnO, HfInZnO, SiInZnO, ZnO, CuO, or SnO layers may be used.

  In the method according to one aspect of the invention, the step of patterning the metal oxide semiconductor layer is performed after patterning the metal layer or the metal layer stack on the metal oxide semiconductor layer, that is, forming the source contact and the drain contact. Will be done later. The advantage of using such a sequence of process steps is that the risk of damaging the metal oxide semiconductor layer during the dry metal etch, eg, in the channel region of a thin film transistor, is reduced by the dry (plasma) etch metal layer or metal layer stack. Compared with the process sequence in which the metal oxide semiconductor layer is patterned before patterning is significantly reduced.

  It is an advantage of the method according to one aspect of the invention that there is no need to form and pattern an etch stop layer, thereby reducing the number of masks required, thereby reducing the number of process steps and manufacturing costs. is there.

  It is an advantage of the method according to one aspect of the invention that the transistor size, in particular the channel length, can be reduced compared to the method using an etch stop layer. For example, depending on the substrate size and the lithographic apparatus used, a transistor having a channel length on the order of about 2 to 5 micrometers can be formed using the method according to one aspect of the invention, In prior art methods using an etch stop layer, the lower limit of channel length is on the order of about 5 to 20 micrometers. In general, the channel length can be reduced by a factor of about 3 as compared to a thin film transistor formed using an etch stop layer. Therefore, when the method according to one aspect of the invention is used in the display manufacturing process, smaller pixels are formed, and an improved resolution display can be manufactured.

Good field effect mobility (eg, in the range of about 2 cm ² / Vs to 100 cm ² / Vs), low I _OFF current (eg, below about 10 pA), and low subthreshold slope (eg, below about 1 V / decade) It is an advantage of the method according to one aspect of the invention that a metal oxide semiconductor thin film transistor having favorable characteristics as described above can be manufactured.

  It is an advantage of the method according to one aspect of the invention that it is compatible with current production lines used for mass production of amorphous silicon thin film transistors and circuits. In particular, the manufacturing process used in the embodiment of the present invention can be performed on an existing manufacturing line for amorphous silicon TFTs. This also implies that metal oxide TFTs can be manufactured using the method according to embodiments of the present invention on current production lines for amorphous silicon TFTs.

  The method according to one aspect of the invention can also be used characteristically to make an array of metal oxide semiconductor thin film transistors, for example for selecting or driving pixels of a display.

  Certain objectives and advantages of some inventive aspects have been described above. Of course, it is understood that not all such objectives and advantages need be achieved in any particular embodiment of the present disclosure. Thus, for example, the disclosure may be embodied in a manner that achieves or optimizes one advantage or group of advantages taught herein without having to achieve other objectives or advantages taught or suggested herein. One skilled in the art will recognize that can be implemented or implemented. Moreover, this summary is merely an example and is not intended to limit the scope of the present disclosure. The present disclosure, both in terms of mechanism and method of operation, together with its features and advantages will be best understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

The process sequence concerning the example of this indication is shown typically. 3 illustrates a method according to an embodiment of the present disclosure. 3 illustrates a method according to an embodiment of the present disclosure. 3 illustrates a method according to an embodiment of the present disclosure. 3 illustrates a method according to an embodiment of the present disclosure. 3 illustrates a method according to an embodiment of the present disclosure. GIZO thin film transistor (LO Mo) having source and drain contacts formed by metal lift-off, and GIZO thin film transistor having source and drain contacts deposited and patterned by dry etching after GIZO patterning without using an etch stop layer 2 shows measured transistor characteristics with (DE Mo). Figure 3 shows measured transistor characteristics of a GIZO thin film transistor made by the method of an embodiment of the present invention. Fig. 4 shows transistor characteristics of GIZO thin film transistors measured at different positions of an array made on a 6 inch substrate according to embodiments of the present invention. Three a-IGZO TFTs each processed using standard BCE (S / D etch after IGZO etch), BCE process according to aspects of the invention (S / D etch before IGZO etch), and conventional lift-off process, respectively The comparison result of transistor characteristics (V _GS -I _DS ) is shown. A comparison of the capacitance of MIS (with a-IGZO) and MIM structure (without a-IGZO) for an area of 500 × 500 μm ² is shown, showing a difference of less than 5%. (A) Transistor of a-IGZOTFT (W / L = 70/10 μm / μm) as a function of stress time at V _GS = + 12 V and V _DS = + 12 V, (b) V _GS = −12 V and V _DS = 0 V The characteristics (V _GS -I _DS ) and (c) V _TH shift of a-IGZOFTFT as a function of stress time in both positive and negative directions are shown. (A) Transfer characteristics (V _GS -I _DS ) and (b) Output characteristics (V _DS -I _DS ) of drive TFT with W / L = 55/5 μm / μm, (c) Measured across PEN foil substrate 9 shows the transfer curves (at V _DS = 10V) of the nine TFTs that were fabricated.

  In the different drawings, the same reference signs refer to the same or analogous elements.

  In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure and how it may be implemented in particular embodiments. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, and techniques have not been described in detail so as not to obscure the present disclosure. On the other hand, the present disclosure will be described with reference to specific examples with reference to certain drawings, but the disclosure is not limited thereto. The drawings included and described herein are schematic and are not limiting the scope of the disclosure. In the drawings, the size of some of the elements may be exaggerated and therefore not illustrated on scale for illustrative purposes.

  In addition, the terms first, second, third, etc. in the description are used to distinguish between similar elements and need to represent an order or order in other ways, both temporally and spatially. Absent. The terms so used are interchangeable in appropriate circumstances, and it is understood that the embodiments of the disclosure described herein may operate in a different order than that described or shown herein. Will be done.

  Further, the terms “up”, “down”, “up”, “down” and the like in the description are used for convenience and do not need to indicate relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein can be implemented in different directions than those described or shown herein. It will be.

  The term “comprising” is not construed as being limited to the means listed thereafter; it does not exclude other elements or steps. Thus, features, numbers, steps, or ingredients referred to are construed accordingly and exclude the presence or addition of one or more other features, numbers, steps, or ingredients, or combinations thereof. must not. Thus, the scope of the expression “a device including means A and B” should not be limited to devices including only components A and B.

  Certain embodiments provide a method of fabricating a bottom gate / top contact metal oxide semiconductor thin film transistor, the method comprising forming a gate electrode on a substrate and forming a gate dielectric layer on the gate electrode. And depositing a metal oxide semiconductor layer over the gate dielectric layer. In one embodiment, the method further includes the steps of depositing a metal layer over the metal oxide semiconductor layer and patterning the metal layer to form a source contact and a drain contact, The step of patterning the layer includes a step of dry etching the metal layer and a step of patterning the metal oxide semiconductor layer thereafter. The method may further include additional steps such as depositing a passivation layer (such as silicon oxide, silicon nitride, and / or aluminum oxide) and / or an annealing step.

  In a method according to one specific example, the step of patterning the metal oxide semiconductor layer is performed after patterning the metal layer on the metal oxide semiconductor layer (by dry etching), that is, forming a source contact and a drain contact. Will be done later.

  An example of a process flow for producing a metal oxide semiconductor thin film transistor according to one specific example is schematically shown in FIG. 1 and further shown in FIG. A gate metal layer, such as a Mo, Ti, Cr, or Cu layer, or a Ti / Mo or Mo / Al / Mo stack, for example about 30 to 300 nm thick, on an electrically insulating substrate 10 After depositing the metal stack (process 1), the gate metal layer or metal stack is patterned (process 2) by means of photolithography and wet or dry etching to form the gate electrode 11. Next, a gate dielectric layer 12 such as a silicon oxide layer, silicon nitride layer, or aluminum oxide layer, or other preferred dielectric layer or layer stack known to those skilled in the art is deposited (process 3). ). The resulting structure is shown in FIG. The substrate may be a hard substrate, a flexible substrate, or a stretchable substrate. When processing on a flexible or stretchable substrate, the substrate is (temporarily) placed on a hard carrier during processing.

  A via (not shown) may be formed in the gate dielectric layer and connected to the gate. Next, a metal oxide semiconductor layer 13 such as an amorphous IGZO (indium / gallium / zinc / oxide) layer is deposited on the gate dielectric layer 12 (FIG. 2B) (process 4). . However, the present disclosure is not limited to this, and other metal oxide semiconductor layers may be used. Suitable metal oxide semiconductors are, for example, InZnO, HfInZnO, SiInZnO, ZnO, CuO, or SnO. The deposition process of the metal oxide semiconductor layer includes, for example, a DC or RF spat or vapor deposition process. The film thickness of the semiconductor layer 13 is, for example, in the range of about 10 nm to 80 nm.

  In the next process, a metal layer 14 or metal stack is deposited on the metal oxide semiconductor layer 13 (FIG. 2 (c)), for example by vapor deposition or sputtering (process 5). The metal layer or metal stack comprises, for example, Mo and has a film thickness in the range between about 50 nm and 300 nm. For example, a Mo / Al / Mo stack, a Mo / Au stack, a Mo / Ti stack, a Mo / Ti / Al / Mo stack, or a Mo / ITO stack may be used, but the present disclosure is not limited thereto. Absent. The metal layer or metal stack is patterned by lithography and dry (plasma) etching to form a source contact 141 and a drain contact 142 as shown in FIG. 2D (process 6). The channel length is, for example, in the range of 2 micrometers to 100 micrometers.

  After the metal layer is etched to form a source contact and a drain contact, the metal oxide semiconductor layer 13 is patterned by lithography and wet or dry etching (process 7) to form an active layer 131 on the transistor (FIG. 2 (e)).

  Next, a passivation layer, such as a silicon oxide, silicon nitride, or aluminum oxide layer having a thickness of about 50 nm to 300 nm, is deposited by sputtering, ALD, or CVD (process 8), plasma etching or wet etching. And patterned (process 9). Finally, the structure is annealed in a nitrogen atmosphere or in air, for example at a temperature between about 50 ° C. and 175 ° C. (process 10).

  When forming a thin film transistor circuit according to one embodiment, a capacitor formed in such a circuit includes a metal oxide semiconductor layer in addition to a dielectric layer between the metal layers.

The thin film transistor was manufactured by the process flow of FIGS. A patterned Mo gate (thickness: about 100 nm) was formed on an electrically insulating substrate. Next, a SiN gate dielectric layer about 100 nm thick was deposited by CVD. In the next process, an a-IGZO layer (In: Ga: Zn = 1: 1: 1 atomic%, film thickness was about 20 nm) was deposited by RF / DC sputtering in an O ₂ atmosphere. Next, a Mo source-drain contact (film thickness of about 100 nm) was formed on the a-IGZO layer by patterning using DC sputtering and a dry etching process (SF ₆ + O ₂ plasma). In the subsequent process, the active region was formed by photolithography and wet etching of the metal oxide layer (the a-IGZO layer was patterned). Finally, the passivation layer was sputtered (about 100 nm SiO _x ) and the transistor was subsequently annealed at 150 ° C. for about 1 hour in an N ₂ atmosphere.

The measured transistor characteristics of a transistor having a channel length of about 10 micrometers is shown in FIG. The transistor has high mobility (about 14.06 cm ² / Vs), low subthreshold slope (about 0.24 V / decade), low hysteresis, I _on / I _off greater than 10 ⁸ , and V _TH close to zero (about 0.5V).

  As a reference, GIZO thin film transistors are fabricated with different process flows without the use of an etch stop layer, where metal oxide semiconductor patterning and etching is performed after metal deposition instead of after source and drain metal patterning. Done before. For additional reference, the source and drain contacts were formed by means of a lift-off process (not suitable for high quality because it causes problems) to produce transistors.

The transistor characteristics of these reference transistors are shown in FIG. Transistors fabricated by etching a metal oxide semiconductor prior to metal deposition without using an etch stop layer (“DE Mo” in FIG. 3) have a clearly low I _ON / I _OFF ratio, high subthreshold slope, and Has a large hysteresis. This is related to the negative impact of the plasma used for source and drain etching on the GIZO layer, and in particular to the non-uniform distribution of the plasma on the wafer surface due to the distributed semiconductor channel region.

  In a method according to a preferred embodiment, when the source and drain are etched, the metal oxide semiconductor layer is not yet patterned. Therefore, the plasma is more evenly distributed over the entire substrate, reducing partial plasma non-uniformity and / or reducing partial plasma charging effects on the metal oxide semiconductor layer.

  A functioning display was made comprising an array of thin film GIZO transistors for selecting and driving array pixels. The GIZO transistor has a channel length of about 5 micrometers and was fabricated by the method according to one embodiment. An array of transistors was fabricated on an approximately 6 inch substrate. FIG. 5 shows the measured transfer characteristics of the five transistors of this array, with one transistor located at the center of the substrate and the other four transistors located at opposite ends of the substrate. The result shows good uniformity of transistor characteristics on the substrate.

Further experimental results are shown below.
The test device was realized on a SiO ₂ (120 nm) gate dielectric thermally grown on a highly doped Si (common gate) substrate. An active layer of a 15 nm thick a-IGZO (In: Ga: Zn = 1: 1: 1) film was deposited by dc sputtering containing 6% O ₂ in argon (Ar). Film thickness and O ₂ / Ar ratio are optimized to achieve the desired TFT performance at low process temperatures. Further, 100 nm thick Mo source and drain (S / D) contacts were formed by PVD and patterning by SF ₆ / O ₂ dry etch chemistry. After the S / D formation, the active layer was patterned by a wet etching procedure using an oxalic acid solution. On top of the active layer, a 100 nm SiO ₂ passivation layer was deposited with reactive pulse DCPVD.

The electrical characteristics of the independent TFT were measured using a parameter analyzer in an inert N ₂ atmosphere.

  By reversing the process order of a-IGZO patterning and S / D contact patterning compared to prior art approaches, the method of the present invention avoids isolated islands of a-IGZO and plasma etching. Suppresses partial accumulation of charge inside. By modifying the standard BCE process flow in this way, key TFT parameters such as hysteresis, mobility, and overall sub-threshold slope show significant improvements.

Three sets of a conventional lift-off flow, a standard BCE flow (S / D etching before semiconductor patterning), and a modified BCE flow (S / D etching after semiconductor patterning) according to the embodiment of the present invention. The IV characteristics of the test FET are shown in FIG. All test devices were realized on SiO ₂ (120 nm) gate dielectrics thermally grown on highly doped Si (common gate) substrates. An a-IGZO test device made with a modified BCE flow according to an aspect of the present invention exhibits a negligible amount of hysteresis in the transfer curve between forward and reverse gate voltage sweeps. In fact, this result is very similar to that obtained with lift-off S / D based devices.

Table 1 outlines the main performance parameters of the three different flows.

The transfer characteristics of a standard BCE treated TFT are only 5-12 cm ² / (V · s), lower mobility, reduced subthreshold swing of 0.60 V / decade, and negative of −0.5 V The threshold voltage is shown. Furthermore, the hysteresis in the transfer curve increased sufficiently compared to the other two flows. The latter indicates that more damage was induced during dry etching of the S / D metal layer on the small island of a-IGZO. Damage is due to partial charge buildup due to plasma exposure during the dry etch process in the isolated active region. Overall, it was observed that the modified BCE flow led to a substantial improvement in device characteristics.

Further, it was verified whether the fact that the a-IGZO layer is under the metal line potentially affects the parasitic capacitance of the signal line. This is particularly important in (TFT) displays and circuit applications. To verify this effect, two capacitors corresponding to a gate dielectric with and without a-IGZO were compared. As shown in FIG. 7, only a 5% change in total volume was measured. Furthermore, the influence of bias stress on the electrical characteristics of the TFT was investigated. Forward and corresponding gate field in the negative direction +/- 1.0MV / cm (gate-field ) is between 10 ⁴ seconds stress time, at room temperature, given in the dark. In the case of positive gate bias (V _DS = 12 V and V _GS = 12 V), a threshold voltage shift of 0.9 V was observed corresponding to the fully on state. In the case of negative bias (V _DS = 0 V and V _GS = −12 V), a threshold voltage shift of 1.0 V was observed. FIGS. 8A and 8B show changes in transfer characteristics as a function of bias stress time for both positive and negative gate biases. FIG. 8 (c) shows a comparison of _VTH shift as a function of stress time for both positive and negative gate biases.

  Finally, a modified BCE process flow according to embodiments of the present invention was integrated on a PEN foil with 200 nm ICP-CVD SiN as the gate dielectric and 100 nm MoCr as the gate metallization.

A substrate foil embodied as a commercially available 25 μm thick thermally stabilized PEN foil was laminated onto a 150 mm hard glass carrier. The carrier supports during the entire fabrication process of the digital circuit and display. In the first step, a 200 nm SiN barrier layer was deposited on the PEN foil by inductively coupled chemical vapor deposition (ICP-CVD) at 150 ° C. A gate metallization consisting of a 100 nm thick MoCr alloy layer was formed by physical vapor deposition (PVD) followed by a wet etch procedure. Next, a 200 nm thick SiN gate dielectric layer was deposited by ICP-CVD at 150 ° C. Low gate leakage current and high breakdown field are required for TFTs used to form blocks in circuit and display backplanes. The challenge is to achieve good dielectric properties using conventional CVD deposition at the low temperatures (<200 ° C.) required for processing on PEN foil. Therefore, the processing conditions were optimized with a SiN dielectric layer deposited by ICP-CVD at 150 ° C. An approximately 8 MV / cm breakdown electric field with a leakage of 1.3e ⁻⁶ mA / cm ² (dielectric constant ε = 7.1) at ² MV / cm was achieved.

Next, an active layer of a 15-nm thick a-IGZO (In: Ga: Zn = 1: 1: 1) film was deposited by dc sputtering containing 6% O ₂ in argon (Ar). Film thickness and O ₂ / Ar ratio were optimized to achieve the desired TFT characteristics at low processing temperatures. In addition, 100 nm thick Mo source and drain (S / D) contacts were formed by PDV and patterned by SF ₆ / O ₂ dry etch chemistry. After the formation of S / D, the active layer was patterned by a wet etch procedure using an oxalic acid solution. On top of the active layer, a 100 nm SiO ₂ passivation layer was deposited with reactive pulse DCPVD.

The transfer characteristics and output characteristics of the resulting TFT (W / L = 55/5 μm / μm) are shown in FIG. TFT is, 12~15cm ² / linear mobility (V · s) (μ) , - 1.0V of _{^{V TH, 10 8 I ON /}} I OFF ratio, and 0.3V / decade of subthreshold Shows shaking. In FIG. 9 (c), it was measured across a six-inch wafer comprising PEN foil spread of _{V ON} and _{I ON} of the TFT is shown. The V _ON and I _ON spread at V _D = 10V and V _G = 20V is less than 5%.

  The foregoing description details certain specific examples of the disclosure. It should be understood, however, that no matter how detailed the foregoing appears in text, the present disclosure can be implemented in many ways. In describing a given feature or form of the present disclosure, the use of a particular term is herein re-described so that the term is limited to include the particular feature of the disclosed feature or form to which the term relates. It should be noted that it should not be taken to imply defining.

  While the foregoing detailed description has shown, described, and pointed out novel features of the present disclosure, as applied to various embodiments, various omissions in the shape and details of the described devices or processes are described. It will be understood that substitutions, alterations, and modifications can be made by those skilled in the art without departing from the spirit of the disclosure.

Claims (11)

A method of manufacturing a bottom gate / top contact metal oxide semiconductor thin film transistor,
Forming a gate electrode on the substrate;
Forming a gate dielectric layer covering the gate electrode;
Depositing a metal oxide semiconductor layer on the gate dielectric layer;
Depositing a metal layer or metal layer stack on the metal oxide semiconductor layer;
Patterning a metal layer or metal layer stack to form source and drain contacts;
Patterning the metal layer or metal layer stack includes dry etching the metal layer or metal layer stack;
And subsequently patterning the metal oxide semiconductor layer.   The method of claim 1, further comprising depositing a passivation layer and performing an annealing process.   The method according to claim 1 or 2, wherein the metal oxide semiconductor layer comprises or consists of an amorphous IGZO (indium gallium zinc oxide) layer.   The method according to claim 1 or 2, wherein the metal oxide semiconductor layer includes or consists of any of InZnO, HfInZnO, SiInZnO, ZnO, CuO, or SnO layers.   The method according to claim 1, wherein the metal oxide semiconductor layer has a thickness of 10 to 80 nm. The metal oxide semiconductor layer comprises or consists of Mo;
The metal layer stack comprises or consists of a Mo / Al / Mo stack, a Mo / Au stack, a Mo / Ti stack, a Mo / Ti / Al / Mo stack, or a Mo / ITO stack. The method of crab.   The method according to any of claims 1 to 6, wherein the metal layer or metal layer stack has a thickness of about 50 nm to 300 nm.   The step of patterning the metal oxide semiconductor layer is performed after patterning a metal layer or a metal layer stack on the metal oxide semiconductor layer to form a source contact and a drain contact. The method described in 1.   The method according to claim 1, wherein the substrate comprises polyethylene naphthalate foil.   10. A method according to any preceding claim, further comprising forming a via in the gate dielectric layer to connect to the gate.   Use of the method according to any of claims 1 to 10 for the production of a transistor having a channel length on the order of 2 to 5 micrometers.

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