JP2016225505A - Thin film transistor, method of manufacturing the same, and sputtering target - Google Patents

Abstract

In a thin film transistor using an oxide semiconductor layer, a thin film transistor having higher mobility than the conventional thin film transistor and a manufacturing method thereof are provided. A thin film transistor has at least a gate electrode 2, a gate insulating film, an oxide semiconductor layer 4, a source-drain electrode 5, and a protective film such as SiNx for protecting the source-drain electrode 5 in this order on a substrate. In the thin film transistor, the oxide semiconductor layer 4 has a semiconductor region and a conductor region, and a conductor region formed by hydrogen diffused from a protective film such as SiNx has at least a channel region and an end portion of the oxide semiconductor layer 4 It exists in 1 or more of them, and has a high mobility. [Selection] Figure 1

Description

  The present invention relates to a thin film transistor, a method for manufacturing the same, and a sputtering target. The thin film transistor of the present invention is suitably used for display devices such as a liquid crystal display and an organic EL display. Hereinafter, the thin film transistor may be referred to as a TFT (Thin Film Transistor).

  An oxide semiconductor has higher carrier mobility than general-purpose amorphous silicon. Oxide semiconductors have a large optical band gap and can be deposited at low temperatures, so they can be applied to next-generation displays that require large size, high resolution, and high-speed driving, and resin substrates with low heat resistance. Is expected.

  When the oxide semiconductor is used as a semiconductor layer of a TFT, it is required that the TFT has excellent switching characteristics. Specifically, (1) the on-current, that is, the maximum drain current when a positive voltage is applied to the gate electrode and the drain electrode is high, and (2) the off-current, ie, the negative voltage is applied to the gate electrode. When the positive voltage is applied, the drain current is low, (3) the S value (Subthreshold Swing), that is, the gate voltage required to increase the drain current by one digit is low, and (4) the threshold voltage, ie, When a positive voltage is applied to the drain electrode and a positive or negative voltage is applied to the gate voltage, the voltage at which the drain current begins to flow is stable without changing over time, and (5) field-effect mobility , It may be simply referred to as mobility).

As the oxide semiconductor, for example, as shown in Patent Documents 1 to 3, an In—Ga—Zn-based oxide semiconductor composed of indium, gallium, zinc, and oxygen, or In— composed of indium, gallium, tin, and oxygen. Ga-Sn oxide semiconductors are known. However, when a TFT is manufactured using the above oxide semiconductor, the upper limit of the field effect mobility is about 10 cm ² / Vs. In recent years, materials exhibiting higher mobility have been demanded in order to cope with an increase in screen size, resolution, and speed of display devices.

JP 2010-219538 A JP 2011-174134 A JP 2013-249537 A

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a thin film transistor exhibiting a higher mobility than the conventional one, for example, an extremely high mobility of about 40 cm ² / Vs or more, a method for manufacturing the same, and a method for manufacturing the thin film transistor. The object is to provide a sputtering target for forming an oxide semiconductor layer.

  The thin film transistor of the present invention that has solved the above problems has at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and a protective film for protecting the source-drain electrode in this order on a substrate. A thin film transistor, wherein the oxide semiconductor layer has a semiconductor region and a conductor region, and the conductor region is present at least in one or more of a channel region and an end of the oxide semiconductor layer. .

  The thin film transistor of the present invention that has solved the above problems has at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and a protective film for protecting the source-drain electrode in this order on a substrate. A thin film transistor, wherein when viewed from the top surface of the substrate, an end portion x adjacent to the channel region of the oxide semiconductor layer is an end of the source-drain electrode adjacent to the channel region and in direct contact with the oxide semiconductor layer It is also characterized by being located outside the portion y and having a shortest distance d between the end x and the end y of 3 μm or more and 100 μm or less.

The oxide semiconductor layer is made of an oxide composed of In, Ga, Sn, and O, and the atomic ratio of each metal element satisfies all of the following formulas (1) to (3). The film preferably contains SiNx.
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3)

In the oxide semiconductor layer, the atomic ratio of In and Ga preferably satisfies the following formula (4).
0.60 ≦ In / (In + Ga) ≦ 0.75 (4)

  It is preferable that at least a part of the oxide semiconductor layer has an amorphous structure.

  The present invention also defines a method for manufacturing the thin film transistor. The manufacturing method includes a step of forming an oxide semiconductor layer by sputtering under conditions of a gas pressure of 1 to 5 mTorr and a step of heat-treating at a temperature of 200 ° C. or higher after forming a protective film. Have

The present invention also includes a sputtering target used for forming the oxide semiconductor layer of the thin film transistor. The sputtering target is characterized by having In, Ga, Sn, and O and satisfying all of the following formulas (1) to (3).
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3)

  According to the present invention, a TFT having higher mobility than the conventional one can be provided.

FIG. 1 is a top view schematically showing Embodiment 1 of the thin film transistor of the present invention. FIG. 2 is a cross-sectional view of the thin film transistor of FIG. FIG. 3 is a top view schematically showing Embodiment 2 of the thin film transistor of the present invention. 4 is a cross-sectional view of the thin film transistor of FIG. FIG. 5 is a top view of a conventional thin film transistor. 6 is a cross-sectional view of the thin film transistor of FIG. FIG. 7 is a top view schematically showing a thermal image observation region in the embodiment. FIG. 8 is a thermal image when a current is applied to the thin film transistor in the embodiment.

The inventors of the present invention have disclosed a TFT using an oxide semiconductor as a semiconductor layer, that is, at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and a protection for protecting the source-drain electrode on a substrate. In order to improve the mobility of TFTs having films in this order, studies have been repeated. As a result, the oxide semiconductor layer in which the source electrode and the drain electrode are electrically connected has a conductor region together with the semiconductor region, and the conductor region is at least one of the following (i) and (ii): If present, the present inventors have found that a higher mobility than conventional can be obtained, and completed the present invention.
(I) Between a channel region in the oxide semiconductor layer, that is, a region of the oxide semiconductor layer that is in direct contact with the source electrode, and a region of the oxide semiconductor layer that is in direct contact with the drain electrode (ii) an end portion of the oxide semiconductor layer

  The oxide semiconductor layer having the conductor region does not require a special process. For example, as described later, the amount of overlap between the source-drain electrode and the oxide semiconductor layer is controlled, and SiNx is included as a hydrogen diffusion source. This can be realized by using a protective film and controlling hydrogen injection into the oxide semiconductor layer.

  Note that in the structure of the oxide semiconductor layer, it is preferable that the ratio of the metal elements is substantially the same in a series of the semiconductor region, the conductor region, and the semiconductor region.

  In particular, the oxide semiconductor layer is preferably an In—Ga—Sn-based oxide semiconductor layer containing In, Ga, and Sn as metal elements in order to obtain a TFT with high mobility. For example, an oxide semiconductor layer including an oxide including In, Ga, Sn, and O can be given.

In addition, it is preferable to appropriately control the atomic ratio of each metal element. Specifically, the atomic ratio of each metal element to the total of In, Ga, and Sn in the oxide semiconductor layer made of an oxide composed of In, Ga, Sn, and O is expressed by the following formula (1). It is preferable to satisfy all of (3). Hereinafter, In / (In + Ga + Sn) may be referred to as an In atom number ratio, Ga / (In + Ga + Sn) may be referred to as a Ga atom number ratio, and Sn / (In + Ga + Sn) may be referred to as an Sn atom number ratio. Each atomic ratio will be described.
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3)

  In is an element that contributes to the improvement of electrical conductivity. As the In atom number ratio increases, that is, as the amount of In in the metal element increases, the conductivity of the oxide semiconductor layer improves, so that the field effect mobility increases. In order to effectively exhibit the above action, the In atom number ratio is preferably set to 0.30 or more. The In atom number ratio is more preferably 0.31 or more, still more preferably 0.35 or more, and still more preferably 0.40 or more. However, if the In atom number ratio is too large, the carrier density increases too much and the threshold voltage tends to decrease. Therefore, the upper limit is preferably 0.50 or less. The In atom number ratio is more preferably 0.48 or less, and still more preferably 0.45 or less.

  Ga is an element that contributes to reduction of oxygen deficiency and control of carrier density. As the Ga atom number ratio is larger, the electrical stability of the oxide semiconductor layer is improved, and the effect of suppressing excessive generation of carriers is exhibited. In order to effectively exhibit the above action, the Ga atom number ratio is preferably 0.20 or more. The Ga atom number ratio is more preferably 0.22 or more, and further preferably 0.25 or more. However, when the Ga atom number ratio is too large, the conductivity of the oxide semiconductor layer is lowered and the field-effect mobility is easily lowered. Therefore, the Ga atom number ratio is preferably 0.30 or less. The Ga atom number ratio is more preferably 0.28 or less.

  Sn is an element that contributes to improvement of acid etching resistance. As the Sn atomic ratio is larger, the resistance of the oxide semiconductor layer to the inorganic acid etchant is improved. In order to more effectively exhibit the above action, the Sn atom number ratio is preferably set to 0.25 or more. The Sn atom number ratio is preferably 0.30 or more, more preferably 0.31 or more, and still more preferably 0.35 or more. On the other hand, if the Sn atom number ratio is too large, the field effect mobility of the oxide semiconductor layer is lowered and the resistance to the acid etching solution is increased more than necessary, and the oxide semiconductor layer itself is likely to be difficult to process. Therefore, the Sn atom number ratio is preferably 0.45 or less. The Sn atom number ratio is more preferably 0.40 or less, and still more preferably 0.38 or less.

Furthermore, the oxide semiconductor layer preferably has an atomic ratio of In and Ga that satisfies the following formula (4).
0.60 ≦ In / (In + Ga) ≦ 0.75 (4)

  Increasing the amount of In increases the carrier density, but the number of defects increases and the reliability tends to decrease. Thus, by adding Ga in a balanced manner so as to satisfy the above formula (4), the carrier density and defects can be controlled, and a highly reliable oxide semiconductor can be obtained.

  It is preferable that at least a part of the oxide semiconductor layer has an amorphous structure. Although an oxide semiconductor layer exhibiting high mobility and high reliability may be crystallized, it is preferable that at least a part of the oxide semiconductor layer of the present invention has an amorphous structure as described above. An oxide semiconductor layer partly having an amorphous structure is preferable from the viewpoint of productivity and yield over an oxide semiconductor that is entirely crystallized because the workability in the wet etching process is favorable. Here, “at least a part is amorphous” means that the degree of amorphization is not particularly limited as long as the TFT including the oxide semiconductor layer exhibits extremely high mobility. The fact that the oxide semiconductor layer of the present invention has an amorphous structure can be confirmed by, for example, a cross-sectional TEM image of the oxide semiconductor layer.

  In order to obtain a TFT having an oxide semiconductor layer including the conductor region and exhibiting high mobility, the structure of the TFT is particularly preferably as follows. That is, when viewed from the top surface of the substrate, the end portion x adjacent to the channel region of the oxide semiconductor layer is more than the end portion y of the source-drain electrode adjacent to the channel region and in direct contact with the oxide semiconductor layer. It is located outside and the shortest distance d between the end x and the end y satisfies 3 μm or more and 100 μm or less.

  With this structure, a mechanism that can realize high mobility can be obtained by hydrogen diffusion (diffusion) from the protective film in contact with the oxide semiconductor layer or the protective layer in contact with the oxide semiconductor layer to the oxide semiconductor layer by heat treatment. It is thought to be related to hydrogen compounds. When hydrogen or a hydrogen compound diffuses from the protective film to the oxide semiconductor layer, the carrier density of the oxide semiconductor layer increases, and the region where the hydrogen or hydrogen compound diffuses is considered to change from a semiconductor to a conductor.

  When promoting the conductorization of the end portion of the oxide semiconductor layer, in particular, as described above, the shortest distance d between the end portion x and the end portion y is 3 μm or more, and the oxide semiconductor layer is a protective layer. It is preferable to be in direct contact with the protective film or in contact with the protective film through an etch stop layer. By subjecting this structure to heat treatment at 200 ° C. or higher in the manufacturing process of the thin film transistor, hydrogen or a hydrogen compound contained in the SiNx layer constituting the protective film diffuses into the oxide semiconductor layer, and the oxide semiconductor layer It is considered that the conductor is formed around the end. On the other hand, since the source-drain electrode functions as a barrier film for hydrogen diffusion, if the shortest distance d described above is shorter than 3 μm, that is, if the oxide semiconductor layer is widely covered with the source-drain electrode, the source-drain electrode is oxidized from the protective film. Hydrogen diffusion to the physical semiconductor layer is hindered, and it is difficult to sufficiently generate carriers in the oxide semiconductor layer. The shortest distance d is preferably 5 μm or more. On the other hand, even if the shortest distance d exceeds 100 μm, the mobility tends to decrease. Therefore, the shortest distance d is set to 100 μm or less. The shortest distance d is preferably 75 μm or less, more preferably 50 μm or less.

As shown in the examples described later, when the shortest distance d satisfies the above range, a very high mobility of 40 cm ² / Vs or more can be achieved.

  As means for effectively diffusing hydrogen into the oxide semiconductor layer, the following method can be cited in addition to controlling the shortest distance d. That is, when the thin film transistor is viewed from the top surface of the substrate, the area of the oxide semiconductor layer that is in direct contact with the protective layer and the etch stop layer is A, and the area that is not in direct contact with either the protective layer or the etch stop layer is B. Then, 0.1 ≦ A / (A + B) <1 may be satisfied. By satisfying the above range, an area where hydrogen contained in the protective film is directly diffused into the oxide semiconductor by heat treatment can be sufficiently ensured.

  In order to obtain the above-described oxide semiconductor layer having a conductor region, it is recommended that the protective film protecting the source-drain electrode contains SiNx. The SiNx is so-called silicon nitride. The x is a positive real number and indicates the degree of nitriding. According to the examination results of the present inventors, by using a TFT including both an oxide semiconductor layer having a predetermined composition and a SiNx-based protective film, hydrogen or a hydrogen compound contained in the protective film is converted into the oxide. It has been clarified that it is diffused (diffused) into the semiconductor layer and greatly contributes to the development of high mobility. Such a mobility improving effect can be obtained for the first time by using the TFT of the present invention.

Thereby, the mobility of the TFT is about 40 cm as compared with the case where the IGZO and the general-purpose In—Ga—Sn-based oxide semiconductor layer described in Patent Documents 1 to 3 described above are used as the oxide semiconductor layer. ² / Vs or higher.

  In order to promote diffusion of hydrogen from the protective film to the oxide semiconductor layer and to realize an oxide semiconductor layer having at least a part of an amorphous structure, the following (i) oxide semiconductor is used in the TFT manufacturing process. It is necessary to include a step of forming the layer by sputtering under a gas pressure of 1 to 5 mTorr, and (ii) a step of heat-treating at a temperature of 200 ° C. or higher after forming the protective film. Hereinafter, each step will be described.

(I) Step of forming oxide semiconductor layer by sputtering under conditions of gas pressure of 1 to 5 mTorr If the gas pressure when forming the oxide semiconductor layer by sputtering is less than 1 mTorr, the film density becomes insufficient. A preferable lower limit of the gas pressure is 2 mTorr or more. On the other hand, if the gas pressure exceeds 5 mTorr, the desired crystal structure cannot be obtained. The upper limit of the gas pressure is preferably 4 mTorr or less, more preferably 3 mTorr or less. A preferable atmosphere at the time of forming the oxide semiconductor layer is an air atmosphere or a water vapor atmosphere.

(Ii) Step of performing heat treatment at a temperature of 200 ° C. or higher after forming the protective film Furthermore, in the present invention, after forming the protective film, heat treatment (post-annealing) is performed at a temperature of 200 ° C. or higher. The heat treatment temperature is a temperature at which hydrogen contained in the protective film starts to diffuse. When the temperature of the heat treatment is less than 200 ° C., high mobility of the TFT does not appear. The minimum with preferable heat processing temperature is 250 degreeC or more, More preferably, it is 260 degreeC or more. On the other hand, if the heat treatment temperature is too high, the TFT becomes a conductor, so the upper limit is preferably 280 ° C. or lower. A more preferable upper limit is 270 ° C. or less.

  In the heat treatment, the heat treatment time is preferably controlled within a range of, for example, 30 to 90 minutes so that a desired crystal structure of the oxide semiconductor layer can be obtained. The atmosphere is not particularly limited, and examples thereof include a nitrogen atmosphere and an air atmosphere.

  The TFT formation process other than the above is not particularly limited, and a normal method can be adopted.

  A preferred embodiment of the TFT of the present invention having the above structure will be described in detail with reference to FIGS. However, the configuration of the present invention is not limited to FIGS. For example, in FIGS. 1 to 4 below, an ESL (Etch Stop Layer) type structure having an etch stop layer 9 is shown. However, the present invention is not limited to this, and the present invention does not include the etch stop layer 9. It can also be applied to a structure of the (Back Channel Etch) type. In the following, conventional TFTs are also shown in FIGS.

  1 and FIG. 2 are a top view and a cross-sectional view of Embodiment 1 illustrating the form of the thin film transistor of the present invention, and FIG. 2 is a cross-sectional view taken along line AA of FIG. 3 and 4 are a top view and a cross-sectional view of Embodiment 2 illustrating another embodiment of the thin film transistor of the present invention, and FIG. 4 is a cross-sectional view taken along line BB of FIG. 5 and 6 are a top view and a cross-sectional view of a conventional thin film transistor, and FIG. 6 is a cross-sectional view taken along line CC in FIG. In FIGS. 1, 3 and 5, the display of the substrate 1 and the gate insulating film 3 is omitted. Although not shown in FIGS. 1, 3 and 5, the outermost surface of each is covered with a protective film 6. As shown in FIG. 1, the contact hole 7 has a shape surrounded by a broken line.

  1, 3, and 5, d indicates the shortest distance between the end of the oxide semiconductor layer adjacent to the channel and the end of the source-drain electrode that is close to the channel and is in direct contact with the oxide semiconductor layer. Therefore, in FIG. 1 illustrating Embodiment 1, the shortest distance between the end of the oxide semiconductor layer close to the channel and the end where the source-drain electrode 5 is in contact with the oxide semiconductor layer 4 through the contact hole 7 is d.

  In the following, the first and second embodiments will be described focusing on the first embodiment, which is significantly different from the conventional one.

  As shown in FIGS. 1 and 2, the TFT of Embodiment 1 includes a gate electrode 2, a gate insulating film 3, an oxide semiconductor layer 4, and an etch stop layer for protecting the oxide semiconductor layer 4 on a substrate 1. 9. A source-drain electrode 5 and a protective film 6 for protecting the source-drain electrode 5 are provided in this order, and the oxide semiconductor layer 4 is electrically connected to the source-drain electrode 5 through a contact hole 7. Yes. The TFT of Embodiment 1 uses the oxide semiconductor layer 4 having the composition described above. The TFT of Embodiment 2 shown in FIGS. 3 and 4 and the conventional TFT shown in FIGS. 5 and 6 also use the oxide semiconductor layer 4 having the composition described above.

  Note that the TFT of the first embodiment is configured such that both ends of the oxide semiconductor layer 4 are in contact with the etch stop layer 9 as shown in FIG. That is, the oxide semiconductor layer 4 is covered with the etch stop layer 9 so as to cover both ends in the channel length direction, and the both ends of the oxide semiconductor layer 4 are not in contact with the source-drain electrode 5. In this respect, both ends of the oxide semiconductor layer 4 are in contact with the source-drain electrode 5 as in the conventional TFT of FIGS. 5 and 6, that is, in the channel length direction of the oxide semiconductor layer 4. Is significantly different from the conventional structure in which both ends of the electrode are covered with the source-drain electrode 5.

  As shown in FIG. 1 showing a top view of the first embodiment, in the first embodiment, a part of the etch stop layer 9 is patterned, and the oxide semiconductor layer 4 is in contact with the source-drain electrode 5 through the contact hole 7. ing. On the other hand, in FIGS. 3 to 6 showing the second embodiment and the conventional structure, the patterned etch stop layer 9 and the source-drain electrode 5 are in contact with the oxide semiconductor layer 4 and the contact hole 7 has. Absent.

  Hereinafter, a preferred method for manufacturing the TFT of the above embodiment will be described. The TFTs shown in FIGS. 1 to 6 are different in patterning shape, but can be manufactured in the same process. However, the present invention is not limited to this.

First, the gate electrode 2 and the gate insulating film 3 are formed on the substrate 1. These forming methods are not particularly limited, and commonly used methods can be employed. Further, the types of the gate electrode 2 and the gate insulating film 3 are not particularly limited, and those commonly used can be used. For example, as the gate electrode 2, Al or Cu metal having a low electrical resistivity, refractory metal such as Mo, Cr, or Ti having high heat resistance, or an alloy thereof can be preferably used. The gate insulating film 3 is typically exemplified by a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and the like. In addition, oxides such as Al ₂ O ₃ and Y ₂ O ₃ and those obtained by stacking these can also be used.

  Next, the above-described oxide semiconductor layer 4 is formed. As described above, in the present invention, particularly when the oxide semiconductor layer is formed by sputtering, it is important to control the gas pressure within the range of 1 to 5 mTorr and to heat-treat at a temperature of 200 ° C. or higher after forming the protective film. It is. Therefore, processes other than these are not specifically limited, A normal method can be employ | adopted. The following methods can be preferably used as a method for forming the oxide semiconductor layer and a method for forming the protective film.

  When the TFT is viewed from the top surface of the substrate, the shape of the oxide semiconductor layer 4 and the shape of the source-drain electrode 5 described later are such that the end of the oxide semiconductor layer close to the channel is close to the channel and the oxide semiconductor layer. And controlling so as to be positioned outside the end of the source-drain electrode that is in direct contact with the electrode.

  For example, the oxide semiconductor layer 4 is preferably formed using a sputtering target by a sputtering method, for example, a DC sputtering method or an RF sputtering method. Hereinafter, the sputtering target may be simply referred to as “target”. According to the sputtering method, a thin film having excellent in-plane uniformity of components and film thickness can be easily formed. Alternatively, the oxide may be formed by a chemical film formation method such as a coating method.

  As a target used in the sputtering method, a target containing the above-described elements and having the same composition as the desired oxide is preferably used, so that a thin film having a desired component composition can be formed with little compositional deviation. Specifically, a target having In, Ga, Sn, and O and having an atomic ratio of each metal element to the sum of In, Ga, and Sn satisfying all of the above formulas (1) to (3) is used. It is recommended.

  The target can be manufactured by, for example, a powder sintering method.

  When the oxide semiconductor layer 4 is formed by sputtering using the above target, in addition to the gas pressure at the time of film formation described above, the partial pressure of oxygen, the input power to the target, the substrate temperature, the relationship between the target and the substrate It is preferable to appropriately control the distance between TS, which is a distance.

  Specifically, for example, it is preferable to form a film under the following sputtering conditions.

It is preferable to add the oxygen amount so that the carrier density of the oxide semiconductor layer is in the range of 1 × 10 ¹⁵ to 10 ¹⁷ / cm ³ so that the oxygen addition amount shows an operation as a semiconductor. The optimum oxygen addition amount may be appropriately controlled according to the sputtering apparatus, the composition of the target, the thin film transistor manufacturing process, and the like. In Examples described later, the addition flow rate ratio was set to 100 × O ₂ / (Ar + O ₂ ) = 4% by volume.

The higher the deposition power density, the better, and it is recommended to set it to approximately 2.0 W / cm ² or more in DC or RF. However, if the film formation power density is too high, the oxide target may be broken or cracked, and the upper limit is about 50 W / cm ² .

  It is recommended that the substrate temperature during film formation is controlled within the range of room temperature to 200 ° C.

  The preferable film thickness of the oxide semiconductor layer 4 can be about 10 nm or more, further 20 nm or more, and can be 200 nm or less, further 100 nm or less.

  After the oxide semiconductor layer 4 is formed, patterning is performed by wet etching. Immediately after the patterning, pre-annealing is preferably performed as a heat treatment for improving the film quality of the oxide semiconductor layer 4. Accordingly, the amount of defects in the oxide semiconductor layer can be suppressed, the above-described on-state current and field-effect mobility can be increased, and transistor performance can be improved. For example, the pre-annealing may be performed in a water vapor atmosphere or an air atmosphere at 250 to 400 ° C. for 10 minutes to 3 hours, particularly preferably at 350 to 400 ° C. for 30 to 60 minutes.

  Next, an etch stop layer 9 is formed. The method for forming the etch stop layer 9 is not particularly limited, and a commonly used method can be employed. Also, the type of the etch stop layer 9 is not particularly limited, and a commonly used one can be used. For example, a SiOx film is used.

  Here, in the TFT of the first embodiment, the contact hole 7 is formed in the etch stop layer 9 as shown in FIGS. In the TFT shown in FIGS. 3 to 6, the etch stop layer 9 is formed by patterning and the etch stop layer 9 is left in the channel portion, but no contact hole is formed.

After the formation of the etch stop layer 9 and before the formation of the source-drain electrode 5 described below, heat treatment (200 ° C. to 300 ° C.) is performed to recover damage from the oxide surface of the oxide semiconductor layer 4. ° C) or N ₂ O plasma treatment.

  Next, the source-drain electrode 5 is formed. The kind of the source-drain electrode 5 is not specifically limited, What is used widely can be used. For example, a metal or alloy such as Al, Mo, or Cu similar to the gate electrode may be used.

  The source-drain electrode 5 can be formed as follows. For example, after forming a metal thin film by magnetron sputtering, patterning can be performed by photolithography, and wet etching can be performed to form an electrode.

  The shape of the source-drain electrode 5 is close to a square as shown in FIG. 1 in the first embodiment, but is longer in the channel length direction in the second embodiment and FIGS. 3 and 5 showing the conventional structure.

After the formation of the source-drain electrode 5 and before the formation of the protective film 6 described below, heat treatment (200 ° C. to 300 ° C.) is performed as necessary to recover damage on the oxide surface of the oxide semiconductor layer 4. ) Or N ₂ O plasma treatment.

  Next, the protective film 6 is formed by a CVD (Chemical Vapor Deposition) method. As described above, in the present invention, the protective film 6 containing SiNx (silicon nitride film) is preferably used. Specific examples include a silicon nitride film, a silicon oxynitride film, and the like. These may be used alone or in combination, or may be used by stacking them. Alternatively, as shown in an embodiment described later, a laminated film in which the upper layer is SiNx and the lower layer is SiOx (silicon oxide film) may be used.

  After the formation of the protective film 6, post-annealing is performed for heat treatment at a temperature of 200 ° C. or higher.

  Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited by the following examples, and can be implemented with modifications within a range that can meet the purpose described above and below. They are all included in the technical scope of the present invention.

Example 1
In the following, the first and second embodiments of the present invention described above, the TFTs of FIGS. 1 and 2, FIGS. 3 and 4, and FIGS. 5 and 6 showing the conventional structure, respectively, are manufactured. The effect was examined.

  In the following examples, the process does not change due to the difference in the TFT structure, and therefore, the description will focus on the first embodiment. The manufacturing process of the second embodiment and the conventional TFT is the same as that of the first embodiment unless otherwise specified.

First, on a glass substrate 1 (Corning Eagle 2000, diameter 100 mm × thickness 0.7 mm), a Mo thin film of 100 nm is formed as a gate electrode 2 and a SiO ₂ film having a thickness of 200 nm is formed as a gate insulating film 3 sequentially. Filmed. The gate electrode 2 was formed by a DC sputtering method using a pure Mo sputtering target. The sputtering conditions were film formation temperature: room temperature, film formation power density: 3.8 W / cm ² , carrier gas: Ar, gas pressure during film formation: 2 mTorr, and Ar gas flow rate: 20 sccm. The gate insulating film 3 uses a plasma CVD method, carrier gas: a mixed gas of SiH ₄ and N ₂ O, film formation power density: 0.961127 W / cm ² , film formation temperature: 320 ° C., gas during film formation The film was formed under a pressure of 133 Pa.

Next, an oxide semiconductor layer (In—Ga—Sn—O film, film thickness: 40 nm) 4 that satisfies the following composition when the total amount of metal elements (In, Ga, Sn) was 100 atomic% was formed. .
In: Ga: Sn = 42.7 atomic%: 26.7 atomic%: 30.6 atomic%

Specifically, as described below, each sputtering target having the same composition as that of the oxide semiconductor layer 4 was used, and a film was formed by the sputtering method under the following conditions.
Sputtering equipment: “CS-200” manufactured by ULVAC, Inc.
Substrate temperature: Room temperature Gas pressure: 1 mTorr
Carrier gas: Ar
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 4% by volume
Deposition power density: 2.55 W / cm ²
In: Ga: Sn = 42.7 atomic%: 26.7 atomic%: 30.6 atomic% of the sputtering target used

  The analysis of the content of each metal element in the oxide semiconductor layer was performed by separately preparing a sample in which each oxide semiconductor layer having a thickness of 40 nm was formed on a glass substrate by the sputtering method in the same manner as described above. The analysis was performed by ICP (Inductively Coupled Plasma) emission spectroscopy using a model number: CIROS Mark II (manufactured by Rigaku Corporation).

  After forming the oxide semiconductor layer 4 as described above, patterning was performed by photolithography and wet etching. As a wet etchant, “ITO-07N” manufactured by Kanto Chemical Co., Inc. was used. In this example, it was confirmed that there was no residue due to wet etching and that etching was appropriately performed for all the oxide semiconductor layers tested.

  As described above, after the oxide semiconductor layer 4 was patterned, pre-annealing was performed to improve the film quality. Pre-annealing was performed at 350 ° C. for 1 hour in an air atmosphere.

After the pre-annealing, a silicon oxide film (SiOx, film thickness 100 nm) was formed on the oxide semiconductor layer 4 as the etch stop layer 9. The silicon oxide film was formed by a plasma CVD method using a mixed gas of N ₂ O and SiH ₄ . The film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 230 ° C., and gas pressure during film formation: 133 Pa. After the silicon oxide film was formed, the etch stop layer 9 was patterned by photolithography and dry etching. At this time, in the first embodiment, the contact hole 7 was formed at the same time as shown in FIGS.

Next, in order to form the source-drain electrode 5, a pure Mo film having a thickness of 200 nm was formed on the etch stop layer 9 by sputtering. The pure Mo film was formed under the following conditions: input power: DC 300 W (deposition power density: 3.8 W / cm ² ), carrier gas: Ar, gas pressure: 2 mTorr, substrate temperature: room temperature.

  Subsequently, the source-drain electrode 5 was patterned by photolithography and wet etching. Specifically, a mixed acid etchant having a phosphoric acid: nitric acid: acetic acid = 70: 2: 10 (mass ratio) liquid temperature of 40 ° C. was used. In this example, various TFT structures having the shortest distance d shown in Table 1 were obtained by changing the line width of the source-drain electrodes when viewed from the upper surface of the substrate.

After forming the source-drain electrode 5 in this manner, as a protective film 6 for protecting the thin film transistor, a laminated film having a total film thickness of 250 nm obtained by laminating a 100 nm thick SiOx film and a 150 nm thick SiNx film. Was formed by plasma CVD. A mixed gas of SiH ₄ , N ₂ , and N ₂ O was used for forming the SiO ₂ film, and a mixed gas of SiH ₄ , N ₂ , and NH ₃ was used for forming the SiNx film. In either case, the film formation conditions were film formation power density: 0.32 W / cm ² , film formation temperature: 150 ° C., and gas pressure during film formation: 133 Pa.

  Next, through holes 8 for probing for transistor characteristic evaluation were formed in the protective film 6 by photolithography and dry etching. Then, as post-annealing, heat treatment was performed at 260 ° C. for 30 minutes in a nitrogen atmosphere.

  The thin film transistor manufactured as described above had a channel length L of 20 μm and a channel width W of 200 μm. The thin film transistor was used for evaluation as follows. In addition, it demonstrates later that the oxide semiconductor layer of the thin-film transistor of this invention has a conductor area | region.

Measurement of shortest distance d The shortest distance d between the end portion x of the oxide semiconductor layer close to the channel and the end portion y of the source-drain electrode close to the channel and in direct contact with the oxide semiconductor layer is the embodiment. 1, 2, and 5 which are top views of the conventional structure, the distances d were measured. In this embodiment, when the end of the patterned oxide semiconductor layer 4 is outside the end of the source-drain electrode 5 that is in direct contact with the oxide semiconductor layer, d is a positive value and is inside. When d was a negative value.

  The following characteristics were examined for the TFT.

(1) Measurement of transistor characteristics The transistor characteristics (drain current-gate voltage characteristics, Id-Vg characteristics) were measured using a semiconductor parameter analyzer “HP4156C” manufactured by Agilent Technology. Detailed measurement conditions are as follows.
Source voltage: 0V
Drain voltage: 10V
Gate voltage: -30-30V (measurement interval: 0.25V)
Substrate temperature: room temperature

(2) Threshold voltage (Vth)
The threshold voltage is roughly a value of a gate voltage when the transistor shifts from an off state (a state where the drain current is low) to an on state (a state where the drain current is high). In this example, the voltage when the drain current is around 1 nA between the on-current and the off-current is defined as the threshold voltage, and the threshold voltage of each thin film transistor is measured.

(3) Field effect mobility μFE
The field effect mobility μFE is derived from the relational expression of drain current and gate voltage, Id = μFE × Cox × W × (Vgs−Vth) ² / 2L, in the saturation region where Vg> Vd−Vth from transistor characteristics. did. In this relational expression, Vgs: gate voltage, Vd: drain voltage, Id: drain current, L: channel length, W: channel width, Cox: capacitance of the gate insulating film, μFE: field effect mobility, Vth: This is the threshold voltage. In this embodiment, the field effect mobility μFE is derived from the slope of the drain current-gate voltage characteristic (Id-Vg characteristic) near the gate voltage that satisfies the linear region. The higher the field effect mobility, the better. In this example, 40 cm ² / Vs was used as a reference, and more than that was accepted.

(4) S value The S value is the minimum value of the gate voltage required to increase the drain current by an order of magnitude from the Id-Vg characteristic, and the lower the value, the better the characteristic. The S value is preferably 0.45 V / decade or less, and more preferably 0.40 V / decade or less.

  These results are also shown in Table 1.

Table 1 shows the following. No. As shown in Embodiments 1 and 2 of the present invention shown in 1-4 and 6-9, d is a positive value, that is, when the thin film transistor is viewed from the top surface of the substrate, the end of the oxide semiconductor layer adjacent to the channel is The mobility is 40 cm ² / Vs or more if it is located outside the end of the source-drain electrode that is in direct contact with the oxide semiconductor layer and d is in the range of 3 μm or more and 100 μm or less. It has been found that a sufficiently high mobility can be achieved than in the past. In contrast, no. When d is a negative value as in Nos. 11 to 15, or When d is zero as shown in FIG. As shown in FIG. 10, d was a positive value, but when it was outside the range of 3 μm or more and 100 μm or less, the TFT did not increase in mobility.

Example 2
A thin film transistor was manufactured in the same manner as in Example 1 except that the type of the protective film 6 was as shown in Table 2. In Example 2, all of Embodiments 1, 2 and the conventional structure were constant at the shortest distance d = 15 μm. In addition, the SiOx single film is formed by a plasma CVD method using a mixed gas of SiH ₄ , N ₂ , and N ₂ O, film formation power density: 0.32 W / cm ² , film formation temperature: 150 ° C., The gas pressure at the time of film formation was 133 Pa. The Al ₂ O ₃ film is formed by a reactive sputtering method using a mixed gas of argon and oxygen, sputter film formation power density: 1.36 W / cm ² , film formation temperature: room temperature, gas during film formation The pressure was 2 mTorr. Of the protective films, SiNx has the highest hydrogen content, followed by SiOx, and Al ₂ O ₃ has been confirmed to be almost zero.

Using the obtained thin film transistor, the characteristics were evaluated in the same manner as in Example 1. These results are also shown in Table 2.

  Table 2 shows the following. No. As shown in 1, 4 and 7, the protective film containing SiNx was able to achieve high mobility. In contrast, no. As shown in 2, 3, 5, 6, 8, and 9, when the protective film did not contain SiNx, high mobility could not be achieved.

  A drain current path was examined for the TFT of Embodiment 1 in which high mobility was obtained. Specifically, thermal image analysis was performed when current was applied using the TFT, and heat generation when the TFT was on was mapped. FIG. 7 is a schematic top view showing the thermal image observation region D in FIG. In FIG. 7, the etch stop layer 9 in FIG. 1 is not shown in order to clarify the observation region. The result of the thermal image analysis is shown in FIG. FIG. 8A shows the result of an example in which the In—Ga—Sn-based oxide semiconductor layer recommended in the present invention is used as the oxide semiconductor layer, and FIG. 8B shows the oxide semiconductor layer. The result of the example which used the IGZO film | membrane as a layer is shown. In FIG. 8A and FIG. 8B, the temperature distribution is displayed in gray scale. The higher the temperature, the lighter the display.

  From the result of FIG. 8 above, in particular, when the In—Ga—Sn-based oxide semiconductor layer of the present invention is used as the oxide semiconductor layer as shown in FIG. It was confirmed that heat was generated and the current path was confirmed. This is apparent from the fact that the heat distribution is different as compared with the TFT using the IGZO thin film as shown in FIG.

  From the data including the above results, the present inventors concluded that the TFT layout is important for increasing the mobility. It is considered important that the protective film overlaps with the oxide semiconductor layer without being blocked by the source-drain electrodes, and hydrogen is injected into the oxide semiconductor layer in the post-annealing step. Note that, as described above, the protective film and the oxide semiconductor layer may be directly overlapped or may be interposed via an etch stop layer.

  In the TFTs of FIGS. 1 to 4 showing Embodiments 1 and 2 of the present invention, high mobility was obtained. The reason is considered as follows. In the oxide semiconductor layer of the present invention in which hydrogen is sufficiently diffused from the protective film to the end portion of the oxide semiconductor layer, hydrogen becomes a donor and the carrier density is increased, so that the oxide semiconductor layer is easily formed into a conductor. In particular, the pattern edge of the oxide semiconductor layer is considered to be easily formed into a conductor because hydrogen diffusion from the protective film concentrates.

  Although not shown in Tables 1 and 2, the electrical resistivity of the oxide semiconductor layer of the present invention is 10 to 20 Ωcm after pre-annealing at 350 ° C. for 1 hour in the atmosphere. On the other hand, the pattern edge of the oxide semiconductor of the thin film transistor cannot be directly measured, but the oxide semiconductor layer of the present invention is found to be a conductor film of 0.1 Ωcm or less when hydrogen diffusion is promoted. Yes. On the other hand, the reason why the TFT of FIGS. 5 and 6 showing the conventional structure could not realize high mobility at all is that hydrogen diffusion from the protective film to the end of the oxide semiconductor layer was not sufficient.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Gate electrode 3 Gate insulating film 4 Oxide semiconductor layer 5 Source-drain electrode 6 Protective film 7 Contact hole 8 Through hole 9 Etch stop layer D Thermal image observation region

Claims (7)

A thin film transistor having at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and a protective film for protecting the source-drain electrode in this order on a substrate,
The oxide semiconductor layer includes a semiconductor region and a conductor region, and the conductor region exists at least in one or more of a channel region and an end portion of the oxide semiconductor layer. A thin film transistor having at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and a protective film for protecting the source-drain electrode in this order on a substrate,
When viewed from the top surface of the substrate, the end portion x adjacent to the channel region of the oxide semiconductor layer is more than the end portion y of the source-drain electrode adjacent to the channel region and in direct contact with the oxide semiconductor layer. A thin film transistor which is located outside and has a shortest distance d between the end x and the end y of 3 μm or more and 100 μm or less. The oxide semiconductor layer is made of an oxide composed of In, Ga, Sn, and O, and the atomic ratio of each metal element satisfies all of the following formulas (1) to (3). The thin film transistor according to claim 1, wherein the film contains SiNx.
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3) The thin film transistor according to claim 3, wherein the oxide semiconductor layer has an atomic ratio of In and Ga that satisfies the following formula (4).
0.60 ≦ In / (In + Ga) ≦ 0.75 (4)   The thin film transistor according to claim 1, wherein at least a part of the oxide semiconductor layer has an amorphous structure. A method for producing the thin film transistor according to claim 1,
Forming an oxide semiconductor layer by sputtering under a gas pressure of 1 to 5 mTorr;
A step of heat-treating at a temperature of 200 ° C. or higher after forming the protective film;
A method for producing a thin film transistor, comprising: It is a sputtering target used for formation of the oxide semiconductor layer of the thin-film transistor in any one of Claims 1-5, Comprising: It has In, Ga, Sn, and O, and following formula (1)-(3) A sputtering target characterized by satisfying all of the above.
0.30 ≦ In / (In + Ga + Sn) ≦ 0.50 (1)
0.20 ≦ Ga / (In + Ga + Sn) ≦ 0.30 (2)
0.25 ≦ Sn / (In + Ga + Sn) ≦ 0.45 (3)