CN209641659U - A kind of board structure promoting TFT stability - Google Patents
A kind of board structure promoting TFT stability Download PDFInfo
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- CN209641659U CN209641659U CN201920327768.8U CN201920327768U CN209641659U CN 209641659 U CN209641659 U CN 209641659U CN 201920327768 U CN201920327768 U CN 201920327768U CN 209641659 U CN209641659 U CN 209641659U
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- 230000001737 promoting effect Effects 0.000 title claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 239
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- 239000002184 metal Substances 0.000 claims abstract description 62
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 18
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 9
- 230000000717 retained effect Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910004205 SiNX Inorganic materials 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 8
- 238000000137 annealing Methods 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 5
- 238000012546 transfer Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000012545 processing Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 description 1
- 101100214488 Solanum lycopersicum TFT2 gene Proteins 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000010420 art technique Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- Thin Film Transistor (AREA)
Abstract
The utility model relates to field of display technology, more particularly to a kind of board structure for promoting TFT stability, including the gate insulating layer sequentially formed on substrate and the substrate, gate metal layer, interlayer insulating film, source-drain electrode metal layer and IGZO active layer, the gate insulating layer includes SIOx insulating layer and SINx insulating layer double-layer structure, the SIOx insulating layer is covered on substrate, the SINx insulating layer is between SIOx insulating layer and gate metal layer, SINx insulating layer is adapted with the shape size of gate metal layer, the source-drain electrode metal layer forms source electrode and drain electrode, IGZO active layer between the source electrode and drain electrode is channel region.Only retain the SINx insulating layer below gate metal layer in this programme, reduce the accounting of SINx insulating layer, while guaranteeing the dangling bonds repairing effect of semiconductor layer Poly-Si, can be effectively reduced subsequent IGZO active layer, H ion-transfer and then promotes the stability of TFT device to IGZO film layer probability in SiNx in thermal annealing.
Description
Technical field
The utility model relates to field of display technology more particularly to a kind of board structures for promoting TFT stability.
Background technique
IGZO is a kind of amorphous oxides containing indium, gallium and zinc, and carrier mobility is 20-30 times of amorphous silicon, can
To greatly improve TFT to the charge-discharge velocity of pixel electrode, the response speed of pixel is improved, has faster panel refresh frequency
Rate is, it can be achieved that ultrahigh resolution TFT-LCD.
Since IGZO TFT device relative low temperature multi-crystal TFT possesses more superior Ioff, picture element TFT only needs single grid
It can suppress electrical leakage problems, low-power consumption purpose can be reached using lower driving frequency.And LTPS TFT is compared with IGZO TFT
Possessing higher mobility (about 3-10 times big), peripheral driving circuit can design smaller, and it is with the obvious advantage in narrow frame, because
This, industry apple, BOE, JDI and AUO etc. start to put into LTPS+Oxide Hybrid TFT exploitation, realize narrow side
Frame low frequency flexible display technologies.Existing LTPO technology can use NMOS/PMOS the and Oxide semiconductor N MOS of poly-Si
Device configuration display circuit realizes device miniaturization, narrow frame by the high mobility characteristic of LTPS technology, while utilizing oxygen
The low drain stream of compound semiconductor devices and the advantages that bend electrical stability, reach narrow frame, flexibility, low frequency.
Generally there is in GI layers of gate insulator SiNx structure in existing LTPO technology, wherein can contain H ion in SiNx film quality,
H ion easily moves in subsequent thermal annealing process, is conducive to the suspension of repairing semiconductor layer Poly-Si in LTPS TFT
Key improves the electric characteristics of TFT1 (the first transistor).But because the TFT electrology characteristic that active layer is IGZO is special to H ion sensitive,
Threshold voltage vt h drift is easily caused, IGZO TFT2 (second transistor) device fluctuation of service is caused.
Summary of the invention
For this reason, it may be necessary to a kind of board structure for promoting TFT stability be provided, to solve on TFT1 substrate in the prior art
The probability that H ion in SiNx insulating layer is transferred in IGZO active layer in annealing process is larger, causes threshold voltage drift,
The problem of TFT device fluctuation of service.
To achieve the above object, a kind of board structure for promoting TFT stability, including substrate and described are inventor provided
Gate insulating layer, gate metal layer, interlayer insulating film, source-drain electrode metal layer and the IGZO active layer sequentially formed on substrate, institute
Stating gate insulating layer includes SIOx insulating layer and SINx insulating layer double-layer structure, and the SIOx insulating layer is covered on substrate, institute
SINx insulating layer is stated between SIOx insulating layer and gate metal layer, the shape size phase of SINx insulating layer and gate metal layer
Adaptation, the source-drain electrode metal layer form source electrode and drain electrode, and the IGZO active layer between the source electrode and drain electrode is channel region.
As a kind of preferred structure of the utility model, the gate metal layer is located above SINx insulating layer, to grid
Only retain by etch process the SINx insulating layer below gate metal layer when extremely metal layer patterning.
As a kind of preferred structure of the utility model, semiconductor is additionally provided between the substrate and gate metal layer
Layer, the semiconductor layer includes PMOS semiconductor layer and NMOS semiconductor layer.
It further include buffer layer as a kind of preferred structure of the utility model, the buffer layer is located at semiconductor layer and base
Between plate.
It further include insulating layer, flatness layer, passivation layer and pixel electrode, institute as a kind of preferred structure of the utility model
Showing that insulating layer is set to the top of source-drain electrode metal layer and IGZO active layer, the flatness layer is set to the top of insulating layer,
The passivation layer is set to the top of flatness layer, and the pixel electrode is set on passivation layer.
Further include public electrode as a kind of preferred structure of the utility model, the public electrode be located at flatness layer with
Between passivation layer.
It is different from the prior art, above-mentioned technical proposal has the advantages that a kind of promotion TFT stability of the utility model
Board structure improves TFT device by the way that the gate insulating layer is arranged to SIOx insulating layer and SINx insulating layer double-layer structure
The insulation performance of part and pressure-resistant performance, while by the SINx insulating layer between SIOx insulating layer and gate metal layer,
SINx insulating layer is adapted with the shape size of gate metal layer, by such structure setting, is only retained below gate metal layer
SINx insulating layer, reduce the accounting of SINx insulating layer, guarantee semiconductor layer Poly-Si dangling bonds repairing effect it is same
When, improve the first transistor electric characteristics while, can be effectively reduced subsequent IGZO active layer in thermal annealing in SiNx H from
Son is transferred to IGZO film layer probability, and then promotes the stability of IGZO second transistor.
Detailed description of the invention
Fig. 1 is a kind of schematic cross-sectional view for one embodiment of board structure for promoting TFT stability of the utility model；
Fig. 2 is a kind of one embodiment part processing procedure schematic diagram of board structure for promoting TFT stability of the utility model；
Fig. 3 is a kind of one embodiment part processing procedure schematic diagram of board structure for promoting TFT stability of the utility model.
Description of symbols:
1, substrate；
21, SIOx insulating layer；22, SINx insulating layer；
3, gate metal layer；
4, interlayer insulating film；
5, source-drain electrode metal layer；
6, IGZO active layer；
71, PMOS semiconductor layer；72, NMOS semiconductor layer；
8, buffer layer；
9, insulating layer；
10, flatness layer；
11, passivation layer；
12, pixel electrode；
13, public electrode；
14, photoresist.
Specific embodiment
Technology contents, construction feature, the objects and the effects for detailed description technical solution, below in conjunction with specific reality
It applies example and attached drawing is cooperated to be explained in detail.
1 to Fig. 3 is please referred to, the utility model discloses a kind of board structures for promoting TFT stability, including 1 He of substrate
Gate insulating layer, gate metal layer (M1) 3, the interlayer insulating film (ILD) 4, source-drain electrode metal layer sequentially formed on the substrate 1
(SD) 5 and IGZO active layer 6, the gate insulating layer includes 22 double-layer structure of SIOx insulating layer 21 and SINx insulating layer, described
SIOx insulating layer 21 is covered on substrate 1, the SINx insulating layer 22 be located at SIOx insulating layer 21 and gate metal layer (M1) 3 it
Between, SINx insulating layer 22 is adapted with the shape size of gate metal layer (M1) 3, and the source-drain electrode metal layer (SD) 5 forms source
Pole and drain electrode, the IGZO active layer 6 between the source electrode and drain electrode are channel region.Main body of the substrate 1 as TFT device
Structure ultimately forms TFT device by corresponding manufacture craft to deposit different film layers on substrate 1.The IGZO is active
Layer 6 is the film layer made of the amorphous oxides containing indium, gallium and zinc, and carrier mobility is very fast.IGZO active layer 6 by
Grid voltage control generates inversion layer, as conducting channel.In the present invention, the source-drain electrode metal layer (SD) 5 wraps
The drain that the source electrode and drain metal layer for including source metal formation are formed, is used as by IGZO active layer 6 leads therebetween
Electric channel is connected in series, to carry out the high speed migration of electronics.
In the present embodiment, the gate insulating layer is the bilayer formed by SIOx insulating layer 21 and SINx insulating layer 22
Insulation system, top gate (top gate type) structure very in LTPS TFT technology, the insulation performance and pressure resistance of TFT device
Performance all has great promotion.The SINx insulating layer 22 is located at SIOx insulating layer 21 and gate metal layer (M1) 3 simultaneously
Between, and guarantee that SINx insulating layer 22 and the shape size of gate metal layer (M1) 3 are adapted, by such structure setting,
The SINx insulating layer 22 for only retaining 3 lower section gate metal layer (M1), reduces the accounting of SINx insulating layer 22, is guaranteeing semiconductor
While the dangling bonds repairing effect of layer Poly-Si, subsequent IGZO active layer 6 H in SiNx in thermal annealing can be effectively reduced
Ion-transfer promotes the stability of TFT device to IGZO film layer probability.
Such as Fig. 1 and as shown in Fig. 2, a kind of preferred embodiment as the utility model, the gate metal layer (M1) 3
Above SINx insulating layer 22, gate metal layer is only retained by etch process when patterning to gate metal layer (M1) 3
(M1) the SINx insulating layer 22 of 3 lower sections.In actual production process, need to produce using metal mask plate (MASK) vapor deposition
PR figure, is then placed in gate metal layer (M1) 3, passes through by the 3 pattern P R figure of gate metal layer (M1) for needing B to protect
Etching (etch) technique gets rid of the gate metal layer (M1) 3 and SINx insulating layer 22 of no protection zone PR, thus to obtain grid
Pole metal layer (M1) 3 and SINx insulating layer 22 compatible with its shape size, therefore the H ion in SINx insulating layer 22 occurs
The blocking of transfer meeting upper gate metal layer (M1) 3, and SiNx declines to a great extent in entire 1 structure inner area accounting of substrate, effectively
The subsequent IGZO active layer 6 that reduces H atom is migrated to the probability of IGZO active layer 6 in SiNx film in TFT annealing process, rise
To the effect for promoting TFT device stability.
In embodiment as shown in Figure 1, as a kind of preferred embodiment of the utility model, the substrate 1 and grid gold
Belong to and be additionally provided with semiconductor layer between layer (M1) 3, the semiconductor layer includes PMOS semiconductor layer 71 and NMOS semiconductor layer 72.
The PMOS semiconductor layer 71, a gate metal layer (M1) 3 and a source-drain electrode metal layer are located at PMOS structural region；The NMOS
Semiconductor layer 72, a gate metal layer (M1) 3 and a source-drain electrode metal layer are located in NMOS structural region.In cmos circuit structure
Middle PMOS area is LTPS TFT structure, i.e., prepares PMOS semiconductor layer 71 using p-type doped polycrystalline silicon materials, and NMOS area is
Oxide TFT structure prepares NMOS semiconductor layer 72 using oxide material, to form cmos circuit structure.
It please refers in embodiment shown in FIG. 1, further includes buffer layer 8, the buffer layer 8 is located at semiconductor layer and substrate 1
Between.The setting of the buffer layer 8 can understand to avoid semiconductor layer directly and the contact of underlay substrate 1 causes characteristic to be deteriorated.
As shown in Figure 1, further including insulating layer (PV) 9, flatness layer (OC) 10, passivation layer in certain preferred embodiments
(VH) 11 and pixel electrode (PE) 12, the insulating layer (PV) 9 be set to source-drain electrode metal layer (SD) 5 and IGZO active layer 6
Top, the flatness layer (OC) 10 is set to the top of insulating layer (PV) 9, and the passivation layer (VH) 11 is set to flatness layer
(OC) 10 top, the pixel electrode (PE) 12 are set on passivation layer (VH) 11.Specifically, further including public electrode (BC)
13, the public electrode (BC) 13 is between flatness layer (OC) 10 and passivation layer (VH) 11.The public electrode (BC) 13 with
The connection of touch-control cabling, the transmitting for touching signals.
In the particular embodiment, it is described in the utility model promoted TFT stability board structure by the following method
It is made:
Partial key processing procedure please refers to shown in Fig. 2 and Fig. 3
Step 1: being sequentially depositing buffer layer 8 and semiconductor layer on substrate 1, and form PMOS using patterning processes and partly lead
Body layer 71 and NMOS semiconductor layer 72；
Step 2: forming gate insulating layer on step 1 treated substrate 1；Specifically it is sequentially depositing SIOx insulating layer 21
With SINx insulating layer 22；
Step 3: depositing gate metal layer (M1) 3 on the substrate 1 of step 2 processing, carry out light in gate metal layer (M1) 3
It hinders (PR) 14 and is coated with post-exposure (photo), pattern needed for being formed according to mask plate (MASK) design, then to gate metal layer
(M1) 3 (etch) is performed etching, the gate metal layer (M1) 3 without 14 protection zone of photoresist (PR) and SiNx film layer is removed,
Can accomplish the SINx insulating layer 22 for retaining the lower section gate metal layer (M1) 3 thus can get gate metal layer (M1) 3 and
SiNx film layer forms pattern；
Step 4: interlayer insulating film (ILD) 4 is formed on step 3 treated substrate 1；
Step 5: IGZO film being deposited using PVD method on the substrate 1 of step 4 processing, after the coating of photoresist (PR) 14
It anneals (depo), exposure (photo), etch (etch) and removing (stripe) process；Ultimately forming required has IGZO active
The pattern of layer (SE) 6；
Step 6: on step 5 treated substrate 1 after carrying out photoresist 14 (PR) coating to interlayer insulating film (ILD) 4,
(photo), etching (etch) and removing (stripe) process are exposed, realizes the via hole of LTPS TFT source drain region.
It finally completes, source-drain electrode metal layer (SD) is to the processing procedure of pixel electrode (PE) 12, this section of processing procedure is compared with LTPO skill
Art technique, this will not be repeated here.
It should be noted that being not intended to limit although the various embodiments described above have been described herein
The scope of patent protection of the utility model.Therefore, based on the innovative idea of the utility model, embodiment described herein is carried out
Change and modification or equivalent structure or equivalent flow shift made based on the specification and figures of the utility model, directly
Or above technical scheme is used in other related technical areas indirectly, it is included in the protection model of the utility model patent
Within enclosing.
Claims (6)
1. a kind of board structure for promoting TFT stability, which is characterized in that including the grid sequentially formed on substrate and the substrate
Pole insulating layer, gate metal layer, interlayer insulating film, source-drain electrode metal layer and IGZO active layer, the gate insulating layer include
SIOx insulating layer and SINx insulating layer double-layer structure, the SIOx insulating layer are covered on substrate, and the SINx insulating layer is located at
Between SIOx insulating layer and gate metal layer, SINx insulating layer is adapted with the shape size of gate metal layer, the source-drain electrode
Metal layer forms source electrode and drain electrode, and the IGZO active layer between the source electrode and drain electrode is channel region.
2. the board structure according to claim 1 for promoting TFT stability, which is characterized in that the gate metal layer position
Above SINx insulating layer, the SINx below gate metal layer is only retained by etch process when to gate metal pattern layers
Insulating layer.
3. the board structure according to claim 2 for promoting TFT stability, which is characterized in that the substrate and grid gold
Belong to and be additionally provided with semiconductor layer between layer, the semiconductor layer includes PMOS semiconductor layer and NMOS semiconductor layer.
4. the board structure according to claim 3 for promoting TFT stability, which is characterized in that it further include buffer layer, it is described
Buffer layer is between semiconductor layer and substrate.
5. the board structure according to claim 1 for promoting TFT stability, which is characterized in that further include insulating layer, flat
Layer, passivation layer and pixel electrode, shown insulating layer is set to the top of source-drain electrode metal layer and IGZO active layer, described flat
Layer is set to the top of insulating layer, and the passivation layer is set to the top of flatness layer, and the pixel electrode is set on passivation layer.
6. the board structure according to claim 5 for promoting TFT stability, which is characterized in that it further include public electrode, institute
Public electrode is stated between flatness layer and passivation layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920327768.8U CN209641659U (en) | 2019-03-15 | 2019-03-15 | A kind of board structure promoting TFT stability |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920327768.8U CN209641659U (en) | 2019-03-15 | 2019-03-15 | A kind of board structure promoting TFT stability |
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| Publication Number | Publication Date |
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| CN209641659U true CN209641659U (en) | 2019-11-15 |
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| Country | Link |
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