CN107808826A - A kind of preparation method of bottom emitting top-gated self-aligned thin film transistor - Google Patents

Abstract

The invention relates to the field of display technology, and discloses a method for preparing a bottom-emission top-gate self-aligned thin film transistor, which includes sequentially forming a light-shielding layer, a first buffer layer covering the light-shielding layer, and depositing an active layer on a base substrate, and also includes : Deposit the first metal layer on the active layer, pattern the active layer and the first metal layer with a two-tone mask to form an active island and a metal buffer layer through a patterning process; form a source drain on the metal buffer layer It does not need to conduct the active layer, but also effectively reduces the parasitic resistance between the channel region and the source and drain electrodes, does not increase the number of masks, simplifies the process of the device, and saves production costs , the metal buffer layer and the light-shielding layer cooperate to effectively isolate the influence of light on the channel region and LDD region, improve the light stability of the top gate device, avoid problems such as afterimages during display, and improve process efficiency and product yield.

Description

A method for fabricating a bottom-emitting top-gate self-aligned thin film transistor

technical field

The invention relates to the field of display technology, in particular to a method for preparing a bottom-emitting top-gate self-aligned thin film transistor.

Background technique

In the field of semiconductor technology, compared with traditional silicon-based thin film transistors (Si-TFTs), metal oxide thin film transistors represented by IGZO (indium gallium zinc oxide) TFTs (thin film transistors) are characterized by their high mobility, manufacturing process The advantages of simplicity, low cost, and large-area uniformity have been developed rapidly, and have become key devices for driving OLED (organic light-emitting diode) display panels.

At present, in order to realize the characteristic of small parasitic capacitance required for higher-resolution OLED display, IGZO TFT adopts a top-gate self-aligned structure, but the main problem is how to reduce the distance between the channel region and the source-drain electrode. Parasitic resistance, as shown in Figure 1, the parasitic resistance R _P between the channel region A and the source and drain electrodes 01 includes the resistance R _LDD of the LDD region (lowly doped drain region) B and the source and drain electrodes 01 and the active layer 02 contact resistance R _C ; the second is how to improve the light stability of the top gate device, because the oxide itself is sensitive to light, the electrical characteristics of the oxide material will change under light; in order to reduce the channel region A and For the parasitic resistance between the source and drain electrodes 01, the area where the active layer 02 is in contact with the source and drain electrodes 01 needs to be treated with Ar (argon), He (helium) and other gas plasmas, that is, the process of realizing the conductorization of the active layer, but The process of conducting the active layer has the problems of complex process, low device mobility, and poor stability. In order to improve the light stability of the top-gate device, a layer of light-shielding layer 03 is usually formed on the substrate 04 to block light. role. However, the light-shielding layer 03 cannot completely and effectively isolate the influence of light on the channel region A and the LDD region B, which makes the TFT prone to large threshold voltage drift, which exceeds the compensation range of the compensation circuit, resulting in a series of problems such as afterimages during display. .

Contents of the invention

The invention provides a method for preparing a bottom-emission top-gate self-aligned thin film transistor. The method for preparing a bottom-emission top-gate self-aligned thin film transistor can effectively reduce the channel region and source-drain electrodes while avoiding the conductorization of the active layer. The parasitic resistance simplifies the manufacturing process and improves the efficiency and product yield of the process.

To achieve the above object, the present invention provides the following technical solutions:

A method for preparing a bottom-emitting top-gate self-aligned thin film transistor, comprising sequentially forming a light-shielding layer, a first buffer layer covering the light-shielding layer, and depositing an active layer on a base substrate, and further comprising:

Depositing a first metal layer on the active layer, patterning the active layer and the first metal layer using a two-tone mask to form the active island and the metal buffer layer through a single patterning process;

A source-drain electrode is formed on the metal buffer layer.

In the preparation method of the bottom-emitting top-gate self-aligned thin film transistor, the active layer and the first metal layer are patterned by using a two-tone mask, and the active island and the metal buffer layer can be formed through a single patterning process, wherein the metal The buffer layer is used as the metal contact layer of the LDD region. By forming the source and drain electrodes on the metal buffer layer, the source and drain electrodes can be directly contacted with the active island, thereby eliminating the need to conduct the active layer and avoiding the active layer. The process has the problems of complex process, low device mobility, and poor stability; at this time, the resistance R _LDD of the LDD region can be ignored, and the parasitic resistance R _P between the channel region and the source-drain electrode only includes the source-drain electrode and active The contact resistance R _C between the source layers effectively reduces the parasitic resistance between the channel region and the source-drain electrodes; at the same time, no mask plate is added during the preparation method of the bottom-emitting top-gate self-aligned thin film transistor number, which simplifies the process of the device and saves the production cost; in addition, because the metal buffer layer on the upper layer of the LDD area is made of metal material, it can block the light above the device, and cooperate with the light-shielding layer to effectively isolate the light from the groove. The impact of the channel region and the LDD region improves the light stability of the top gate device and avoids problems such as afterimages during display.

Therefore, the above-mentioned bottom-emitting top-gate self-aligned thin film transistor preparation method can effectively reduce the parasitic resistance of the channel region and the source-drain electrode while avoiding the conductorization of the active layer, simplify the preparation process, and improve the efficiency of the process and the product. yield.

Preferably, the patterning of the active layer and the first metal layer using a two-tone mask plate to form the active island and the metal buffer layer through a patterning process specifically includes:

forming a photoresist layer on the first metal layer;

Exposing and developing the photoresist layer;

etching the active layer and the first metal layer for the first time to form the active island;

The first metal layer is etched a second time to form a metal buffer layer.

Preferably, the first etching adopts a wet etching process, and the second etching process adopts a wet etching process or a dry etching process.

Preferably, the active layer is made of metal oxide material.

Preferably, the metal oxide material is IGZO.

Preferably, the preparation method of the bottom-emitting top-gate self-aligned thin film transistor further includes oxidation treatment of the active layer.

Preferably, the oxidation treatment of the active layer specifically includes performing annealing treatment or ion plasma treatment on the active layer.

Preferably, the forming the source and drain electrodes on the metal buffer layer specifically includes:

sequentially depositing a first insulating layer and a second metal layer on the first buffer layer formed with the active island and the metal buffer layer;

forming a photoresist layer on the second metal layer;

Exposing and developing the photoresist layer;

etching the second metal layer to form a gate electrode;

Afterwards, using the pattern of the gate electrode as a mask, the first insulating layer is etched downward by self-alignment to form a gate insulating layer;

Depositing and patterning an interlayer insulating layer on the first buffer layer to form a contact hole;

A third metal layer is deposited and patterned to form a source-drain electrode, a part of the source-drain electrode is disposed in the contact hole and electrically connected to the metal buffer layer.

Preferably, the third metal layer is made of Mo, Al, Ti, Au, Cu, Hf or Ta.

Preferably, the sequentially forming the light-shielding layer and the first buffer layer on the base substrate specifically includes:

Depositing and patterning a fourth metal layer on the cleaned base substrate to form a light shielding layer;

Depositing a second insulating layer on the base substrate after forming the light shielding layer to prepare the first buffer layer.

Preferably, the fourth metal layer is made of Mo, Al, Ti, Au, Cu, Hf, Ta, AlNd alloy or MoNb alloy.

Preferably, the second insulating layer is made of silicon oxide, silicon nitride or silicon oxynitride.

Description of drawings

1 is a schematic diagram of a parasitic resistance R _P between a channel region and a source-drain electrode in a bottom-emitting top-gate self-aligned thin film transistor provided by the background technology of the present invention;

2 is a schematic diagram of the parasitic resistance R _P between the channel region and the source and drain electrodes in a bottom-emitting top-gate self-aligned thin film transistor provided by the present invention;

3 is a process flow diagram of a method for preparing a bottom-emitting top-gate self-aligned thin film transistor provided by the present invention;

FIG. 4( a )- FIG. 4( f ) are a method for fabricating a bottom-emitting top-gate self-aligned thin film transistor provided by the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

As shown in Figure 2 and Figure 3, a method for preparing a bottom-emitting top-gate self-aligned thin film transistor comprises the following steps:

Step S301, sequentially forming a light-shielding layer 2, a first buffer layer 3 covering the light-shielding layer 2, and depositing an active layer 4 on the base substrate 1;

Step S302, depositing the first metal layer 5 on the active layer 4, patterning the active layer 4 and the first metal layer 5 by using a two-tone mask to form the active island 41 and the metal buffer layer 51 through one patterning process;

Step S303 , forming source and drain electrodes 9 on the metal buffer layer 51 .

In the above-mentioned method for preparing a bottom-emitting top-gate self-aligned thin film transistor, the light-shielding layer 2, the first buffer layer 3 and the active layer 4 are first prepared through step S301 as shown in FIG. 4(a), and then prepared through step S302. The source island 41 and the metal buffer layer 51 use a two-tone mask to pattern the active layer 4 and the first metal layer 5, and the active island 41 and the metal buffer layer 51 can be formed through a single patterning process, wherein the metal buffer layer 51 As the metal contact layer of the LDD region B, the source and drain electrodes 9 are finally formed on the metal buffer layer 51 through step S303 as shown in FIG. The active layer 4 is conductive, which avoids the problems of complex process, low device mobility, and poor stability in the conductive process of the active layer 4; at this time, the resistance R _LDD of the LDD region B can be ignored, and the channel region A The parasitic resistance R _P between the source and drain electrodes 9 only includes the contact resistance R _C between the source and drain electrodes 9 and the active layer 4, effectively reducing the parasitic resistance between the channel region A and the source and drain electrodes 9; At the same time, the number of mask plates is not increased in the whole process of manufacturing the bottom emission top gate self-aligned thin film transistor, which simplifies the process of the device and saves the production cost; in addition, because the metal buffer layer 51 on the upper layer of the LDD region B Composed of metal materials, it can block the light above the device, cooperate with the light-shielding layer 2 to effectively isolate the influence of light on the channel region A and LDD region B, improve the light stability of the top gate device, and avoid the occurrence of Afterimage and other issues.

Therefore, the method for preparing the above-mentioned bottom-emitting top-gate self-aligned thin film transistor can effectively reduce the parasitic resistance between the channel region A and the source-drain electrodes 9 while avoiding the conductorization of the active layer 4, simplify the preparation process, and improve the efficiency of the process. efficiency and product yield.

In addition, the two-tone mask can be a half-tone mask or a gray-tone mask, and the whole process can be carried out in a low temperature environment, so it can be applied in flexible displays, and the equipment is simple, the process is simple, the process cost is low, and the process is controllable. Strong. Therefore, the above method for preparing a bottom-emitting top-gate self-aligned thin film transistor can also be widely used in other fields of thin film transistors.

As shown in Fig. 4 (a), Fig. 4 (b) and Fig. 4 (c), a preferred implementation mode uses a two-tone mask to pattern the active layer 4 and the first metal layer 5 to pass a patterning The process forms the active island 41 and the metal buffer layer 51, specifically including:

forming a photoresist layer 6 on the first metal layer 5;

Exposing and developing the photoresist layer 6;

Etching the active layer 4 and the first metal layer 5 for the first time to form active islands 41;

The active layer 4 is etched for the second time to form the metal buffer layer 51 .

In the preparation method of the above-mentioned bottom-emission top-gate self-aligned thin film transistor, first, a layer of photoresist is coated on the first metal layer 5 to form a photoresist layer 6; The adhesive layer 6 is exposed and developed as shown in Figure 4 (b), forming a photoresist completely reserved part, a photoresist partly reserved part and a photoresist completely removed part, wherein the photoresist completely reserved part corresponds to the formation of metal In the region of the buffer layer 51, the part of the photoresist remaining corresponds to the region where the active island 41 will form a channel, and the thickness of the photoresist in the part of the photoresist remaining part is smaller than the thickness of the photoresist in the part where the photoresist is completely reserved , the photoresist completely removed region corresponds to other regions; the first etching process is performed to remove the active layer 4 and the first metal layer 5 in the photoresist completely removed region to form active islands 41; finally, an ashing process is performed , remove the photoresist in the partially reserved area of the photoresist, perform a second etching process, remove the first metal layer 5 in the partially reserved area of the photoresist, and remove the photoresist in the partially reserved area of the photoresist to form a metal layer The buffer layer 51 is shown in Fig. 4(c). Using the above etching process can effectively reduce or even avoid damage to the active island 41 and the metal buffer layer 51 , improve the characteristics of the oxide thin film transistor, and improve the product yield.

In the above preparation method, a two-tone mask is used to form the metal contact layer and the active island of the LDD region B through a photolithographic etching process, which not only avoids the process of conducting the active layer 4, but also effectively reduces the channel density. The parasitic resistance between the region A and the source-drain electrode 9 simplifies the process of the device and saves the production cost.

Specifically, a wet etching process is used for the first etching process, and a wet etching process or a dry etching process is used for the second etching process.

In the above-mentioned method for preparing a bottom-emitting top-gate self-aligned thin film transistor, the etching process may adopt a wet etching process followed by a dry etching process, or both may adopt a wet etching process, and the following methods may be adopted:

Method 1, the first etching process adopts a wet etching process, and the second etching process adopts a wet etching process;

Method 2, the first etching process adopts a wet etching process, and the second etching process adopts a dry etching process.

Whether the etching process adopts a wet etching process or a dry etching process can be selected according to the specific actual conditions of the bottom emission top gate self-aligned thin film transistor, its preparation method, and preparation environment.

Specifically, the active layer 4 is made of metal oxide material. More specifically, the metal oxide material is IGZO.

In the method for preparing the bottom-emitting top-gate self-aligned thin film transistor, the material of the active layer 4 can be a metal oxide material, can be a semiconductor a-Si, and the active layer 4 can also be made of other metal materials that can meet the requirements. preparation. Wherein, the metal oxide can be IGZO (indium gallium zinc oxide), ZnON (zinc oxynitride) or ITZO (indium tin zinc oxide), and the metal oxide can also be prepared from other metal materials that can meet the requirements.

In order to further improve the characteristics of the oxide thin film transistor, specifically, the method for preparing the bottom emission top gate self-aligned thin film transistor further includes oxidation treatment of the active layer 4 .

More specifically, the oxidation treatment of the active layer 4 includes performing annealing treatment or plasma treatment on the active layer 4 .

In order to further improve the characteristics of the oxide thin film transistor, it is usually necessary to perform multiple annealing or plasma treatment on the oxide thin film transistor to oxidize the active layer 4 or form a protective layer such as SiO ₂ on the oxide thin film transistor. The thin film transistor is protected from the external environment, the characteristics of the oxide thin film transistor are improved, and the product yield rate is improved.

As shown in Fig. 4(d), Fig. 4(e) and Fig. 4(f), a preferred embodiment forms the source and drain electrodes 9 on the metal buffer layer 51, specifically including:

sequentially depositing a first insulating layer 7 and a second metal layer 8 on the first buffer layer 3 formed with the active island 41 and the metal buffer layer 51;

forming a photoresist layer 6 on the second metal layer 8;

Exposing and developing the photoresist layer 6;

Etching the second metal layer 8 to form a gate electrode 81;

Then, using the pattern of the gate electrode 81 as a mask, the first insulating layer 7 is etched downward by self-alignment to form the gate insulating layer 81;

Then depositing and patterning an interlayer insulating layer 6 on the first buffer layer 3 to form a contact hole;

A third metal layer is deposited and patterned to form the source-drain electrodes 9 , a part of the source-drain electrodes 9 is disposed in the contact holes and electrically connected to the metal buffer layer 51 .

In the method for preparing the above-mentioned bottom-emitting top-gate self-aligned thin film transistor, the first insulating layer 7 and the second metal layer 8 are continuously deposited on the first buffer layer 3, and a photoresist is coated on the second metal layer 8 to form The photoresist layer 6 is shown in Figure 4(e), and the pattern of the gate electrode 81 is etched, and then the pattern of the gate electrode 81 is used as a mask to form a gate insulating layer by self-alignment downward etching 81 pattern; then, deposition interlayer insulating layer 6 as shown in Fig. 4 (e), photolithographic patterning interlayer insulating layer 6 is to form contact hole; Then deposit the 3rd metal layer on interlayer insulating layer 6 and pattern to form source and drain electrodes 9;

In the above-mentioned preparation method of the bottom-emitting top-gate self-aligned thin film transistor, the gate electrode 81 and the gate insulating layer 81 are formed in one process to prepare the top-gate self-aligned structure, which can effectively avoid the gap between the gate and the source-drain electrodes. The overlapping area between them suppresses the parasitic capacitance introduced by the overlapping area and the parasitic resistance of the source and drain electrodes 9, which is conducive to reducing parasitic effects and signal delays, improving device performance and product yield, and can be applied in high resolution OLED display.

Specifically, the third metal layer is made of Mo, Al, Ti, Au, Cu, Hf or Ta.

In the preparation method of the above bottom emission top gate self-aligned thin film transistor, the third metal layer can be made of Mo (molybdenum), Al (aluminum), Ti (titanium), Au (gold), Cu (copper), Hf (饸) ), Ta (tantalum), and the third metal layer can also be made of other metal materials that can meet the requirements.

In a preferred embodiment, the light-shielding layer 2 and the first buffer layer 3 are sequentially formed on the base substrate 1, specifically including:

Depositing and patterning a fourth metal layer on the cleaned base substrate 1 to form a light shielding layer 2;

A second insulating layer is deposited on the substrate after the light shielding layer 2 is formed to prepare the first buffer layer 3 .

Specifically, the fourth metal layer is made of Mo, Al, Ti, Au, Cu, Hf, Ta, AlNd alloy or MoNb alloy.

Specifically, the second insulating layer is made of silicon oxide, silicon nitride or silicon oxynitride.

In the method for preparing the above-mentioned bottom-emitting top-gate self-aligned thin film transistor, the base substrate 1 is firstly cleaned by a standard method, and then the fourth metal layer is deposited, wherein the fourth metal layer can be made of Mo (molybdenum), Al ( Aluminum), Ti (titanium), Au (gold), Cu (copper), Hf (饸), Ta (tantalum), AlNd (aluminum neodymium compound) alloy or MoNb (aluminum neodymium compound), The fourth metal layer can also be prepared from other metal materials that can meet the requirements, and then coated with photoresist, and the pattern of the light-shielding layer 2 is photo-etched on the base substrate 1, and then, on the substrate after the light-shielding layer 2 is formed A second insulating layer is deposited. The second insulating layer is made of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The second insulating layer can also be made of other insulating materials that can meet requirements.

Apparently, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (12)

1. a kind of preparation method of bottom emitting top-gated self-aligned thin film transistor, is included on underlay substrate and sequentially forms shading Layer, the first buffer layer of the covering light shield layer and deposition active layer, it is characterised in that also include：

The first metal layer is deposited on active layer, uses active layer described in duotone reticle pattern and the first metal layer with logical Cross a patterning processes and form the active island and the metal buffer layer；

Source-drain electrode is formed on the metal buffer layer.

2. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 1, it is characterised in that described Active layer described in duotone reticle pattern and the first metal layer are used to form the active island by a patterning processes With the metal buffer layer, specifically include:

Photoresist layer is formed on the first metal layer；

The photoresist layer is exposed, developed；

The active layer and the first metal layer are etched to form the active island for the first time；

The first metal layer is etched for the second time to form metal buffer layer.

3. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 2, it is characterised in that described Etching uses wet-etching technique for the first time, and second of etching technics uses wet-etching technique or dry carving technology.

4. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 2, it is characterised in that described Active layer is made up of metal oxide materials.

5. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 4, it is characterised in that described Metal oxide materials are IGZO.

6. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 2, it is characterised in that also wrap Include oxidation processes active layer.

7. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 6, it is characterised in that oxidation Processing active layer specifically include active layer is made annealing treatment or gas ions processing.

8. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 1, it is characterised in that described Source-drain electrode is formed on metal buffer layer, is specifically included：

The first insulating barrier and second metal layer are sequentially depositing in the first buffer layer formed with active island and metal buffer layer；

Photoresist layer is formed in the second metal layer；

The photoresist layer is exposed, developed；

The second metal layer is etched to form gate electrode；

Afterwards using the figure of gate electrode as mask, etch first insulating barrier downwards using autoregistration and form gate insulator Layer；

Afterwards in first buffer layer deposition and graphical interlayer insulating film to form contact hole；

The 3rd metal level is deposited and patterned to form source-drain electrode, the source-drain electrode part is arranged on the contact hole It is interior and electrically connected with the metal buffer layer.

9. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 8, it is characterised in that described 3rd metal level by Mo, Al, Ti, Au, Cu, Hf or, Ta is made.

10. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 1, it is characterised in that institute State and light shield layer and first buffer layer are sequentially formed on underlay substrate, specifically include：

The 4th metal level is deposited and patterned on underlay substrate after cleaning to form light shield layer；

The second insulating barrier is deposited on the substrate after forming light shield layer and prepares first buffer layer.

11. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 10, it is characterised in that institute The 4th metal level is stated to be made up of Mo, Al, Ti, Au, Cu, Hf, Ta, AlNd alloy or MoNb alloys.

12. the preparation method of bottom emitting top-gated self-aligned thin film transistor according to claim 10, it is characterised in that institute The second insulating barrier is stated to be made up of silica, silicon nitride or silicon oxynitride.