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JP2013058637A - Ga2O3-based semiconductor element - Google Patents

Ga2O3-based semiconductor element Download PDF

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JP2013058637A
JP2013058637A JP2011196438A JP2011196438A JP2013058637A JP 2013058637 A JP2013058637 A JP 2013058637A JP 2011196438 A JP2011196438 A JP 2011196438A JP 2011196438 A JP2011196438 A JP 2011196438A JP 2013058637 A JP2013058637 A JP 2013058637A
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crystal film
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contact region
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JP5948581B2 (en
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Kohei Sasaki
公平 佐々木
Masataka Towaki
正高 東脇
Shizuo Fujita
静雄 藤田
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National Institute of Information and Communications Technology
Tamura Corp
Kyoto University NUC
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
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Abstract

【課題】高品質のＧａ２Ｏ３系半導体素子を提供する。
【解決手段】一実施の形態として、α−Ａｌ２Ｏ３基板２上に形成されたα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶（０≦ｘ＜１）からなるｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３と、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３上に形成されたソース電極１２及びドレイン電極１３と、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３中に形成され、ソース電極１２及びドレイン電極１３にそれぞれ接続されたコンタクト領域１４、１５と、α−Ａｌ２Ｏ３基板２のｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３と反対側の面上の、コンタクト領域１４とコンタクト領域１５との間に形成されたゲート電極１１と、を含むＧａ２Ｏ３系ＦＥＴ１０を提供する。
【選択図】図１A high quality Ga 2 O 3 based semiconductor device is provided.
As an embodiment, a p-type α made of α- (Al x Ga 1-x ) 2 O 3 single crystal (0 ≦ x <1) formed on an α-Al 2 O 3 substrate 2. -(Al x Ga 1-x ) 2 O 3 single crystal film 3, source electrode 12 and drain electrode 13 formed on p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3, Contact regions 14 and 15 formed in the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 and connected to the source electrode 12 and the drain electrode 13, respectively, and α-Al 2 O 3 A gate electrode 11 formed between the contact region 14 and the contact region 15 on the surface opposite to the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 of the substrate 2; A Ga 2 O 3 -based FET 10 is provided.
[Selection] Figure 1

Description

本発明は、Ｇａ２Ｏ３系半導体素子に関する。 The present invention relates to a Ga 2 O 3 based semiconductor element.

従来のＧａ２Ｏ３系半導体素子として、α−Ａｌ２Ｏ３（サファイア）基板上に形成されたβ−Ｇａ２Ｏ３結晶膜を用いたβ−Ｇａ２Ｏ３系半導体素子が知られている（例えば、非特許文献１参照）。 As a conventional Ga 2 O 3 based semiconductor devices, α-Al 2 O 3 (sapphire) is β-Ga 2 O 3 based semiconductor device is known which uses a β-Ga 2 O 3 crystal film formed on a substrate (For example, refer nonpatent literature 1).

K. Matsuzaki et al. Appl. Phys. Lett. 88, 092106, 2006.K. Matsuzaki et al. Appl. Phys. Lett. 88, 092106, 2006.

しかしながら、単斜晶系のβ−Ｇａ２Ｏ３結晶膜をコランダム構造のα−Ａｌ２Ｏ３基板上に成長させることは困難であり、高品質なβ−Ｇａ２Ｏ３結晶膜を得ることはできない。このため、α−Ａｌ２Ｏ３基板上のβ−Ｇａ２Ｏ３結晶膜を用いて高品質のＧａ２Ｏ３系半導体素子を形成することは困難である。 However, it is difficult to grow a monoclinic β-Ga 2 O 3 crystal film on a corundum α-Al 2 O 3 substrate, and a high-quality β-Ga 2 O 3 crystal film is obtained. I can't. For this reason, it is difficult to form a high-quality Ga 2 O 3 based semiconductor element using a β-Ga 2 O 3 crystal film on an α-Al 2 O 3 substrate.

したがって、本発明の目的は、高品質のＧａ２Ｏ３系半導体素子を提供することにある。 Accordingly, an object of the present invention is to provide a high quality Ga 2 O 3 based semiconductor element.

本発明の一態様は、上記目的を達成するために、［１］〜［３］のＧａ２Ｏ３系半導体素子を提供する。 In order to achieve the above object, one embodiment of the present invention provides Ga 2 O 3 -based semiconductor elements [1] to [3].

［１］α−Ａｌ２Ｏ３基板上に形成されたα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶（０≦ｘ＜１）からなるα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜と、前記α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜上に形成されたソース電極及びドレイン電極と、前記α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜中に形成され、前記ソース電極及び前記ドレイン電極にそれぞれ接続された第１のコンタクト領域及び第２のコンタクト領域と、前記α−Ａｌ２Ｏ３基板の前記α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜と反対側の面上の、前記第１のコンタクト領域と前記第２のコンタクト領域との間に形成されたゲート電極と、を含むＧａ２Ｏ３系半導体素子。 [1] α-Al 2 O 3 consisting of alpha-formed on a substrate (Al x Ga 1-x) 2 O 3 single crystal (0 ≦ x <1) α- (Al x Ga 1-x) 2 An O 3 single crystal film, a source electrode and a drain electrode formed on the α- (Al x Ga 1-x ) 2 O 3 single crystal film, and the α- (Al x Ga 1-x ) 2 O 3 A first contact region and a second contact region formed in a single crystal film and connected to the source electrode and the drain electrode, respectively, and the α- (Al x Ga 1) of the α-Al 2 O 3 substrate. -x) on the 2 O 3 single crystal film opposite surface, the first Ga 2 O 3 based semiconductor device including a contact region and a gate electrode formed between said second contact region .

［２］前記α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜はｐ型であり、第１のコンタクト領域、及び第２のコンタクト領域はｎ型である、前記［１］に記載のＧａ２Ｏ３系半導体素子。 [2] The α- (Al x Ga 1-x ) 2 O 3 single crystal film is p-type, and the first contact region and the second contact region are n-type, according to the above [1]. Ga 2 O 3 based semiconductor element.

［３］前記α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜は、ドーパントを含まない高抵抗の領域であり、第１のコンタクト領域、及び第２のコンタクト領域はｎ型である、前記［１］に記載のＧａ２Ｏ３系半導体素子。 [3] The α- (Al x Ga 1-x ) 2 O 3 single crystal film is a high-resistance region not containing a dopant, and the first contact region and the second contact region are n-type. The Ga 2 O 3 based semiconductor device according to [1].

本発明によれば、高品質のＧａ２Ｏ３系半導体素子を提供することができる。 According to the present invention, it is possible to provide a high quality Ga 2 O 3 system semiconductor element.

図１は、第１の実施の形態に係るＧａ２Ｏ３系ＦＥＴの断面図である。FIG. 1 is a cross-sectional view of a Ga 2 O 3 -based FET according to the first embodiment. 図２は、α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜の形成に用いられるＭＢＥ装置の一例の構成図である。FIG. 2 is a configuration diagram of an example of an MBE apparatus used for forming an α- (Al x Ga 1-x ) 2 O 3 single crystal film. 図３は、第２の実施の形態に係るＧａ２Ｏ３系ＦＥＴの断面図である。FIG. 3 is a cross-sectional view of a Ga 2 O 3 -based FET according to the second embodiment.

本発明の実施の形態によれば、ホモエピタキシャル成長法を用いて高品質なα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜をα−Ａｌ２Ｏ３基板上に形成し、その高品質のα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜を用いて、高品質のＧａ２Ｏ３系半導体素子を形成することができる。以下、その実施の形態の例について詳細に説明する。 According to the embodiment of the present invention, a high-quality α- (Al x Ga 1-x ) 2 O 3 single crystal film is formed on an α-Al 2 O 3 substrate using a homoepitaxial growth method. A high-quality Ga 2 O 3 based semiconductor element can be formed using a quality α- (Al x Ga 1-x ) 2 O 3 single crystal film. Hereinafter, an example of the embodiment will be described in detail.

〔第１の実施の形態〕
第１の実施の形態では、Ｇａ２Ｏ３系半導体素子としてのＧａ２Ｏ３系ＦＥＴ（Field Effect Transistor）について説明する。 [First Embodiment]
In the first embodiment, it will be described Ga 2 O 3 system Ga 2 O 3 based FET as a semiconductor device (Field Effect Transistor).

（Ｇａ２Ｏ３系半導体素子の構成）
図１は、第１の実施の形態に係るＧａ２Ｏ３系ＦＥＴの断面図である。Ｇａ２Ｏ３系ＦＥＴ１０は、α−Ａｌ２Ｏ３基板２上に形成されたｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３と、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３上に形成されたソース電極１２及びドレイン電極１３と、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３中にソース電極１２及びドレイン電極１３の下にそれぞれ形成されたコンタクト領域１４、１５と、α−Ａｌ２Ｏ３基板２のｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３と反対側の面上の、コンタクト領域１４とコンタクト領域１５との間に形成されたゲート電極１１とを含む。 (Configuration of Ga 2 O 3 based semiconductor element)
FIG. 1 is a cross-sectional view of a Ga 2 O 3 -based FET according to the first embodiment. The Ga 2 O 3 -based FET 10 includes a p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 formed on the α-Al 2 O 3 substrate 2 and a p-type α- (Al x Ga). The source electrode 12 and the drain electrode 13 formed on the 1-x ) 2 O 3 single crystal film 3 and the source electrode 12 and the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 Contact regions 14 and 15 respectively formed under the drain electrode 13 and a surface opposite to the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 of the α-Al 2 O 3 substrate 2 The gate electrode 11 formed between the contact region 14 and the contact region 15 is included.

Ｇａ２Ｏ３系ＦＥＴ１０は、ノーマリーオフ型のトランジスタとして機能する。ゲート電極１１に閾値以上の電圧を印加すると、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３のα−Ａｌ２Ｏ３基板２との界面近傍にチャネルが形成され、ソース電極１２からドレイン電極１３へ電流が流れるようになる。このとき、α−Ａｌ２Ｏ３基板２はゲート絶縁膜として機能する。 The Ga 2 O 3 type FET 10 functions as a normally-off type transistor. When a voltage higher than the threshold value is applied to the gate electrode 11, a channel is formed in the vicinity of the interface of the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 with the α-Al 2 O 3 substrate 2, A current flows from the source electrode 12 to the drain electrode 13. At this time, the α-Al 2 O 3 substrate 2 functions as a gate insulating film.

α−Ａｌ２Ｏ３基板２は、α−Ａｌ２Ｏ３単結晶からなる絶縁性の基板であり、０．１μｍ以上、５００μｍ以下の厚さを有することが好ましい。０．１μｍよりも薄い場合は、ゲートリークが生じるおそれがあり、５００μｍよりも厚い場合は、閾値電圧が大きくなりすぎるためである。 The α-Al 2 O 3 substrate 2 is an insulating substrate made of α-Al 2 O 3 single crystal, and preferably has a thickness of 0.1 μm or more and 500 μm or less. If it is thinner than 0.1 μm, gate leakage may occur, and if it is thicker than 500 μm, the threshold voltage becomes too large.

ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３は、Ｍｇ、Ｈ、Ｌｉ、Ｎａ、Ｋ、Ｒｂ、Ｃｓ、Ｆｒ、Ｂｅ、Ｃａ、Ｓｒ、Ｂａ、Ｒａ、Ｍｎ、Ｆｅ、Ｃｏ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｇ、Ａｕ、Ｚｎ、Ｃｄ、Ｈｇ、Ｔｌ、Ｐｂ、Ｎ、Ｐ等のｐ型ドーパントを含むα−（ＡｌｘＧａ１−ｘ）２Ｏ３（０≦ｘ＜１）の単結晶膜である。ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３は、例えば、１×１０１５／ｃｍ３以上、１×１０１９／ｃｍ３以下の濃度のｐ型ドーパントを含む。また、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３の厚さは、例えば、０．０１〜１０μｍである。 The p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 is composed of Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, and Fe. Α- (Al x Ga 1-x ) 2 O 3 (0 ≦ x) containing p-type dopants such as Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Tl, Pb, N, and P <1) Single crystal film. The p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 includes, for example, a p-type dopant having a concentration of 1 × 10 15 / cm 3 or more and 1 × 10 19 / cm 3 or less. The thickness of the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 is, for example, 0.01 to 10 μm.

ゲート電極１１、ソース電極１２、及びドレイン電極１３は、例えば、Ａｕ、Ａｌ、Ｔｉ、Ｓｎ、Ｇｅ、Ｉｎ、Ｎｉ、Ｃｏ、Ｐｔ、Ｗ、Ｍｏ、Ｃｒ、Ｃｕ、Ｐｂ等の金属、これらの金属のうちの２つ以上を含む合金、又はＩＴＯ等の導電性化合物からなる。また、ゲート電極２１は、異なる２つの金属からなる２層構造、例えばＡｌ／Ｔｉ、Ａｕ／Ｎｉ、Ａｕ／Ｃｏ、を有してもよい。   The gate electrode 11, the source electrode 12, and the drain electrode 13 are, for example, metals such as Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, and Pb, and these metals. It consists of conductive compounds, such as an alloy containing 2 or more of these, or ITO. The gate electrode 21 may have a two-layer structure made of two different metals, for example, Al / Ti, Au / Ni, Au / Co.

コンタクト領域１４、１５は、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３中に形成されたｎ型ドーパントの濃度が高い領域であり、それぞれソース電極１２及びドレイン領域１３が接続される。ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３中のα−Ａｌ２Ｏ３基板２との界面近傍にチャネルを形成するためには、コンタクト領域１４、１５はこの界面と交わることが好ましい。その場合、コンタクト領域１４、１５の底部がα−Ａｌ２Ｏ３基板２中に存在する。 The contact regions 14 and 15 are regions in which the concentration of n-type dopant formed in the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 is high, and the source electrode 12 and the drain region 13, respectively. Is connected. In order to form a channel near the interface with the α-Al 2 O 3 substrate 2 in the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3, the contact regions 14 and 15 are formed at this interface. It is preferable to cross. In that case, the bottoms of the contact regions 14 and 15 exist in the α-Al 2 O 3 substrate 2.

コンタクト領域１４、１５は、例えば、１×１０１８／ｃｍ３以上、５×１０１９／ｃｍ３以下の濃度のｎ型ドーパントを含む。 The contact regions 14 and 15 include, for example, an n-type dopant having a concentration of 1 × 10 18 / cm 3 or more and 5 × 10 19 / cm 3 or less.

（Ｇａ２Ｏ３系ＦＥＴの製造方法）
α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜の製造方法の一例として、分子線エピタキシー（ＭＢＥ；Molecular Beam Epitaxy）法による方法を以下に説明する。ＭＢＥ法は、単体あるいは化合物の固体をセルと呼ばれる蒸発源で加熱し、加熱により生成された蒸気を分子線として基板表面に供給する結晶成長方法である。 (Manufacturing method of Ga 2 O 3 system FET)
As an example of a method for producing an α- (Al x Ga 1-x ) 2 O 3 single crystal film, a method using a molecular beam epitaxy (MBE) method will be described below. The MBE method is a crystal growth method in which a simple substance or a compound solid is heated by an evaporation source called a cell, and vapor generated by heating is supplied as a molecular beam to a substrate surface.

図２は、α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜の形成に用いられるＭＢＥ装置の一例の構成図である。このＭＢＥ装置１００は、真空槽１０７と、この真空槽１０７内に支持され、α−Ａｌ２Ｏ３基板２を保持する基板ホルダ１０１と、基板ホルダ１０１に保持されたα−Ａｌ２Ｏ３基板２を加熱するための加熱装置１０２と、薄膜を構成する原子又は分子ごとに設けられた複数のセル１０３（１０３ａ、１０３ｂ、１０３ｃ）と、複数のセル１０３を加熱するためのヒータ１０４（１０４ａ、１０４ｂ、１０４ｃ）と、真空槽１０７内に酸素系ガスを供給するガス供給パイプ１０５と、真空槽１０７内の空気を排出するための真空ポンプ１０６とを備えている。基板ホルダ１０１は、シャフト１１０を介して図示しないモータにより回転可能に構成されている。 FIG. 2 is a configuration diagram of an example of an MBE apparatus used for forming an α- (Al x Ga 1-x ) 2 O 3 single crystal film. The MBE apparatus 100 includes a vacuum chamber 107, is supported on the vacuum chamber 107, α-Al 2 O 3 and the substrate holder 101 for holding a substrate 2, α-Al 2 O 3 substrate held on the substrate holder 101 Heating device 102 for heating 2, a plurality of cells 103 (103 a, 103 b, 103 c) provided for each atom or molecule constituting the thin film, and a heater 104 (104 a, 104 a, 104) for heating the plurality of cells 103 104b, 104c), a gas supply pipe 105 for supplying an oxygen-based gas into the vacuum chamber 107, and a vacuum pump 106 for discharging the air in the vacuum chamber 107. The substrate holder 101 is configured to be rotatable by a motor (not shown) via a shaft 110.

第１のセル１０３ａには、Ｇａ粉末等のα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜のＧａ原料が充填されている。この粉末のＧａの純度は、６Ｎ以上であることが望ましい。第２のセル１０３ｂには、ドナーとしてドーピングされるｐ型ドーパントの原料の粉末が充填されている。第３のセル１０３ｃには、Ａｌ粉末等のα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜のＡｌ原料が充填されている。第１のセル１０３ａ、第２のセル１０３ｂ、及び第３のセル１０３ｃの開口部にはシャッターが設けられている。 The first cell 103a is filled with a Ga raw material of an α- (Al x Ga 1-x ) 2 O 3 single crystal film such as Ga powder. As for the purity of Ga of this powder, it is desirable that it is 6N or more. The second cell 103b is filled with a p-type dopant raw material powder to be doped as a donor. The third cell 103c is filled with an Al raw material of an α- (Al x Ga 1-x ) 2 O 3 single crystal film such as Al powder. Shutters are provided in openings of the first cell 103a, the second cell 103b, and the third cell 103c.

まず、α−Ａｌ２Ｏ３基板２をＭＢＥ装置１００の基板ホルダ１０１に取り付ける。次に、真空ポンプ１０６を作動させ、真空槽１０７内の気圧を１０−１０Ｔｏｒｒ程度まで減圧する。そして、加熱装置１０２によってα−Ａｌ２Ｏ３基板２を加熱する。なお、α−Ａｌ２Ｏ３基板２の加熱は、加熱装置１０２の黒鉛ヒータ等の発熱源の輻射熱が基板ホルダ１０１を介してα−Ａｌ２Ｏ３基板２に熱伝導することにより行われる。 First, the α-Al 2 O 3 substrate 2 is attached to the substrate holder 101 of the MBE apparatus 100. Next, the vacuum pump 106 is operated, and the atmospheric pressure in the vacuum chamber 107 is reduced to about 10 −10 Torr. Then, the α-Al 2 O 3 substrate 2 is heated by the heating device 102. The heating of the α-Al 2 O 3 substrate 2 is performed by radiant heat of the heat source of the graphite heater of the heating device 102 is thermally conducted to the alpha-Al 2 O 3 substrate 2 through the substrate holder 101.

α−Ａｌ２Ｏ３基板２が所定の温度に加熱された後、ガス供給パイプ１０５から真空槽１０７内に、酸素系ガスを供給する。 After the α-Al 2 O 3 substrate 2 is heated to a predetermined temperature, an oxygen-based gas is supplied from the gas supply pipe 105 into the vacuum chamber 107.

真空槽１０７内に酸素系ガスを供給した後、真空槽１０７内のガス圧が安定するのに必要な時間（例えば５分間）経過後、基板ホルダ１０１を回転させながら第１のヒータ１０４ａ、第２のヒータ１０４ｂ、及び第３のヒータ１０４ｃにより第１のセル１０３ａ、第２のセル１０３ｂ、及び第２のセル１０３ｃを加熱し、Ｇａ、Ａｌ、ｐ型ドーパントを蒸発させて分子線としてα−Ａｌ２Ｏ３基板２の表面に照射する。 After supplying the oxygen-based gas into the vacuum chamber 107, after the time necessary for the gas pressure in the vacuum chamber 107 to stabilize (for example, 5 minutes) has elapsed, the first heater 104a and the first heater 104a are rotated while the substrate holder 101 is rotated. The first cell 103a, the second cell 103b, and the second cell 103c are heated by the second heater 104b and the third heater 104c, and Ga, Al, and p-type dopants are evaporated to form α- Irradiate the surface of the Al 2 O 3 substrate 2.

これにより、α−Ａｌ２Ｏ３基板２の主面上にα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶がＭｇ等のｐ型ドーパントを添加されながらエピタキシャル成長し、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３が形成される。なお、Ｍｇ以外のｐ型ドーパントとして、Ｇａ又はＡｌサイトを置換する場合は、Ｈ、Ｌｉ、Ｎａ、Ｋ、Ｒｂ、Ｃｓ、Ｆｒ、Ｂｅ、Ｃａ、Ｓｒ、Ｂａ、Ｒａ、Ｍｎ、Ｆｅ、Ｃｏ、Ｎｉ、Ｐｄ、Ｃｕ、Ａｇ、Ａｕ、Ｚｎ、Ｃｄ、Ｈｇ、Ｔｌ、又はＰｂ等を用いることができ、酸素サイトを置換する場合は、Ｎ又はＰ等を用いることができる。ｐ型ドーパントの添加濃度は、第２のセル１０３ｂの温度により制御することができる。 Thereby, the α- (Al x Ga 1-x ) 2 O 3 single crystal is epitaxially grown on the main surface of the α-Al 2 O 3 substrate 2 while adding a p-type dopant such as Mg, and the p-type α- ( The Al x Ga 1-x ) 2 O 3 single crystal film 3 is formed. As a p-type dopant other than Mg, when replacing Ga or Al sites, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Tl, or Pb can be used, and N or P can be used when substituting the oxygen site. The addition concentration of the p-type dopant can be controlled by the temperature of the second cell 103b.

なお、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３は、ＰＬＤ（Pulsed Laser Deposition）法、ＣＶＤ（Chemical Vapor Deposition）法等により形成されてもよい。 The p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 may be formed by a PLD (Pulsed Laser Deposition) method, a CVD (Chemical Vapor Deposition) method, or the like.

次に、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３内にＳｎ等のｎ型ドーパントをイオン注入することにより、コンタクト領域１４、１５を形成する。なお、注入するイオンはＳｎに限られず、例えば、Ｇａ又はＡｌサイトを置換する場合は、Ｔｉ、ＺＲ、Ｈｆ、Ｖ、Ｎｂ、Ｔａ、Ｍｏ、Ｗ、Ｒｕ、Ｒｈ、Ｉｒ、Ｃ、Ｓｉ、Ｇｅ、Ｐｂ、Ｍｎ、Ａｓ、Ｓｂ、又はＢｉを用いることができる。また、酸素サイトを置換する場合は、Ｆ、Ｃｌ、Ｂｒ、又はＩを用いることができる。 Next, contact regions 14 and 15 are formed by ion-implanting n-type dopants such as Sn into the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3. The ions to be implanted are not limited to Sn. For example, when replacing Ga or Al sites, Ti, ZR, Hf, V, Nb, Ta, Mo, W, Ru, Rh, Ir, C, Si, Ge , Pb, Mn, As, Sb, or Bi can be used. Further, when substituting the oxygen site, F, Cl, Br, or I can be used.

注入濃度は、例えば、１×１０１８／ｃｍ３以上５×１０１９／ｃｍ３以下である。注入深さは、３０ｎｍ以上であればよい。注入後、注入領域の表面をフッ酸にて１０ｎｍ程度エッチングする。硫酸や硝酸、塩酸などを用いてエッチングしてもよい。その後、窒素雰囲気下で８００℃以上３０ｍｉｎ以上のアニール処理を施し、注入ダメージを回復させる。アニール処理を酸素雰囲気で行う場合は、処理温度を８００℃以上９５０℃以下、処理時間を３０ｍｉｎ以上とすればよい。 The implantation concentration is, for example, 1 × 10 18 / cm 3 or more and 5 × 10 19 / cm 3 or less. The implantation depth may be 30 nm or more. After the implantation, the surface of the implantation region is etched by about 10 nm with hydrofluoric acid. Etching may be performed using sulfuric acid, nitric acid, hydrochloric acid, or the like. Thereafter, annealing treatment is performed at 800 ° C. or more for 30 minutes or more in a nitrogen atmosphere to recover implantation damage. In the case where the annealing treatment is performed in an oxygen atmosphere, the treatment temperature may be 800 ° C. or more and 950 ° C. or less, and the treatment time may be 30 minutes or more.

なお、コンタクト領域１４、１５の形成方法はイオン注入に限られず、熱拡散法を用いてもよい。この場合、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３のコンタクト領域１４、１５を形成したい領域上にＳｎ等の金属を接触させ、熱処理を施すことによりｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３中にＳｎ等のドーパントを拡散させる。 The method for forming the contact regions 14 and 15 is not limited to ion implantation, and a thermal diffusion method may be used. In this case, a metal such as Sn is brought into contact with the region where the contact regions 14 and 15 of the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3 are to be formed, and heat treatment is performed to thereby form the p-type α. A dopant such as Sn is diffused in the — (Al x Ga 1-x ) 2 O 3 single crystal film 3.

その後、ゲート電極１１、ソース電極１２、及びドレイン電極１３を形成する。   Thereafter, the gate electrode 11, the source electrode 12, and the drain electrode 13 are formed.

〔第２の実施の形態〕
第２の実施の形態は、ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３の代わりにアンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜が形成される点において第１の実施の形態と異なる。第１の実施の形態と同様の点については、説明を省略又は簡略化する。 [Second Embodiment]
In the second embodiment, an undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film is formed instead of the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film 3. This is different from the first embodiment. The description of the same points as in the first embodiment will be omitted or simplified.

（Ｇａ２Ｏ３系半導体素子の構成）
図３は、第２の実施の形態に係るＧａ２Ｏ３系ＦＥＴの断面図である。Ｇａ２Ｏ３系ＦＥＴ２０は、α−Ａｌ２Ｏ３基板２上に形成されたアンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜４と、アンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜４上に形成されたソース電極１２及びドレイン電極１３と、アンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜４中にソース電極１２及びドレイン電極１３の下にそれぞれ形成されたコンタクト領域２４、２５と、α−Ａｌ２Ｏ３基板２のアンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜４と反対側の面上の、コンタクト領域２４とコンタクト領域２５との間に形成されたゲート電極１１とを含む。 (Configuration of Ga 2 O 3 based semiconductor element)
FIG. 3 is a cross-sectional view of a Ga 2 O 3 -based FET according to the second embodiment. The Ga 2 O 3 -based FET 20 includes an undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film 4 formed on the α-Al 2 O 3 substrate 2 and an undoped α- (Al x Ga 1-1). x ) The source electrode 12 and the drain electrode 13 formed on the 2 O 3 single crystal film 4, and the source electrode 12 and the drain electrode 13 in the undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film 4. Contact regions 24 and 25 respectively formed underneath, and contacts on the surface opposite to the undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film 4 of the α-Al 2 O 3 substrate 2. Gate electrode 11 formed between region 24 and contact region 25 is included.

Ｇａ２Ｏ３系ＦＥＴ２０は、ノーマリーオフ型のトランジスタとして機能する。ゲート電極１１に閾値以上の電圧を印加すると、アンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜４のα−Ａｌ２Ｏ３基板２との界面近傍にチャネルが形成され、ソース電極１２からドレイン電極１３へ電流が流れるようになる。このとき、α−Ａｌ２Ｏ３基板２はゲート絶縁膜として機能する。 The Ga 2 O 3 type FET 20 functions as a normally-off type transistor. When a voltage higher than the threshold is applied to the gate electrode 11, a channel is formed in the vicinity of the interface between the undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film 4 and the α-Al 2 O 3 substrate 2, and the source A current flows from the electrode 12 to the drain electrode 13. At this time, the α-Al 2 O 3 substrate 2 functions as a gate insulating film.

アンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜４は、ドーパントを含まない高抵抗のα−（ＡｌｘＧａ１−ｘ）２Ｏ３（０≦ｘ＜１）の単結晶膜である。結晶欠陥等により弱い導電性を有する場合もあるが、電気抵抗が十分高いため、ゲート電極１１に電圧を印加することなくソース電極１２からドレイン電極１３へ電流が流れることはない。また、アンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜４の厚さは、例えば、０．０１〜１０μｍである。 The undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film 4 is a single crystal of high resistance α- (Al x Ga 1-x ) 2 O 3 (0 ≦ x <1) that does not contain a dopant. It is a membrane. Although it may have weak conductivity due to crystal defects or the like, since the electric resistance is sufficiently high, no current flows from the source electrode 12 to the drain electrode 13 without applying a voltage to the gate electrode 11. Moreover, the thickness of the undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film 4 is, for example, 0.01 to 10 μm.

アンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜４の形成方法は、例えば、第１の実施の形態のｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜３の形成方法からｐ型ドーパントを注入する工程を省いたものである。 The method of forming the undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film 4 is, for example, the p-type α- (Al x Ga 1-x ) 2 O 3 single crystal film of the first embodiment. The step of injecting the p-type dopant from the forming method 3 is omitted.

ゲート電極１１、ソース電極１２、及びドレイン電極１３は、例えば、Ａｕ、Ａｌ、Ｔｉ、Ｓｎ、Ｇｅ、Ｉｎ、Ｎｉ、Ｃｏ、Ｐｔ、Ｗ、Ｍｏ、Ｃｒ、Ｃｕ、Ｐｂ等の金属、これらの金属のうちの２つ以上を含む合金、又はＩＴＯ等の導電性化合物からなる。また、ゲート電極２１は、異なる２つの金属からなる２層構造、例えばＡｌ／Ｔｉ、Ａｕ／Ｎｉ、Ａｕ／Ｃｏ、を有してもよい。   The gate electrode 11, the source electrode 12, and the drain electrode 13 are, for example, metals such as Au, Al, Ti, Sn, Ge, In, Ni, Co, Pt, W, Mo, Cr, Cu, and Pb, and these metals. It consists of conductive compounds, such as an alloy containing 2 or more of these, or ITO. The gate electrode 21 may have a two-layer structure made of two different metals, for example, Al / Ti, Au / Ni, Au / Co.

コンタクト領域２４、２５は、アンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜４中に形成されたｎ型ドーパントの濃度が高い領域であり、それぞれソース電極１２及びドレイン領域１３が接続される。アンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜４中のα−Ａｌ２Ｏ３基板２との界面近傍にチャネルを形成するためには、コンタクト領域２４、２５はこの界面と交わることが好ましい。その場合、コンタクト領域２４、２５の底部がα−Ａｌ２Ｏ３基板２中に存在する。 The contact regions 24 and 25 are regions where the concentration of the n-type dopant formed in the undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film 4 is high, and the source electrode 12 and the drain region 13 respectively Connected. In order to form a channel in the vicinity of the interface with the α-Al 2 O 3 substrate 2 in the undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film 4, the contact regions 24 and 25 are connected to this interface. It is preferable to cross. In that case, the bottoms of the contact regions 24, 25 exist in the α-Al 2 O 3 substrate 2.

コンタクト領域２４、２５は、例えば、１×１０１８／ｃｍ３以上、５×１０１９／ｃｍ３以下の濃度のｎ型ドーパントを含む。 The contact regions 24 and 25 include, for example, an n-type dopant having a concentration of 1 × 10 18 / cm 3 or more and 5 × 10 19 / cm 3 or less.

（実施の形態の効果）
本実施の形態によれば、ホモエピタキシャル成長法を用いて高品質なα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜を形成し、そのα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜を用いて、高品質のＧａ２Ｏ３系半導体素子を形成することができる。また、これらのＧａ２Ｏ３系半導体素子は、高品質なα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜をチャネル層として用いるため、優れた動作性能を有する。 (Effect of embodiment)
According to the present embodiment, a high-quality α- (Al x Ga 1-x ) 2 O 3 single crystal film is formed using a homoepitaxial growth method, and the α- (Al x Ga 1-x ) 2 O A high-quality Ga 2 O 3 based semiconductor element can be formed using the three single crystal films. In addition, these Ga 2 O 3 based semiconductor elements have excellent operation performance because a high-quality α- (Al x Ga 1-x ) 2 O 3 single crystal film is used as the channel layer.

なお、本発明は、上記実施の形態に限定されず、発明の主旨を逸脱しない範囲内において種々変形実施が可能である。例えば、上記実施の形態において、Ｇａ２Ｏ３系半導体素子をｎ型半導体素子として説明したが、ｐ型半導体素子であってもよい。この場合、各部材の導電型（ｎ型又はｐ型）が全て逆になる。また、発明の主旨を逸脱しない範囲内において上記実施の形態の構成要素を任意に組み合わせることができる。 The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the invention. For example, in the above embodiment, the Ga 2 O 3 based semiconductor element has been described as an n-type semiconductor element, but it may be a p-type semiconductor element. In this case, the conductivity type (n-type or p-type) of each member is reversed. In addition, the constituent elements of the above-described embodiment can be arbitrarily combined without departing from the spirit of the invention.

以上、本発明の実施の形態を説明したが、上記に記載した実施の形態は特許請求の範囲に係る発明を限定するものではない。また、実施の形態の中で説明した特徴の組合せの全てが発明の課題を解決するための手段に必須であるとは限らない点に留意すべきである。   While the embodiments of the present invention have been described above, the embodiments described above do not limit the invention according to the claims. In addition, it should be noted that not all the combinations of features described in the embodiments are essential to the means for solving the problems of the invention.

２…α−Ａｌ２Ｏ３基板、 ３…ｐ型α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜、 ４…アンドープα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜、 １０、２０…Ｇａ２Ｏ３系ＦＥＴ、 １１…ゲート電極、 １２…ソース電極、 １３…ドレイン電極、 １４、１５、２４、２５…コンタクト領域 2... Α-Al 2 O 3 substrate, 3... P-type α- (Al x Ga 1-x ) 2 O 3 single crystal film, 4... Undoped α- (Al x Ga 1-x ) 2 O 3 single crystal film 10, 20 ... Ga 2 O 3 type FET, 11 ... Gate electrode, 12 ... Source electrode, 13 ... Drain electrode, 14, 15, 24, 25 ... Contact region

Claims (3)

α−Ａｌ２Ｏ３基板上に形成されたα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶（０≦ｘ＜１）からなるα−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜と、
前記α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜上に形成されたソース電極及びドレイン電極と、
前記α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜中に形成され、前記ソース電極及び前記ドレイン電極にそれぞれ接続された第１のコンタクト領域及び第２のコンタクト領域と、
前記α−Ａｌ２Ｏ３基板の前記α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜と反対側の面上の、前記第１のコンタクト領域と前記第２のコンタクト領域との間に形成されたゲート電極と、
を含むＧａ２Ｏ３系半導体素子。 α-Al 2 O 3 consisting of alpha-formed on a substrate (Al x Ga 1-x) 2 O 3 single crystal (0 ≦ x <1) α- (Al x Ga 1-x) 2 O 3 single A crystal film;
A source electrode and a drain electrode formed on the α- (Al x Ga 1-x ) 2 O 3 single crystal film;
A first contact region and a second contact region formed in the α- (Al x Ga 1-x ) 2 O 3 single crystal film and connected to the source electrode and the drain electrode, respectively;
Between the first contact region and the second contact region on the surface of the α-Al 2 O 3 substrate opposite to the α- (Al x Ga 1-x ) 2 O 3 single crystal film. A gate electrode formed on
A Ga 2 O 3 based semiconductor element containing 前記α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜はｐ型であり、
第１のコンタクト領域、及び第２のコンタクト領域はｎ型である、
請求項１に記載のＧａ２Ｏ３系半導体素子。 The α- (Al x Ga 1-x ) 2 O 3 single crystal film is p-type,
The first contact region and the second contact region are n-type.
Ga 2 O 3 based semiconductor device according to claim 1. 前記α−（ＡｌｘＧａ１−ｘ）２Ｏ３単結晶膜は、ドーパントを含まない高抵抗の領域であり、
第１のコンタクト領域、及び第２のコンタクト領域はｎ型である、
請求項１に記載のＧａ２Ｏ３系半導体素子。
The α- (Al x Ga 1-x ) 2 O 3 single crystal film is a high-resistance region that does not contain a dopant,
The first contact region and the second contact region are n-type.
Ga 2 O 3 based semiconductor device according to claim 1.
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Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014072517A (en) * 2013-06-21 2014-04-21 Roca Kk Semiconductor device and manufacturing method of the same, and crystal and manufacturing method of the same
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JP2016201540A (en) * 2015-04-10 2016-12-01 株式会社Flosfia Crystalline oxide semiconductor film and semiconductor device
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JP2017103446A (en) * 2015-12-04 2017-06-08 財團法人工業技術研究院Ｉｎｄｕｓｔｒｉａｌ Ｔｅｃｈｎｏｌｏｇｙ Ｒｅｓｅａｒｃｈ Ｉｎｓｔｉｔｕｔｅ P-type metal oxide semiconductor material and transistor
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WO2019098296A1 (en) 2017-11-15 2019-05-23 株式会社Flosfia Semiconductor device
WO2019098295A1 (en) 2017-11-15 2019-05-23 株式会社Flosfia P-type oxide semiconductor film and method for forming same
WO2019098298A1 (en) 2017-11-15 2019-05-23 株式会社Flosfia Semiconductor device
WO2020013260A1 (en) 2018-07-12 2020-01-16 株式会社Flosfia Semiconductor device and semiconductor system including semiconductor device
WO2020013259A1 (en) 2018-07-12 2020-01-16 株式会社Flosfia Semiconductor device and semiconductor system including semiconductor device
US10538862B2 (en) 2015-03-20 2020-01-21 Tamura Corporation Crystal laminate structure
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JPWO2021106809A1 (en) * 2019-11-29 2021-06-03
JPWO2021106811A1 (en) * 2019-11-29 2021-06-03
JPWO2021106810A1 (en) * 2019-11-29 2021-06-03
CN114302982A (en) * 2019-08-27 2022-04-08 信越化学工业株式会社 Laminated structure and method for producing the same
WO2023149180A1 (en) 2022-02-02 2023-08-10 信越化学工業株式会社 Crystalline oxide film, multilayer structure, semiconductor device, and method for producing crystalline oxide film
KR20230120608A (en) 2022-02-09 2023-08-17 가부시키가이샤 플로스피아 Crystalline oxide films, laminated structures, and semiconductor devices
WO2024122463A1 (en) 2022-12-06 2024-06-13 信越化学工業株式会社 Crystalline oxide semiconductor film, laminated structure, and semiconductor device
US12100760B2 (en) 2018-07-12 2024-09-24 Flosfia Inc. Semiconductor device and semiconductor system including semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004022837A (en) * 2002-06-17 2004-01-22 Stanley Electric Co Ltd Oxide semiconductor thin film deposition substrate by vapor phase method and deposition method
JP2006073774A (en) * 2004-09-02 2006-03-16 Matsushita Electric Ind Co Ltd Thin film transistor and manufacturing method thereof
JP2007287451A (en) * 2006-04-14 2007-11-01 Kochi Univ Of Technology Ion doping apparatus, ion doping method, semiconductor device manufacturing method, and thin film transistor manufacturing method
JP2009091217A (en) * 2007-10-11 2009-04-30 Nippon Light Metal Co Ltd Gallium-aluminum oxide crystal film, method for producing the same, and semiconductor device using the same
JP2010212436A (en) * 2009-03-10 2010-09-24 Fuji Xerox Co Ltd Field effect transistor
JP2011130424A (en) * 2009-11-20 2011-06-30 Semiconductor Energy Lab Co Ltd Modulation circuit and semiconductor device including the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004022837A (en) * 2002-06-17 2004-01-22 Stanley Electric Co Ltd Oxide semiconductor thin film deposition substrate by vapor phase method and deposition method
JP2006073774A (en) * 2004-09-02 2006-03-16 Matsushita Electric Ind Co Ltd Thin film transistor and manufacturing method thereof
JP2007287451A (en) * 2006-04-14 2007-11-01 Kochi Univ Of Technology Ion doping apparatus, ion doping method, semiconductor device manufacturing method, and thin film transistor manufacturing method
JP2009091217A (en) * 2007-10-11 2009-04-30 Nippon Light Metal Co Ltd Gallium-aluminum oxide crystal film, method for producing the same, and semiconductor device using the same
JP2010212436A (en) * 2009-03-10 2010-09-24 Fuji Xerox Co Ltd Field effect transistor
JP2011130424A (en) * 2009-11-20 2011-06-30 Semiconductor Energy Lab Co Ltd Modulation circuit and semiconductor device including the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SHINOHARA DAISUKE, FUJITA SHIZUO (KYOTO UNIV., KYOTO, JPN): "Heteroepitaxy of Corundum-Structured α-Ga2O3 Thin Films on α-Al2O3 Substrates by Ultrasonic Mist C", JPN J APPL PHYS, vol. 47, no. 9, JPN6015033628, 12 September 2008 (2008-09-12), JP, pages 7311 - 7313, XP055137290, ISSN: 0003139503, DOI: 10.1143/JJAP.47.7311 *

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WO2024122463A1 (en) 2022-12-06 2024-06-13 信越化学工業株式会社 Crystalline oxide semiconductor film, laminated structure, and semiconductor device

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