JP2010193119A - Method of preventing image information stealing and graphic controller for achieving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of preventing image information stealing which obviates the need of a shield for an electronic apparatus or a room, and allows the use of an existing display. <P>SOLUTION: When transmitting image information (video signal video) to a display 200, a computer 100 generates a horizontal synchronization signal and a vertical synchronization signal by a horizontal-vertical synchronization generation circuit 125 so that each of the frequency fh of the horizontal synchronization signal Hsync and the frequency fv of the vertical synchronization signal Vsync always varies in a preset range to be transmitted to the display, and thereby displays the image information on the display based on the horizontal synchronization signal and the vertical synchronization signal of which the frequencies vary. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image information theft prevention method for preventing the theft of image information performed by intercepting a weak electromagnetic wave leaking from a computer, and a graphic controller for realizing the prevention method.

  Electronic devices such as computers and peripheral devices (for example, displays) may be stolen by intercepting weak electromagnetic waves that leak from the electronic devices. A technique for stealing such information is referred to as “TEMPEST (Transient Electromagnetic Pulse Survey Technology)”. In “TEMPEST”, image information displayed on the display is particularly easily stolen. For this reason, it is preferable that the electronic device has a TEMPEST countermeasure.

  As a general TEMPEST measure, an electronic device manufacturer or user shields electronic devices (specifically, the computer body, peripheral devices, and all connections between computers and peripheral devices) so that electromagnetic waves do not leak. It is to be. However, in consideration of the operability of the electronic device, the room where the electronic device is installed may be shielded.

  Also, for example, in Patent Document 1, as a countermeasure against TEMPEST, a computer on the image information transmission side transmits a video signal together with these synchronization signals by shifting the phases of the horizontal synchronization signal and the vertical synchronization signal, and the display on the image information reception side A technique for displaying a video signal in synchronization with a horizontal synchronizing signal and a vertical synchronizing signal having different phases is disclosed.

Japanese Patent Laid-Open No. 06-83298

  However, since the above-described general TEMPEST countermeasure needs to shield an electronic device or a room, there is a problem that a burden is imposed on the user in terms of cost.

  In addition, the technique disclosed in Patent Document 1 needs to change the configuration of the display. That is, in the technique disclosed in Patent Document 1, it is necessary to provide a display with a circuit for displaying a video signal in synchronization with a horizontal synchronizing signal and a vertical synchronizing signal having different phases. Therefore, the technique disclosed in Patent Document 1 has a problem in that the cost of the display increases because the configuration of the display becomes complicated. Moreover, since the technique disclosed in Patent Document 1 needs to change the configuration of the display, there is a problem that an existing display that is widely used cannot be used.

  The present invention has been made to solve the above-described problems, and does not require an electronic device or room shield, and can steal image information that can be used by an existing display without changing the configuration of the display. The main object of the present invention is to provide a graphics controller incorporated in a computer on the image information transmission side in order to realize this prevention method.

By the way, in TEMPEST, even if a malicious person steals image information transmitted from the image information transmission side to the reception side, a low-frequency component (such as a video signal) is also included in the stolen image information. , A continuous signal block such as black) can be extracted, but a synchronization signal cannot be extracted. Therefore, a malicious person fixes the synchronization signal to the assumed value, extracts the video signal from the stolen image information, and synchronizes the extracted video signal with the assumed synchronization signal to obtain the image. Information is being played (displayed).
Therefore, the inventor gives a special characteristic to the synchronization signal that cannot be extracted by TEMPEST (specifically, a range in which the frequency of the synchronization signal is set in advance (particularly, preferably the display operation of the display on the image information receiving side). It is considered that it is possible to apply simple and effective TEMPEST countermeasures to electronic devices by constantly changing within the guaranteed range.

  In order to achieve the above object based on such a viewpoint, the first invention provides a method for preventing image information theft for preventing image information from being stolen by intercepting a weak electromagnetic wave leaking from a computer. The computer includes a horizontal / vertical synchronization signal generation circuit that generates a horizontal synchronization signal and a vertical synchronization signal, and the horizontal / vertical synchronization signal generation circuit when transmitting the image information to a display. The horizontal synchronization signal and the vertical synchronization signal are generated and transmitted to the display so that the frequency of the horizontal synchronization signal and the frequency of the vertical synchronization signal always fluctuate within a preset range. Thus, the image information is displayed on the display based on the horizontal synchronizing signal and the vertical synchronizing signal whose frequency varies. And wherein the door.

  Further, the second invention is a graphic controller for generating image information to be displayed on the display, and the frequency of the horizontal synchronizing signal and the frequency of the vertical synchronizing signal are always changed within a preset range. It has a horizontal / vertical synchronizing signal generating circuit for generating a horizontal synchronizing signal and the vertical synchronizing signal.

  According to the first aspect of the present invention, there is provided a method for preventing image information theft that does not require shielding of an electronic device and a room and that can be used by an existing display without modifying the configuration of the display. Accordingly, it is possible to provide a graphic controller for realizing the prevention method of the first invention.

It is a block diagram (1) for demonstrating the structure of the horizontal / vertical synchronizing signal generation circuit which concerns on embodiment. It is a block diagram (2) for demonstrating the structure of the horizontal / vertical synchronizing signal generation circuit which concerns on embodiment. It is a state transition diagram for explaining the operation of the vertical synchronizing signal output circuit. It is a state transition diagram for demonstrating operation | movement of a horizontal synchronizing signal output circuit. FIG. 5 is an explanatory diagram of a relationship between a register setting value and a synchronization frequency. It is explanatory drawing of a synchronous frequency. It is explanatory drawing of a display screen.

  Hereinafter, an embodiment of the present invention (hereinafter referred to as “the present embodiment”) will be described in detail with reference to the drawings. In addition, each figure is only shown schematically to such an extent that the present invention can be understood. Therefore, the present invention is not limited to the illustrated example. Moreover, in each figure, the same code | symbol is attached | subjected about the common component and the same component, and those overlapping description is abbreviate | omitted.

<Configuration of horizontal / vertical synchronization signal generation circuit>
Hereinafter, a configuration of a horizontal / vertical synchronizing signal generation circuit which is a characteristic component of the present invention will be described with reference to FIG. 1 and FIG. 1 and 2 are block diagrams for explaining the configuration of the horizontal / vertical synchronizing signal generation circuit according to the embodiment.

First, the configuration of the computer 100 in which the horizontal / vertical synchronization signal generation circuit 125 is incorporated will be described with reference to FIG.
As shown in FIG. 1, the computer 100 includes a video memory 110, a graphic controller 120, a clock generator 130, and a transmitter 140.

  The video memory 110 is a storage unit that stores image information. The video memory 110 outputs a video signal Video constituting image information to the graphic controller 120.

  The graphic controller 120 is a signal generating unit for displaying image information on the display 200. The graphic controller 120 is connected to a CPU (not shown) via the CPU bus 20 and generates image information to be displayed on the display 200 based on a command from the CPU. The graphic controller 120 has a horizontal / vertical synchronization signal generation circuit 125. The horizontal / vertical synchronization signal generation circuit 125 has a frequency of the horizontal synchronization signal Hsync (hereinafter referred to as “horizontal synchronization frequency”) fh (see FIG. 5) and a frequency of the vertical synchronization signal Vsync (hereinafter referred to as “vertical synchronization frequency”). ) Function means for generating the horizontal synchronization signal Hsync and the vertical synchronization signal Vsync so that fv (see FIG. 5) always varies within a preset range. The configuration of the horizontal / vertical synchronization signal generation circuit 125 will be described later.

  The clock generator 130 is a functional unit that generates a video clock signal VCLOCK for sampling the video signal Video. The clock generator 130 outputs the generated video clock signal VCLOCK to the graphic controller 120.

  The transmitter 140 is a functional unit for transmitting image information to the display 200. The transmitter 140 transmits the video signal Video, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the video clock signal VCLOCK output from the graphic controller 120 to the display 200. The display 200 receives the video signal Video, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the video clock signal VCLOCK by the receiver 210, and displays image information on the display unit 220 based on these signals. .

Next, a detailed configuration of the horizontal / vertical synchronization signal generation circuit 125 will be described with reference to FIG.
As shown in FIG. 2, the horizontal / vertical synchronization signal generation circuit 125 includes four registers 1, 2, 3, 4, a vertical deviation generation circuit 5, a horizontal deviation generation circuit 6, a vertical synchronization signal output circuit 7, and a horizontal A synchronization signal output circuit 8 is provided.

  The register 1 is storage means in which a maximum value of the number of vertical lines NV (see FIG. 5) (hereinafter referred to as “maximum number of vertical lines NVmax (see FIG. 5)”) is set. The register 2 is storage means in which a minimum value of the number of vertical lines NV (hereinafter referred to as “minimum number of vertical lines NVmin (see FIG. 5)”) is set. The register 3 is storage means in which the maximum value of the horizontal dot number NH (see FIG. 5) (hereinafter referred to as “maximum horizontal dot number NHmax (see FIG. 5)”) is set. The register 4 is storage means in which a minimum value of the number of horizontal dots NH (hereinafter referred to as “minimum number of horizontal dots NHmin (see FIG. 5)”) is set. The four registers 1, 2, 3, and 4 are connected to a CPU (not shown) via the CPU bus 20, respectively. The CPU controls the maximum vertical line number NVmax, the minimum vertical line number NVmin, and the maximum corresponding to each of them. One of the horizontal dot number NHmax and the minimum horizontal dot number NHmin is set (stored).

  The register 1 outputs the maximum vertical line number NVmax to the vertical deviation generation circuit 5 as the output b. The register 2 outputs the minimum vertical line number NVmin to the vertical deviation generation circuit 5 as the output c. The register 3 outputs the maximum horizontal dot number NHmax to the horizontal deviation generating circuit 6 as the output d. The register 4 outputs the minimum horizontal dot number NHmin to the horizontal deviation generation circuit 6 as the output e.

  The vertical deviation generation circuit 5 is a functional unit that generates the number of vertical lines NV set in the vertical counter 7a described later. The vertical deviation generation circuit 5 receives the maximum vertical line number NVmax from the register 1, receives the minimum vertical line number NVmin from the register 2, and further receives the vertical synchronization signal Vsync from the vertical synchronization signal output circuit 7. The vertical deviation generation circuit 5 generates the vertical line number NV in synchronization with the vertical synchronization signal Vsync so that the value always deviates (varies) within the range from the minimum vertical line number NVmin to the maximum vertical line number NVmax. The output f is output to the vertical synchronization signal output circuit 7.

  The horizontal deviation generating circuit 6 is a functional means for generating a horizontal dot number NH set in a horizontal counter 8a described later. The horizontal deviation generation circuit 6 receives the maximum horizontal dot number NHmax from the register 3, receives the minimum horizontal dot number NHmin from the register 4, and further receives the horizontal synchronization signal Hsync from the horizontal synchronization signal output circuit 8. The horizontal deviation generation circuit 6 generates the horizontal dot number NH in synchronization with the horizontal synchronization signal Hsync so that the value always deviates (varies) within the range from the minimum horizontal dot number NHmin to the maximum horizontal dot number NHmax. The output g is output to the horizontal synchronizing signal output circuit 8.

  The vertical synchronization signal output circuit 7 is functional means for outputting the vertical synchronization signal Vsync subsequently. The vertical synchronization signal output circuit 7 receives the number of vertical lines NV from the vertical deviation generation circuit 5, and further receives the horizontal synchronization signal Hsync from the horizontal counter 8. The vertical synchronizing signal output circuit 7 includes a counter (hereinafter, referred to as “vertical counter”) 7a that counts values based on the horizontal synchronizing signal Hsync. When the vertical line number NV is input from the vertical deviation generation circuit 5, the vertical synchronization signal output circuit 7 sets (stores) the input vertical line number NV in the vertical counter 7a as the upper limit value of the count. Accordingly, the vertical counter 7a counts values from “0” to “NV”, with the lower limit value being “0” and the upper limit value being “NV”. Note that the number of vertical lines NV set in the vertical counter 7a varies.

  As will be described later, when the count value of the vertical counter 7a is between “0” and “NV−1”, the vertical synchronization signal output circuit 7 uses L (“0”) as the vertical synchronization signal Vsync. Low) signal is generated, and when the count value of the vertical counter 7a becomes “NV”, an H (high) signal having a value “1” is generated as the vertical synchronization signal Vsync. The vertical synchronization signal output circuit 7 outputs the generated vertical synchronization signal Vsync as an output h to the vertical deviation generation circuit 5 and also to the display unit 220 via the transmitter 140 of the display 200 (see FIG. 1).

  The horizontal synchronizing signal output circuit 8 is a functional unit that outputs the horizontal synchronizing signal Hsync subsequently. The horizontal synchronization signal output circuit 8 receives the horizontal dot number NV from the horizontal deviation generation circuit 6 and further receives the video clock signal VCLOCK from the clock generator 130. The horizontal synchronization signal output circuit 8 includes a counter (hereinafter referred to as “horizontal counter”) 8a that counts values based on the video clock signal VCLOCK. When the horizontal dot number NH is input from the horizontal deviation generating circuit 6, the horizontal synchronizing signal output circuit 8 sets (stores) the input horizontal dot number NH in the horizontal counter 8a as the upper limit value of the count. Thereby, the horizontal counter 8a sets the lower limit value to “0”, sets the upper limit value to “NH”, and counts values from “0” to “NH”. The horizontal dot number NH set in the horizontal counter 8a is a fluctuating value.

  As will be described later, when the count value of the horizontal counter 8a is between “0” and “NH−1”, the horizontal synchronization signal output circuit 8 uses the L signal having the value “0” as the horizontal synchronization signal Hsync. When the count value of the horizontal counter 8a becomes “NH”, an H signal having a value “1” is generated as the horizontal synchronization signal Hsync. The horizontal synchronization signal output circuit 8 outputs the generated horizontal synchronization signal Hsync as an output i to the horizontal deviation generation circuit 6 and also to the display unit 220 via the transmitter 140 of the display 200.

<Operation of horizontal / vertical sync signal generator>
Hereinafter, the operation of the horizontal / vertical synchronizing signal generation circuit 125 will be described.
Note that the horizontal / vertical synchronizing signal generation circuit 125 sets the maximum vertical line number NVmax in the register 1 and the minimum vertical line number NVmin in the register 2 in advance by a CPU (not shown). Is set in the register 3, and the minimum horizontal dot number NHmin is set in the register 4. These set values (that is, the maximum number of vertical lines NVmax, the minimum number of vertical lines NVmin, the maximum number of horizontal dots NHmax, and the minimum number of horizontal dots NHmin) are the vertical synchronization signals generated by the vertical synchronization signal output circuit 7, respectively. The guaranteed range of the display operation of the display 200 on the image information receiving side is the frequency of Vsync (that is, vertical synchronization frequency fv) and the frequency of the horizontal synchronization signal Hsync generated by the horizontal synchronization signal output circuit 8 (that is, horizontal synchronization frequency fh). The value to be a value within is predetermined. Specific values of these set values will be described later with reference to FIG.

  First, the vertical deviation generation circuit 5 reads the set values (that is, the maximum vertical line number NVmax and the minimum vertical line number NVmin) set from the register 1 and the register 2, respectively, and based on these set values, the vertical counter The number of vertical lines NV set to 7a is determined (generated). At this time, the number of vertical lines NV determined by the vertical deviation generation circuit 5 is arbitrarily changed within the range from the minimum number of vertical lines NVmin to the maximum number of vertical lines NVmax in synchronization with the vertical synchronization signal Vsync. . As the means, for example, a sequential circuit that changes in order from the minimum number of vertical lines NVmin to the maximum number of vertical lines NVmax, or a pseudo-random circuit can be considered.

  Similarly, the horizontal deviation generating circuit 6 reads the set values (that is, the maximum horizontal dot number NHmax and the minimum horizontal dot number NHmin) respectively set from the register 3 and the register 4, and based on these set values, The number of horizontal dots NH set in the counter 8a is determined (generated). At this time, the horizontal dot number NH determined by the horizontal deviation generating circuit 6 is arbitrarily changed in synchronization with the horizontal synchronization signal Hsync within the range from the minimum horizontal dot number NHmin to the maximum horizontal dot number NHmax. . As the means, for example, a sequential circuit that changes in order from the minimum horizontal dot number NHmin to the maximum horizontal dot number NHmax, or a pseudo-random circuit can be considered.

  As will be described later with reference to FIG. 3, the vertical synchronization signal output circuit 7 changes its state in accordance with the count value of the vertical counter 7a, and outputs a vertical synchronization signal Vsync having a value corresponding to each state. At this time, the value (that is, the number of vertical lines NV) set in the vertical counter 7a is deviated (varied). Accordingly, the vertical synchronization frequency (that is, vertical) output from the vertical synchronization signal output circuit 7 according to this variation. The frequency of the synchronization signal Vsync) fv (see FIG. 5) also varies.

  On the other hand, as will be described later with reference to FIG. 4, the horizontal synchronization signal output circuit 8 changes the state in accordance with the count value of the horizontal counter 8a and outputs the horizontal synchronization signal Hsync having a value corresponding to each state. . At this time, the value (that is, the number of horizontal dots NH) set in the horizontal counter 8a is deviated (varied). Accordingly, the horizontal synchronization frequency (that is, horizontal level) output from the horizontal synchronization signal output circuit 8 according to this variation. The frequency of the synchronization signal Hsync) fh (see FIG. 5) also varies.

Hereinafter, the operation of the vertical synchronizing signal output circuit 7 will be described with reference to FIG. FIG. 3 is a state transition diagram for explaining the operation of the vertical synchronizing signal output circuit. FIG. 3 shows that the vertical synchronization signal output circuit 7 makes the first state the initial state and sequentially changes from the first state to the second state and the third state according to the count value of the vertical counter 7a. ing.
Here, it is assumed that the count value of the vertical counter 7a is “n”, the lower limit value of the count is “0”, and the upper limit value of the count is “N”.

  First, the vertical synchronizing signal output circuit 7 sets (stores) the number of vertical lines NV generated by the vertical deviation generation circuit 5 in the vertical counter 7a as the count upper limit value N. Accordingly, the vertical counter 7a counts values from “0” to “NV”, with the lower limit value being “0” and the upper limit value N being “NV”.

  The vertical synchronizing signal output circuit 7 receives the horizontal synchronizing signal Hsync as the output i from the vertical synchronizing signal output circuit 8. The vertical counter 7a of the vertical synchronization signal output circuit 7 counts a value in synchronization with the horizontal synchronization signal Hsync. The state of the vertical synchronization signal output circuit 7 changes according to the count value of the vertical counter 7a. Therefore, the state of the vertical synchronizing signal output circuit 7 changes in synchronization with the horizontal synchronizing signal Hsync.

  As shown in FIG. 3, the vertical synchronization signal output circuit 7 is in the first state when the count value of the vertical counter 7a is “n = 0”, and the count value of the vertical counter 7a is “n ≠ 0”. And “n ≠ N” (that is, when the count value of the vertical counter 7a is between “n = 1” and “n = N−1”), The third state is entered when the count value of the vertical counter 7a is “n = N”.

  In the first state, the vertical synchronization signal output circuit 7 outputs a value “0” as the vertical synchronization signal Vsync. Thereafter, the vertical synchronizing signal output circuit 7 updates (processes) the count value of the vertical counter 7a to “n = 1”, and transitions to the second state.

  In the second state, the vertical synchronization signal output circuit 7 appropriately updates the count value n of the vertical counter 7a to “n + 1” while the count value of the vertical counter 7a is “n ≠ N−1”. During this time, the vertical synchronization signal output circuit 7 outputs the value “0” as the vertical synchronization signal Vsync. Then, when the count value of the vertical counter 7a reaches “n = N−1”, the vertical synchronization signal output circuit 7 updates the count value of the vertical counter 7a to “n = N” and makes a transition to the third state. .

  In the third state, the vertical synchronization signal output circuit 7 outputs the value “1” as the vertical synchronization signal Vsync. Then, the vertical synchronization signal output circuit 7 is initialized (updated) to “n = 0” in the count value of the vertical counter 7a, and transitions to the first state. At this time, the vertical synchronizing signal output circuit 7 sets (stores) the vertical cycle number NV for the next period generated by the vertical deviation generation circuit 5 in the vertical counter 7a as the count upper limit value N.

On the other hand, the horizontal synchronizing signal output circuit 8 operates in the same manner as the vertical synchronizing signal output circuit 7.
Hereinafter, the operation of the horizontal synchronizing signal output circuit 8 will be described with reference to FIG. FIG. 4 is a state transition diagram for explaining the operation of the horizontal synchronizing signal output circuit. In FIG. 4, the horizontal synchronization signal output circuit 8 sets the first state to the initial state in the same manner as the vertical synchronization signal output circuit 7, and changes from the first state to the second state according to the count value of the horizontal counter 8 a. It shows that the state transitions sequentially to three states.
However, here, the count value of the horizontal counter 8 is described as “n”. Here, the description will be made assuming that the horizontal synchronizing signal output circuit 8 sets the horizontal dot number NH generated by the horizontal deviation generating circuit 6 in the horizontal counter 8a as the upper limit value N of the count.

  First, the horizontal synchronization signal output circuit 8 sets (stores) the horizontal dot number NH generated by the horizontal deviation generation circuit 6 in the horizontal counter 8a as the count upper limit value N. Thereby, the horizontal counter 8a sets the lower limit value to “0”, sets the upper limit value N to “NH”, and counts values from “0” to “NH”.

  The horizontal synchronizing signal output circuit 8 receives the video clock signal VCLOCK as an output j from the clock generator 130. The horizontal counter 8a of the horizontal synchronizing signal output circuit 8 counts the value in synchronization with the video clock signal VCLOCK. The state of the horizontal synchronizing signal output circuit 8 changes according to the count value of the horizontal counter 8a. Accordingly, the state of the horizontal synchronizing signal output circuit 8 changes in synchronization with the video clock signal VCLOCK.

  As shown in FIG. 4, similarly to the vertical synchronization signal output circuit 7, the horizontal synchronization signal output circuit 8 is in the first state when the count value of the horizontal counter 8a is “n = 0”, and the horizontal synchronization signal output circuit 8 When the count value of the counter 8a is “n ≠ 0” and “n ≠ N” (that is, when the count value of the horizontal counter 8a is between “n = 1” and “n = N−1”) ), The second state is entered, and the third state is entered when the count value of the horizontal counter 8a is “n = N”.

  In the first state, the horizontal synchronization signal output circuit 8 outputs a value “0” as the horizontal synchronization signal Hsync. Thereafter, the horizontal synchronization signal output circuit 8 updates (processes) the count value of the horizontal counter 8a to “n = 1”, and transitions to the second state.

  In the second state, the horizontal synchronization signal output circuit 8 appropriately updates the count value n of the horizontal counter 8a to “n + 1” while the count value of the horizontal counter 8a becomes “n ≠ N−1”. During this time, the horizontal synchronization signal output circuit 8 outputs the value “0” as the horizontal synchronization signal Hsync. Then, when the count value of the horizontal counter 8a reaches “n = N−1”, the horizontal synchronization signal output circuit 8 updates the count value of the horizontal counter 8a to “n = N” and makes a transition to the third state. .

  In the third state, the horizontal synchronization signal output circuit 8 outputs a value “1” as the horizontal synchronization signal Hsync. Then, the horizontal synchronization signal output circuit 8 is initialized (updated) to “n = 0” as the count value of the horizontal counter 8a, and transitions to the first state. At this time, the horizontal synchronizing signal output circuit 8 sets (stores) the horizontal dot number NH for the next cycle generated by the horizontal deviation generating circuit 6 in the horizontal counter 8a as the count upper limit value N.

Note that. As the states of the vertical synchronizing signal output circuit 7 and the horizontal synchronizing signal output circuit 8 change, the horizontal synchronizing frequency fh (see FIG. 5) and the vertical synchronizing frequency fv (see FIG. 5) are respectively within the following ranges. Change.
fh: fvideo / NHmax to fvideo / NHmin
fv: fvideo / (NHmax × NVmax) to fvideo / (NHmin × NVmin)
Here, fvideo is the frequency of the video clock signal VCLOCK (hereinafter referred to as “video frequency”).

  Note that the vertical synchronization frequency fv and the horizontal synchronization frequency fh always vary within a certain range. Hereinafter, specific values of the vertical synchronization frequency fv and the horizontal synchronization frequency fh will be described with reference to FIGS. FIG. 5 is an explanatory diagram of the relationship between the register setting value and the synchronization frequency. FIG. 6 is an explanatory diagram of the synchronization frequency, and FIG. 7 is an explanatory diagram of the display screen.

  Here, the case where the number of display pixels of the display 200 is horizontal 1024 × vertical 768 and the video frequency fvideo is 65 MHz will be described. In this case, as shown in FIG. 5, the minimum horizontal dot number NHmin that is the set value of the register 4 is “1080” dots, and the maximum horizontal dot number NHmax that is the set value of the register 3 is “1200” dots. The minimum vertical line number NVmin that is a setting value of 2 is “780” lines, and the maximum vertical line number NVmax that is a setting value of the register 1 is “840” lines.

In this case, the minimum value (hereinafter referred to as “minimum horizontal synchronization frequency”) fhmin and maximum value (hereinafter referred to as “maximum horizontal synchronization frequency”) fhmax of the horizontal synchronization frequency fh, and the minimum value of the vertical synchronization frequency fv. The fvmin (hereinafter referred to as “minimum vertical synchronization frequency”) and the maximum value (hereinafter referred to as “maximum vertical synchronization frequency”) fvmax are as follows (see FIG. 5).
fhmin = fvideo / NHmax = 65 MHz / 1200 = 54.2 kHz
fhmax = fvideo / NHmin = 65 MHz / 1080 = 60.2 kHz
fvmin = fvideo / (NHmax × NVmax) = 65 MHz / (1200 × 840) = 64.5 Hz
fvmax = fvideo / (NHmin × NVmin) = 65 MHz / (1080 × 780) = 77.2 Hz

  Therefore, the horizontal synchronization frequency fh and the vertical synchronization frequency fv always vary within the range R shown in FIG.

  If a malicious person attempts to steal image information by TEMPEST, TEMPEST cannot extract the horizontal synchronizing signal fh and the vertical synchronizing signal fv from the stolen image information. Therefore, a malicious person fixes the horizontal synchronization signal fh and the vertical synchronization signal fv to assumed values, extracts the video signal Video from the image information that does not include the stolen synchronization signal, and extracts the extracted video signal. Image information is reproduced (displayed) by synchronizing Video with the assumed horizontal synchronizing signal fh and vertical synchronizing signal fv. However, the actual horizontal synchronization frequency fh and vertical synchronization frequency fv always vary within the range R shown in FIG. For this reason, the stolen image information is appropriately moved in the direction of the arrow shown in FIG. 7, for example, so that it always appears to flow. That is, since a malicious person cannot synchronize the video signal Video, the image information cannot be displayed normally.

  On the other hand, the display 200 is directly connected to the computer 100. Therefore, the display 200 can appropriately acquire the horizontal synchronization frequency fh and the vertical synchronization frequency fv that cannot be extracted by TEMPEST from the computer 100. Therefore, the display 200 can synchronize the video signal Video. Moreover, the horizontal synchronization frequency fh and the vertical synchronization frequency fv are values within the guaranteed range of the display operation of the display 200. Therefore, the display 200 can display image information normally.

As described above, according to this embodiment, the computer 100 on the image information transmission side always operates within the range in which the horizontal synchronization frequency fh and the vertical synchronization frequency fv are set in advance by the horizontal / vertical synchronization signal generation circuit 125. A horizontal synchronization signal Hsync and a vertical synchronization signal Vsync are generated and transmitted to the display 200 by the transmitter 140 so as to fluctuate. At this time, the horizontal / vertical synchronization signal generation circuit 125 determines that the horizontal synchronization frequency Hsync and the vertical synchronization frequency fh and the vertical synchronization frequency fv are values within the guaranteed range of the display operation of the display 200 on the image information receiving side. A synchronization signal Vsync is generated. Therefore, according to the present embodiment, it is possible to prevent the stealing of image information without shielding an electronic device or a room, thereby reducing the burden on the user in terms of cost.
Further, according to the horizontal / vertical synchronization signal generation circuit 125, the horizontal synchronization frequency fh and the vertical synchronization frequency fv are varied within the guaranteed range of the display operation of the display 200. Therefore, the configuration of the display 200 is completely altered. In addition, it is possible to prevent theft of image information that can be used by the existing display 200.

The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the gist of the present invention.
For example, in the above-described embodiment, the horizontal / vertical synchronization signal generation circuit 125 registers the maximum vertical line number NVmax and the minimum vertical line number NVmin, the maximum horizontal dot number NHmax, and the minimum horizontal dot number NHmin in the registers 1, 2, 3, 4 The configuration is set to. However, the horizontal / vertical synchronization signal generation circuit 125 may be configured to set the center value and deviation of the number of vertical lines NV and the number of horizontal dots NH in a register.

1, 2, 3, 4 Register 5 Vertical deviation generation circuit 6 Horizontal deviation generation circuit 7 Vertical synchronization signal output circuit 7a Vertical counter 8 Horizontal synchronization signal output circuit 8a Horizontal counter 20 CPU bus 100 Computer 110 Video memory 120 Graphic controller 125 Horizontal / Vertical synchronization signal generation circuit 130 Clock generator 140 Transmitter 200 Display 210 Receiver 220 Display unit Hsync Horizontal synchronization signal NH Number of horizontal dots NHmax Maximum number of horizontal dots NHmin Minimum number of horizontal dots NVmax Number of vertical lines NVmax Maximum number of vertical lines NVmin Minimum number of vertical lines VCLOCK Video clock signal Video Video signal Vsync Vertical sync signal

Claims (7)

In the image information theft prevention method for preventing the theft of image information performed by intercepting weak electromagnetic waves leaking from the computer,
The computer
It has a horizontal and vertical sync signal generation circuit that generates a horizontal sync signal and a vertical sync signal,
When transmitting the image information to the display, the horizontal and vertical synchronization signal generation circuit constantly changes the frequency of the horizontal synchronization signal and the frequency of the vertical synchronization signal within a preset range. Generating the horizontal synchronization signal and the vertical synchronization signal and transmitting them to the display, thereby causing the display to display the image information based on the horizontal synchronization signal and the vertical synchronization signal whose frequency varies. A method of preventing image information theft. In the image information theft prevention method according to claim 1,
The image signal stealing prevention method, wherein the image signal is a signal that does not include a synchronization signal and represents information including a video signal. In the image information theft prevention method according to claim 1 or claim 2,
The horizontal / vertical synchronization signal generation circuit includes the horizontal synchronization signal and the vertical synchronization signal so that the frequency of the horizontal synchronization signal and the frequency of the vertical synchronization signal are values within a guaranteed range of display operation of the display. A method of preventing image information theft. In a graphic controller that generates image information to be displayed on the display,
It has a horizontal / vertical synchronization signal generating circuit for generating the horizontal synchronization signal and the vertical synchronization signal so that the frequency of the horizontal synchronization signal and the frequency of the vertical synchronization signal always fluctuate within a preset range. A featured graphic controller. The graphic controller according to claim 4,
The horizontal / vertical synchronization signal generation circuit includes the horizontal synchronization signal and the vertical synchronization signal so that the frequency of the horizontal synchronization signal and the frequency of the vertical synchronization signal are values within a guaranteed range of display operation of the display. A graphic controller characterized by generating. The graphic controller according to claim 4 or 5,
The horizontal / vertical synchronization signal generation circuit includes:
A horizontal deviation generating circuit for generating a horizontal dot number whose value constantly fluctuates within a predetermined range from the minimum horizontal dot number to the maximum horizontal dot number;
A vertical deviation generating circuit for generating a number of vertical lines whose value constantly fluctuates within a preset range from the minimum number of vertical lines to the maximum number of vertical lines;
A horizontal synchronization signal whose value is high only when the value counted based on the video clock signal for sampling the video signal constituting the image information becomes the number of horizontal dots generated by the horizontal deviation generation circuit A horizontal sync signal output circuit for outputting
A vertical synchronization signal whose value is high only when the value counted based on the horizontal synchronization signal generated by the horizontal synchronization signal output circuit is equal to the number of vertical lines generated by the vertical deviation generation circuit And a vertical synchronization signal output circuit for outputting a graphic controller. The graphic controller according to claim 6.
In addition, it has four registers,
Each of the four registers is preset with any one of the minimum horizontal dot number, the maximum horizontal dot number, the minimum vertical line number, and the maximum vertical line number.

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