JP2010114461A - Solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a saturated signal amount, while suppressing white scratch generation or dark current generation caused by crystal defects, in a CMOS solid-state image pickup device. <P>SOLUTION: The solid-state image pickup device is formed with a first insulating film 40 on a semiconductor substrate 33 surface, a diffusion layer 43 and a second insulating film 44 on the diffusion layer and includes an element isolation means 86 for isolation neighboring pixels. The second insulating film 44 is formed in a position as deep as, or shallower than a p-n junction, in an accumulation layer 39 side of a photoelectric conversion part PD constituting a pixel, and is formed over the first insulating film 40. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  In general, MOS type semiconductor devices use LOCOS (selective oxidation) isolation as element isolation for a long time, and recently, STI (shallow trench isolation) has been used for miniaturization.

  Similarly, in a CMOS solid-state imaging device, it has become common to employ STI for device isolation. A CMOS solid-state imaging device is composed of a pixel region and a peripheral circuit that drives the signal region and performs signal processing, and employs a peripheral circuit miniaturization technique in the pixel region. The same STI element isolation method as that of the periphery is generally used in the element isolation of pixels of a recent fine CMOS solid-state imaging element.

  FIG. 9 shows a schematic configuration of a main part of a pixel region in a CMOS solid-state imaging device as viewed from above, and FIG. 10 shows a cross-sectional structure of a conventional photodiode (photoelectric conversion unit) by STI separation and a pixel transistor. FIG. 10 corresponds to a cross section on the line AA of FIG.

  In the CMOS solid-state imaging device, a unit pixel 2 [2A, 2B, 2C, 2D] is formed by a photodiode PD serving as a photoelectric conversion unit and a plurality of MOS transistors, and the plurality of unit pixels 2 are arranged in a matrix. A pixel region 3 is formed. The unit pixel 2 includes, for example, one photodiode PD and four CMOS transistors, that is, a read transistor, a reset transistor, a selection transistor, and an amplification transistor. In FIG. 9, for simplification of description, only the photodiode PD and the readout transistor Tr1, the reset transistor Tr2, and the amplification transistor Tr3 connected thereto are shown as the unit pixel 2, and the other selection transistors are omitted. The read transistor is formed by a charge storage region of the photodiode PD, a source / drain region 4 serving as a floating diffusion (FD), and a transfer gate electrode 5 formed through a gate insulating film. The reset transistor Tr2 is formed of a pair of source / drain regions 4 and 6 and a reset gate electrode 7 formed through a gate insulating film. The amplification transistor Tr3 is formed by source / drain regions 6 and 8 and a gate electrode formed through a gate insulating film. A vertical signal line 10 is connected to one source / drain region 8 of the readout transistor Tr1 of each pixel arranged in the vertical direction, and a power source that supplies a power supply voltage Vdd to one source / drain region 6 of the reset transistor Tr2. The line is connected. The pixels 2 [2A, 2B, 2C, 2D] are separated from each other by an element isolation region 22.

  As shown in the cross-sectional structure of FIG. 10, the CMOS solid-state imaging device 11 is formed with, for example, a p-type semiconductor well region 13 in an n-type silicon semiconductor substrate 12 and trenches are formed in the p-type semiconductor well region 13 by conventional STI isolation. 14 is formed and a silicon oxide film 15 is buried in the trench 14 to form an element isolation region that isolates elements between adjacent pixels 2, that is, an STI region 221 (corresponding to the element isolation region 22 in FIG. 9). Is done. By this STI region 221, the photodiode PD of one pixel 2B and the photodiode PD of the adjacent pixel 2A are separated, and the floating diffusion (FD) of the reading transistor Tr1 of one pixel 2B and the other pixel The source / drain region 8 of the 2A amplification transistor Tr3 is separated.

  The photodiode PD includes a so-called n-type substrate 12, a p-type semiconductor well region 13, an n-type charge storage region 18, and a p + accumulation layer 19 at the interface between the insulating film 20 on the surface side and a HAD (Hall Accumulated). (Diode) structure. The read transistor Tr1 is configured by forming a transfer gate electrode 5 through a gate insulating film 21 between the n-type charge storage region 18 of the photodiode PD and the source / drain region 4 serving as a floating diffusion (FD). On the other hand, in the STI region 221, a p + semiconductor region 17 for suppressing dark current and white scratches is formed at the interface between the deeply buried silicon oxide film 15, the n-type charge storage region 18 and the p-type semiconductor well region 13. It is formed.

  On the other hand, in a MOS solid-state imaging device, a technique has been proposed in which an element isolation portion is formed of an insulating film formed on a semiconductor substrate so as not to erode the semiconductor substrate as the element isolation portion (see Patent Document 1). .

JP2002-270808

  The CMOS solid-state imaging device using the above-described STI element separation method as a pixel region separation technique has two major problems.

  The STI element isolation method is excellent in forming a fine element isolation region because the deep trench 14 is formed in the silicon substrate (12, 13) and the silicon oxide film 15 is buried to form the element isolation region 81. However, there is a first problem that crystal defects due to thermal stress are likely to occur due to the difference in thermal expansion coefficient between the deeply buried silicon oxide film 15 and the silicon substrate (12, 13). For this reason, a contrivance such as making the STI shape tapered is performed. However, when the STI shape is tapered, the region of the photodiode PD is narrowed, leading to a decrease in saturation signal amount and sensitivity.

  The second problem is the presence of the p + semiconductor region 17 at the interface between the silicon oxide film 15 in the trench 14 and the photodiode PD. In the photodiode PD, so-called HAD sensor, the n-type charge accumulation region 18 is depleted, but the boundary with the silicon oxide film 15 suppresses dark current and white scratches due to generation of minority current carriers from the interface state. Therefore, it is necessary to cover with the P + semiconductor region 17 by the diffusion layer. Therefore, it is necessary to cover the interface of the silicon oxide film 15 in the STI region 221 with the p + semiconductor region 17 having a concentration similar to that of the p + accumulation layer 19 of the HAD sensor. There is a manufacturing problem of covering the depth direction with sufficient concentration three-dimensionally. For example, it is difficult to introduce a p-type impurity for forming the p + semiconductor region 17 into the side surface of the trench of the STI region 221 by ion implantation. That is, it is difficult to perform ion implantation because impurities are introduced into a narrow area (side surface of the trench) by oblique ion implantation. Further, since the p + semiconductor region 17 is further introduced at the initial stage of the process, there is a problem that the p + semiconductor region 17 spreads greatly toward the photosensor (photodiode PD) due to thermal diffusion, and the photosensor is narrowed. Even if heat treatment can be reduced, the trench side surface of the STI region 221 must be covered with the high-concentration p + semiconductor region 17 in principle. Therefore, as shown in FIG. There is a fundamental problem that the area of 18 becomes narrow and the saturation signal amount decreases.

  Element isolation by the STI region 221 which is a conventional miniaturization technique can achieve fine isolation as a simple MOS transistor isolation method, but the above-mentioned two problems are involved in pixel separation of a CMOS solid-state image sensor. Therefore, it is difficult to deteriorate the image and manufacture fine pixels.

In view of the above, the present invention provides a solid-state imaging device in which the generation of white scratches due to crystal defects and the occurrence of dark current are suppressed, and the saturation signal amount is increased as compared with the conventional one.
That is, the present invention requires a surface pinning layer (so-called p-type semiconductor region) for suppressing dark current at the interface in the STI separation method originally employed for miniaturization, and has an effective sensor area. It is an object of the present invention to provide a CMOS solid-state imaging device that solves the problem of not being able to earn, obtains a larger saturation signal amount with a pixel size of the same area, and can suppress the occurrence of dark current. In particular, the present invention provides a technique capable of increasing the amount of saturation signal by widening the sensor region with respect to the separation region between the photodiodes and between the photodiodes and the transistors that occupy many regions in the separation region.

  A solid-state imaging device according to the present invention includes an element separation unit that is formed by a first insulating film on a surface of a semiconductor substrate, a diffusion layer, and a second insulating film thereon, and separates adjacent pixels. The insulating film 2 is formed at a position that is equal to or shallower than the position of the pn junction on the accumulation layer side of the photoelectric conversion portion that constitutes the pixel, and is formed above the first insulating film. The configuration is as follows.

According to the solid-state imaging device according to the present invention, adjacent pixels are separated by the element separation means constituted by the diffusion layer and the second insulating film thereon. Since substantial element isolation between the pixels is performed in the diffusion layer, the isolation width is only the width of the diffusion layer, the area of the photoelectric conversion unit in the pixel can be expanded, and the saturation signal amount in the fine pixel is increased. Can do. Compared to the STI separation method, a larger saturation signal amount can be obtained with a pixel size of the same area. In addition, since the diffusion layer is used, generation of white scratches due to crystal defects and generation of dark current are suppressed.
Since the second insulating film is formed on the diffusion layer so as to protrude upward from the first insulating film, even if a part of the gate electrode is extended on the second insulating film, the second insulating film is formed. The inter-pixel separation is ensured without causing depletion or inversion layers directly under the insulating film. The second insulating film of the element isolating means is formed at a position equivalent to or shallower than the pn junction position on the accumulation layer side on the photoelectric conversion unit side, that is, the lower surface of the second insulating film Is set to a shallow position below the pn junction position, the photoelectric conversion part can be formed under the second insulating film, and the effective area of the photoelectric conversion part can be increased.

It is a block diagram of the principal part which shows 1st Embodiment of the solid-state image sensor which concerns on this invention. It is a block diagram of the principal part which shows 2nd Embodiment of the solid-state image sensor which concerns on this invention. It is a block diagram of the principal part which shows 3rd Embodiment of the solid-state image sensor which concerns on this invention. A It is a block diagram of the principal part which shows 4th Embodiment of the solid-state image sensor which concerns on this invention. B is a comparison diagram of surface potential distribution in a source / drain region of a transistor of a photodiode and an adjacent pixel across an element isolation region. C is a surface potential distribution diagram of the present embodiment in a source / drain region of a transistor of a pixel and an adjacent pixel across an element isolation region. 1A to 1B are manufacturing process diagrams (part 1) illustrating an embodiment of a method for manufacturing a solid-state imaging device according to the present invention. C to D are manufacturing process diagrams (part 2) illustrating an embodiment of a method for manufacturing a solid-state imaging device according to the present invention. E to F are manufacturing process diagrams (part 3) illustrating an embodiment of a method for manufacturing a solid-state imaging device according to the present invention. It is a manufacturing process figure (the 4) which shows one Embodiment of the manufacturing method of the solid-state image sensor which concerns on this invention. It is a schematic top view of an example of the pixel area of a solid-state image sensor. It is sectional drawing of the principal part (on the AA line of FIG. 9) of the solid-state image sensor of the prior art example 1. FIG. It is sectional drawing of the principal part which shows the reference example of a solid-state image sensor.

  A feature of the solid-state imaging device (hereinafter referred to as a CMOS solid-state imaging device) according to the present embodiment is that, in a pixel region where at least a plurality of pixels are arranged, element separation within a pixel and element separation between adjacent pixels are performed by a diffusion layer. More preferably, the element isolation is performed by an element isolation means composed of a diffusion layer and an insulating film thereon. That is, for element isolation between photodiodes, an isolation insulating film having a shallower depth than the conventional silicon oxide film in the STI region, and a required conductivity type diffusion layer provided under the isolation insulating film, preferably an HAD sensor The element isolation means is composed of a required conductivity type diffusion layer having a high concentration equal to or higher than that of the accumulation layer. At this time, the bottom (so-called lower surface) of the isolation insulating film is set to a position equal to or shallower than the pn junction position on the accumulation layer side of the HAD sensor. This configuration makes it easier to extend the charge storage area of the photosensor below the isolation insulating film, increases the area of the charge storage area of the photosensor more effectively than before, and increases white spots and dark current. Without increasing the saturation signal charge amount. Such element isolation means of the present embodiment is also applied between the photodiode and the source / drain region of the transistor, and again, it is possible to increase the area of the charge storage region of the photosensor.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of a CMOS solid-state imaging device according to the present invention. FIG. 1 shows a cross-sectional structure corresponding to the BB line of the pixel region of FIG.
In the CMOS solid-state imaging device 31 according to the first embodiment, a p-type semiconductor well region 33 of a second conductivity type, for example, a p-type semiconductor well region 33 is formed on a first conductivity type, for example, an n-type silicon semiconductor substrate 32. In the region 33, a plurality of unit pixels 2 [2A, 2B, 2C, 2D] composed of a photodiode PD serving as a photoelectric conversion unit and a plurality of MOS transistors are formed, and between each adjacent unit pixel 2 and in the unit pixel. An element isolation region 82 (corresponding to the element isolation region 22 of FIG. 9) serving as an element isolation unit according to the present invention is formed. In FIG. 1, in the p-type semiconductor well region 33, the photodiode PD and transfer transistor Tr1 constituting the pixel 2B, the photodiode PD constituting the pixel 2A, the photodiode PD constituting the pixel 2D, and each pixel 2B, An element isolation region 82 that separates 2A and 2D is formed.

In the same way as described above, the photodiode PD is a first conductivity type for accumulating the second conductivity type p + accumulation layer 39 at the interface with the insulating film 40 on the surface of the silicon substrate and the photoelectrically converted signal charges thereunder. The HAD type sensor composed of the n type charge accumulation region 38 is formed. The p + accumulation layer 39 is formed of a high-concentration p-type diffusion layer of 5 × 10 ¹⁷ cm ⁻³ or more, for example. The n-type charge accumulation region 38 is formed by ion implantation with a dose amount of about 1 × 10 ¹² cm ⁻² , for example.
The transfer transistor Tr1 includes an n-type source / drain region 34 (corresponding to the region 4 (FD) in FIG. 9) serving as a floating diffusion (FD) and an n-type charge storage region 38 of the photodiode PD, and a gate insulation therebetween. A transfer gate electrode 35 (corresponding to the transfer gate electrode 5 in FIG. 9) made of, for example, another crystalline silicon film formed through the film 41 is formed.

  The element isolation region 82 includes a p-type isolation diffusion layer 43 formed by ion implantation in the p-type semiconductor well region 33, and an isolation insulating film formed thereon, in this example, an isolation oxide film (SiO2 film) 44. The The isolation oxide film 44 is formed so that the bottom of the oxide film 44 exists at a position much shallower than the conventional one. The bottom of the isolation oxide film 44 is shallower than the pn junction position 45j formed by the n-type charge storage region 38 and the p + accumulation layer 39, in this example, the pn junction position 45j and the silicon substrate surface 32a. It is formed so as to be located between them. Accordingly, at least in the element isolation region 82 between the pixels 2, the interface state is covered under the isolation oxide film 44 by the p + accumulation layer 39 continuous from the photodiode PD.

  The p + accumulation layer 39 extending continuously below the isolation oxide film 44 functions to suppress the cause of dark current and white spots due to interface states. Since the isolation oxide film 44 is a very shallow oxide film, it does not cause crystal defects due to thermal stress. The p-type isolation diffusion layer 43 also performs isolation in the depth direction between adjacent photodiodes PD. At this time, the p-type isolation diffusion layer 43 may be formed by ion implantation a plurality of times in the depth direction.

On the other hand, the n-type charge accumulation region 38 in the photodiode PD is present in the lateral direction so as to be present under the isolation oxide film 44 and in contact with the p-type isolation diffusion layer 43 in order to increase the saturation signal amount (so-called signal charge amount). Formed to spread. For this reason, the width d1 of the p-type isolation diffusion layer 43 is made as thin as the processing line width allows. The width d1 of the p-type isolation diffusion layer 43 can be 0.05 μm to 10 μm. Note that the isolation width d1 of the p-type isolation diffusion layer 43 may be approximately the same as the width d2 of the trench 14 in the STI region 221 described above. The p-type isolation diffusion layer 43 has a dose amount of about 1 × 10 ¹² cm ^{−2 because} the ion implantation dose amount of the n-type charge storage region 38 is about 1 × 10 ¹² cm ⁻² .

  In the isolation by the element isolation region 82 between the photodiode PD of the pixel 2D and the source / drain region 34 which becomes the floating diffusion (FD) of the readout transistor Tr1 of the pixel 2B, the photodiode PD side is completely the same as described above. Can be the same structure. That is, the p + accumulation layer 39 is formed under the isolation oxide film 44 so as to extend. On the floating diffusion (FD) side, the P + accumulation layer 39 may or may not be formed below and on the side surface of the isolation oxide film 44.

  According to the CMOS solid-state imaging device 31 according to the first embodiment, the element isolation region 82 is configured by the p-type isolation diffusion layer 43 and the isolation oxide film 44 thereon. By this p-type isolation diffusion layer 43, between the photodiodes PD of the adjacent pixels 2 or between the photodiode PD of the adjacent pixels 2 and the source / drain regions 34 of the MOS transistors, and the source / drain regions of the MOS transistors of the adjacent pixels 2 There is a substantial separation between them. Further, by providing the isolation oxide film 44, even when a gate electrode or wiring is extended (so-called) on the isolation oxide film 44, a parasitic channel such as a depletion or an inversion layer is provided immediately below the isolation oxide film 44. Induction of the layer can be prevented, and element isolation can be reliably performed.

  Then, the n-type charge storage region 38 of the photodiode PD is formed under the isolation oxide film 44 so as to be in contact with the p-type isolation diffusion layer 43, so that the area of the n-type charge storage region is expanded and the saturation signal is increased. The amount can be greatly increased compared to conventional STI separation schemes. Further, the isolation oxide film 44 is formed so that the bottom thereof is shallower than the pn junction position 45j on the p + accumulation layer 39 side, and on the photodiode PD side, below the isolation oxide film 44, the p + accumulation is performed. Since the layer 39 is formed to be extended, dark current and white spots can be suppressed. Therefore, the effective opening of the photodiode PD can be increased without increasing the dark current and the white point, and the saturation signal amount can be greatly increased.

  The isolation oxide film 44 may not be formed deeper than the silicon substrate surface. When the isolation oxide film 44 is a thin oxide film, the impurity concentration in the p-type region immediately below the isolation oxide film 44 is increased. As a result, even if the isolation oxide film 4 is made thinner, the generation of a parasitic channel can be prevented immediately below the isolation oxide film 44. The film thickness of the isolation oxide film 44 is related to the surface concentration of the p-type region immediately below the isolation oxide film 44, but can be 1 nm to 1000 nm.

Here, the reason other than the above will be described in which the bottom depth of the isolation oxide film 44 is set in the vicinity of the pn junction position 45j. Incidentally, as shown in FIG. 11A, in the case of the conventional STI isolation method, if the n-type charge storage region 18 is extended to the depth direction along the side surface of the STI region 81, that is, the pn junction is extended to the depth direction, The apparent capacity of the n-type charge accumulation region 18 is increased, and a larger amount of signal charge can be accumulated. However, particularly in the photodiode PD having the HAD structure, it is necessary to completely read out the much accumulated signal charge. However, as shown in FIG. 11B, a potential dip 24 that becomes deeper due to the three-dimensional effect occurs along the STI region 221 in the potential distribution 23 in the HAD sensor, and unread reading of signal charges occurs. Therefore, it becomes easier to read the signal charge when the pn junction j of the HAD sensor is extended as far as possible to the element isolation region.
In the first embodiment, since the pn junction of the HAD sensor can be formed to extend horizontally up to the element isolation region 82, the saturation signal charge amount is increased without any harmful effects, and this signal charge is completely read out without being left unread. be able to.

  Next, FIG. 2 shows a second embodiment of the CMOS solid-state imaging device according to the present invention. FIG. 2 shows a cross-sectional structure of the main part of the pixel region similar to that described above, and portions corresponding to those in FIG.

A CMOS solid-state imaging device 51 according to the second embodiment includes a device isolation region 83 (see FIG. 9) that separates a source / drain region 49 of a floating diffusion (FD) or other MOS transistor from a photodiode PD of an adjacent pixel. (Corresponding to the element isolation region 22) is composed of the first p-type isolation diffusion layer 43, the second p-type isolation diffusion layer 47 thereon, and the isolation oxide film 44 thereon. Second isolation diffusion layer 47 is formed to have an impurity concentration equal to or higher than that of p + accumulation layer 39.
The other configuration is the same as that of FIG.

  According to the CMOS solid-state imaging device 51 according to the second embodiment, the separation capability can be further increased by providing the second p-type separation diffusion layer 47. That is, in the element isolation region between the source / drain region 49 of the floating diffusion (FD) or other transistor and the photodiode PD, the gate electrode 48 runs on the isolation oxide film 44. For this reason, when there is only the first p-type isolation diffusion layer 43 in the region where the P + accumulation layer 39 is not present, the surface of the first p-type isolation diffusion layer 43 is easily inverted by the potential of the gate electrode 48. This makes it easier for charge to leak into the photodiode PD. However, in the present embodiment, the formation of the inversion layer is prevented by forming the second p-type isolation diffusion layer 47 having a high concentration under the isolation oxide film 44 where the potential to invert the surface is applied. Separation ability is improved. In addition, the same effects as in the first embodiment can be obtained, for example, the area of the effective photodiode PD can be increased without increasing the dark current and the white point, and both saturation signals can be significantly increased.

  Note that the effect of blocking the inversion layer can be achieved, for example, by forming the isolation oxide film 44 thick, but there is a drawback that it becomes difficult to process the isolation oxide film. In the second embodiment, the isolation oxide film 44 can be formed relatively thin, and the isolation oxide film 44 can be easily processed.

  FIG. 3 shows a third embodiment of a CMOS solid-state imaging device according to the present invention. FIG. 3 shows a cross-sectional structure of the main part of the pixel region similar to that described above, and parts corresponding to those in FIG.

  A CMOS solid-state imaging device 52 according to the third embodiment includes a p-type isolation diffusion layer between a source / drain region 49 of a floating diffusion (FD) or other MOS transistor and a photodiode PD of an adjacent pixel. An element isolation region 84 (corresponding to the element isolation region 22 in FIG. 8) is formed of 43 and an isolation oxide film 44 thereon.

  In the present embodiment, at least when the impurity concentration of the floating diffusion (FD), the source / drain region 49 of another MOS transistor, and the p-type isolation diffusion layer 43 in the element isolation region is high, at least the isolation oxidation. In the element isolation region 84 where the gate electrode does not run on the film 44, a separation region 53 is formed so that the source / drain region 34 can be separated from the p-type isolation diffusion layer 43 by a required distance. That is, the separation region 53 is formed so that the p-type semiconductor well region 33 exists between the source / drain region 49 and the p-type isolation diffusion layer 43.

In this configuration, when the isolation oxide film 44 is thick, the self-line source / drain regions 39 can be formed using the isolation oxide film 44 as a mask. When the isolation oxide film 44 is thin, the source / drain region 39 can be formed through a resist mask.
The other configuration is the same as that of FIG.

  According to the CMOS solid-state imaging device 52 according to the third embodiment, by providing the separation region 53 between the source / drain region 49 and the element isolation region 84, the source / drain region 49 and the p-type isolation diffusion layer are provided. Even if the concentration of 43 is high, it is possible to prevent the junction electric field of the source / drain region 9 from increasing. In addition, the same effects as those of the first embodiment can be obtained, for example, the area of the effective photodiode PD can be increased without increasing the dark current and white point, and the saturation signal amount can be significantly increased.

  In the above example, the isolation insulating film 44 is formed of a silicon oxide film, but the isolation insulating film 44 can also be formed of an insulating film including a silicon oxide film and a silicon nitride film.

As another embodiment of the present invention, although not shown, the surface concentration of the p-type isolation diffusion layer 43 immediately below the isolation oxide film 44 in the element isolation region is set to be equal to or higher than the concentration of the p + accumulation layer 39. In addition, the concentration of the p-type isolation diffusion layer 43 can be reduced in the depth direction. In particular, the portion of the p-type separation diffusion layer 43 corresponding to the separation portion from the n-type charge storage region 38 except for the surface can be configured to have the highest concentration.
By gradually decreasing the concentration of the p-type isolation diffusion layer 43 in the depth direction, the lateral diffusion of the p-type isolation diffusion layer 43 can be suppressed, and the reduction in the area of the photodiode can be prevented. Can do.

Next, a fourth embodiment of the CMOS solid-state imaging device according to the present invention will be described.
In the element isolation region of the present embodiment, the isolation oxide film 44 necessary for element isolation and the concentration of the p-type isolation diffusion layer 43 therebelow are determined because the gate electrode in the pixel is on the isolation oxide film 44. It is about to get on. FIG. 4A shows a cross-sectional structure of a main part of a CMOS solid-state imaging device according to the fourth embodiment. In the present embodiment, the photodiode PD and the MOS transistor of the pixel adjacent to the photodiode PD are separated from the element isolation region 85 (the element isolation region of FIG. 9) by the p-type isolation diffusion layer 43 and the isolation oxide film 44 thereon. 22). That is, the n-type charge accumulation region 38 is in contact with the p-type isolation diffusion layer 43 so that it exists under the isolation oxide film 44, and the n-type source / drain region 49 is in contact with the p-type isolation diffusion layer 43. . In this case, the p + accumulation layer 39 of the photodiode PD is formed extending under the isolation oxide film 44. In a MOS transistor, it is formed by a pair of source / drain regions and a gate electrode on a gate insulating film. A gate electrode is formed on the isolation oxide film 44.
Since other configurations are the same as those in FIG. 1, the corresponding parts are denoted by the same reference numerals and description thereof is omitted.

  In the element isolation region 85, if the isolation oxide film 44 is thicker and the concentration of the p-type isolation diffusion layer 43 is higher, the isolation characteristics are improved. However, in this case, it becomes difficult to form the isolation oxide film 44 and to process the gate electrode. If the concentration of the p-type isolation diffusion layer 43 is high, the n-type charge storage region 38 may be eroded by the diffusion of p-type impurities, and the saturation signal amount may be reduced.

  Therefore, in the present embodiment, an element isolation region 85 in which the isolation oxide film 44 is thin and the concentration of the p-type isolation diffusion layer 43 is low is formed, and pixel photoelectric conversion is performed as a pixel driving condition of the CMOS solid-state imaging device. The potential of the source / drain regions of the MOS transistors of other pixels adjacent to the photoelectric conversion portion of the pixel that accumulates charges through the element isolation region is not set to 0 V within the charge accumulation period in which charges are accumulated in the portion. . For example, the voltage applied to the source / drain region should not be 0V. The thickness of the isolation oxide film 44 can be as thin as 1 nm to 1000 nm. That is, the isolation oxide film 44 only needs to have a thickness that prevents current from flowing through the isolation oxide film due to a potential difference between the polysilicon electrode and the substrate. It is sufficient if the oxide film thickness is thick so that the electric field intensity is usually less than 5 MV / cm. If it is 2.5V, the film thickness can be about 5 nm.

  FIG. 4B shows a potential distribution when the source / drain region becomes 0 V for some reason. Since the ground potential is applied to the p-type isolation diffusion layer 43, the potential immediately below the element isolation region is 0V. Therefore, when a depletion or inversion layer is induced immediately below the isolation oxide film by the potential of the gate electrode disposed on the isolation oxide film, the n-type charge accumulation of the photodiode PD that is accumulating charges from the source / drain regions There is a possibility that electrons (charges) flow to the region. In the CMOS solid-state imaging device in which the potential of the source / drain region is 0 V, the thickness of the isolation oxide film in the element isolation region is increased, the concentration of the p-type isolation diffusion layer 43 is increased, and a depletion or inversion layer is formed. It is necessary not to be induced. Incidentally, an example in the case where the source / drain region becomes 0V will be described. For example, the amplification transistor Tr3 of the pixel shown in FIG. 9 is precharged for resetting the vertical signal line before reading out or resetting the charge. At that time, the vertical signal line 10 is lowered to the ground (GND) level, and the source / drain region 8 connected to the vertical signal line 10 becomes 0V.

On the other hand, FIG. 4C shows the potential distribution of the present embodiment. The potential of the source / drain region is higher than 0V, for example, about +0.2 to 0.3V, or 0. Even a few volts are set to a positive potential. Since the ground potential is applied to the p-type isolation diffusion layer 43, the potential immediately below the element isolation region is 0V. By having such a potential distribution that a potential barrier is formed immediately below the element isolation region, the silicon region immediately below the isolation oxide film is depleted or inverted by the potential of the gate electrode disposed on the isolation oxide film. Is induced, electrons (charges) are prevented from leaking from the source / drain regions of the transistors of the adjacent pixels to the n-type charge accumulation region in the charge accumulation period of the n-type charge accumulation region 38. Therefore, the isolation oxide film in the element isolation region can be made thin and the concentration of the p-type isolation diffusion layer can be reduced. For example, when the voltage of the source / drain region is 0.5 V, the isolation oxide film 44 can be separated by setting the thickness of the isolation oxide film 44 to 50 nm and the concentration of the p-type isolation diffusion layer 43 to 1 × 10 ¹³ cm ⁻² . Under this condition, there is no problem in the processing of the isolation oxide film 44, and the junction electric field in the source / drain region is weak. In addition, since the concentration of the p-type isolation diffusion layer can be lowered, the n-type charge accumulation region is not eroded by impurity diffusion, and an increase in the saturation signal amount can be maintained.

  Next, an embodiment of a method for manufacturing a CMOS solid-state imaging device according to the present invention will be described with reference to FIGS. For the sake of clarity, the figure shows a region including separation between photodiodes and separation between the photodiode and source / drain regions.

First, as shown in FIG. 5A, a silicon substrate 30 in which a second conductivity type p-type semiconductor well region 33 is formed on a first conductivity type n-type silicon substrate 32 is provided. After a silicon oxide film 40 is formed on the surface of the silicon substrate 30 and a silicon nitride film 55 is grown thereon, an n-type charge storage region is formed in a region that becomes a photodiode through a resist mask (not shown), for example. 38 is formed by ion implantation. For example, n-type impurities are ion-implanted at a dose of about 1 × 10 ¹² cm ⁻² to form the n-type charge storage region 38. At this time, as the n-type impurity, As is suppressed in the heat treatment diffusion, but phosphorus (P) can also be used. Further, when forming the n-type charge storage region 38, the portion adjacent to the photodiode is turned back by the p-type impurity to form the p-type isolation region of the element isolation region. Therefore, the n-type charge storage region is formed in a continuous pattern. You can also. In this example, the n-type charge accumulation region 38 is formed continuously in adjacent pixels.

  Next, as shown in FIG. 5B, the silicon nitride film 55 in the portion where the element isolation region is to be formed, that is, the portion between the photodiodes of the adjacent pixels, and the portion between the photodiode of the adjacent pixels and the source / drain regions. Then, the lower silicon oxide film 40 is selectively removed by etching to form an opening 56.

Next, as shown in FIG. 6C, a shallow groove 57 is dug in the surface of the silicon substrate corresponding to the opening 56 by a shallow etching process using the silicon nitride film 55 and the silicon oxide film 450 as a mask. The groove depth at this time is assumed to be shallower than the pn junction depth of the HAD structure described above. Here, when a necessary silicon oxide film can be formed, the surface of the silicon substrate may not be dug. Next, p-type impurities are ion-implanted to form a second p-type isolation diffusion layer 47 for element isolation on the bottom surface of the trench 57. The second p-type isolation diffusion layer 47 is formed, for example, by ion implantation of boron (B) at a dose amount of 2 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² and an implantation energy number of keV to 50 keV.

  Next, as shown in FIG. 6D, below the second p-type isolation diffusion layer 47, the first p-type isolation diffusion layer 43 [43a, 43b is narrower than the second p-type isolation diffusion layer 47. ] Is formed by ion implantation. At this time, ion implantation is performed in a plurality of depth directions. In this example, the ions are divided and implanted twice in the depth direction, a p-type isolation diffusion layer 43a having a high concentration is formed in the shallower side, and a p-type isolation diffusion layer 43b having a low concentration is formed in the deeper side.

  Next, as shown in FIG. 7E, an isolation oxide film is formed on the entire surface so as to fill the groove 57 and the opening 56 by, for example, HDP-CVD (High Density Plasma Chemical Vapor Deposition). A silicon oxide film 44 'is formed.

  Next, as shown in FIG. 7F, the silicon oxide film 44 'is planarized to the surface of the silicon nitride film 55 by, for example, a CMP (chemical mechanical polishing) method, and the isolation oxide film 44 embedded in the trench 57 and the opening 56 is formed. leave. An isolation region 84 is formed by the isolation oxide film 44, the second p-type isolation diffusion layer 47, and the first p-type isolation diffusion layer 43 [43a, 43b].

  Next, as shown in FIG. 8, the silicon nitride film 55 is removed, and thereafter, the source / drain regions 49 of the MOS transistor and the p + accumulation layer 39 of the photodiode are formed by a normal process. The depth of the source / drain region 49 is the same as the depth of the p + accumulation layer 39 or is formed deeper than the depth of the p + accumulation layer 39 as in the source / drain region 34 of FIG. Any of the cases can be. The p + accumulation layer 39, the n-type charge storage region 38, the p-type semiconductor well region 33, and the n-type silicon substrate 32 form a photodiode PD having an HAD structure. Thereafter, a gate insulating film and a gate electrode are formed to form corresponding MOS transistors. In FIG. 8, source / drain regions 49 are formed by ion implantation using the isolation oxide film 44 as a part of the mask. As a result, a target CMOS solid-state imaging device is obtained.

  As another embodiment of the manufacturing method, after forming the opening 56 in the silicon nitride film 55 and the silicon oxide film 40 in the step of FIG. 5B, no groove is formed on the surface of the silicon substrate, and the silicon nitride film is formed before ion implantation. The silicon substrate surface is oxidized using 55 as a mask. By this step, a shallow groove 57 with little surface damage can be formed in the silicon substrate. After the surface oxide film is left, the target CMOS solid-state imaging device can be manufactured by the same process as described above.

According to the method for manufacturing a CMOS solid-state imaging device according to the above-described embodiment, the silicon oxide film 44 ′ is embedded in the opening 56 of the silicon nitride film 55, the silicon nitride film 55 is removed, and the surface is the surface of the silicon substrate 30. By forming the isolation oxide film 44 with a more protruding silicon oxide film, the isolation oxide film 44 with a small area can be formed easily and accurately.
7E and 7F, a silicon oxide film 44 'is formed on the silicon nitride film 55 so as to fill the opening 56, and then the surface of the silicon nitride film 55 is planarized by CMP to control the film thickness. The formed isolation oxide film 44 can be formed easily and accurately.
After the opening 56 is formed, the surface of the silicon substrate facing the opening 56 is slightly selectively etched to form a shallow groove 57 and bury the silicon oxide film 44 ', thereby separating the lower surface at a position lower than the silicon substrate surface. An oxide film 44 can be formed.

  A high-concentration p-type region 47 is formed on the surface of the silicon substrate facing the opening 56 in the step of FIG. 6C, and the p-type separation diffusion layer 43 [43a is formed by a plurality of ion implantations so that the concentration decreases in the depth direction in the step of FIG. , 43b], the p-type isolation diffusion layer 43 having a high surface concentration and a low concentration in the substrate depth direction can be easily formed.

Since the n-type charge storage region 38 is formed before the opening 56 and the silicon oxide film 44 are formed, the n-type charge storage region 38 is finally extended under the isolation oxide film 44 to form the p-type isolation diffusion layer 43. It can be formed in contact.
Before ion implantation of the p-type region 47 and the p-type diffusion layers 43 and 343b, the silicon substrate surface is oxidized using the silicon nitride film as a mask to form a shallow silicon groove 57 with little surface damage. Can do.

  In the above example, the shallow oxide film 44 is formed after forming the shallow groove 57 on the surface of the silicon substrate using the silicon nitride film 55 as a mask. However, as another embodiment, although not shown, the silicon substrate 30 is selected. The isolation oxide film 44 can be formed by locally oxidizing the surface of the silicon substrate facing the opening 56 using the non-oxidizing film, for example, the silicon nitride film 5 as a mask, without digging the groove 57 by etching.

  According to the CMOS solid-state imaging device shown in FIG. 8 obtained by the above manufacturing method, as described above, since the substantial device isolation is performed by the first p-type isolation diffusion layer 43, the isolation width is the first p-type. Only the mold isolation diffusion layer 43 has a width, so that the area of the photodiode PD in the pixel can be increased, and the saturation signal amount in the fine pixel can be increased. Since the first p-type separation / diffusion layer 43 is used, the occurrence of white scratches and dark current due to crystal defects is suppressed.

  Since the isolation insulating film 44 is formed on the first p-type isolation diffusion layer 43 so as to protrude above the silicon oxide film 40, even if a part of the gate electrode is extended on the isolation insulating film 44. There is no depletion or inversion layer induced directly under the isolation insulating film 44, and the inter-pixel isolation is ensured.

  The isolation insulating film 44 in the element isolation region 86 is formed at a position equivalent to or shallower than the pn junction position on the accumulation layer side on the photoelectric conversion portion side, that is, the lower surface of the isolation insulating film 44 is formed. By setting the shallow position below the pn junction position, the charge storage region 38 of the photodiode PD can be formed up to the bottom of the isolation insulating film 44, and the effective area of the charge storage region 38 can be increased. That is, since the charge storage region 38 of the photodiode PD exists under the isolation oxide film 44, the area of the charge storage region 38 can be expanded and the saturation charge amount can be increased. Since the second p-type isolation diffusion layer 47 having a high concentration is formed under the isolation oxide film 44, it is possible to improve the isolation capability and suppress dark current and white spots.

  2 [2A to 2D] .. Pixels, 31, 51, 52..CMOS solid-state imaging device, 30..Semiconductor substrate, 32..n-type semiconductor substrate, 32a..Semiconductor surface, 33..p-type semiconductor well region PD PD photodiode Tr1 Read transistor 34 (FD) Source drain region (floating diffusion) 35 Gate electrode 38 Charge accumulation region 39 Accumulation layer 41..Gate insulating film, 40..Insulating film, 43..p-type isolation diffusion layer, 44..isolation insulating film, 82 to 85..element isolation region, 45j..pn junction position, 49..source. Drain region, 53 .. spaced region, 55 .. silicon nitride film, 56 .. opening, 57 .. groove

Claims (4)

A first insulating film on the surface of the semiconductor substrate;
Formed by a diffusion layer and a second insulating film thereon, and having element isolation means for separating adjacent pixels,
The second insulating film is formed at a position that is equal to or shallower than the position of the pn junction on the accumulation layer side of the photoelectric conversion portion that constitutes the pixel, and from the first insulating film. A solid-state image sensor formed above. The solid-state imaging device according to claim 1, wherein the second insulating film is formed by a CVD method. The solid-state imaging device according to claim 2, wherein the second insulating film is formed by an HDP-CVD method. The solid-state imaging device according to claim 1, wherein the second insulating film is formed by embedding an oxide film.

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