JP2008153566A - Solid-state imaging apparatus, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus in which STIs are used for element isolation regions, wherein dark current and occurrence of a white blemish are reduced and achieves storage charge amount increase. <P>SOLUTION: The solid-state imaging apparatus includes an imaging region formed on a substrate composed of silicon and containing a photoelectric conversion part, a trench isolation formed at least a part of a portion that surrounds the photoelectric conversion part on the substrate, and a MOS transistor formed in a region electrically isolated from the photoelectric conversion part by the trench isolation in the imaging region, wherein the side part and the portion surrounding the bottom part of the trench isolation contain indium which is an impurity of a conductivity type different from that of an electric charge storage region of the photoelectric conversion part. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device in which an imaging region having a plurality of pixels is provided on a semiconductor substrate, a manufacturing method thereof, and a camera.

  A MOS (Metal Oxide Semiconductor) type solid-state imaging device is an image sensor that reads out a signal accumulated in a photodiode constituting each pixel by an amplifier circuit including a MOS transistor. This MOS type solid-state imaging device has advantages in that it operates at a low voltage, can read out charges at a high speed, and can be integrated into one chip with a peripheral circuit.

  Furthermore, in recent years, MOS type solid-state imaging devices have the potential to expand the market by reducing the cell size and developing technology that improves the basic performance of imaging devices such as a wide dynamic range.

  The imaging region in a general MOS type solid-state imaging device is composed of a photodiode formed on a silicon substrate, a floating diffusion, a MOS type transistor, and an element isolation region that electrically isolates these elements. In general, STI (shallow trench isolation) is formed as an element isolation region.

  The element isolation region made of STI is formed by forming a recess in the silicon substrate by etching and filling the recess with an oxide film in order to satisfy the element isolation characteristics. In this etching, unnecessary charges generated even in the dark when no light is irradiated increase due to etching damage, and noise increases. Further, when the cell size is reduced, the B (boron) injection region injected into the side wall portion of the STI is expanded by thermal diffusion, so that the lateral region of the photodiode is narrowed, and the number of stored electrons is reduced. Furthermore, noise characteristics, that is, white scratches and dark current characteristics are deteriorated due to unnecessary charges generated at the STI interface entering the photodiode.

  As a method for solving the problem when the element isolation region made of STI as described above is formed, solid-state imaging devices according to first to third conventional examples described below have been proposed.

  FIG. 7 shows a cross-sectional configuration including a photodiode portion in the solid-state imaging device according to the first conventional example (see, for example, Patent Document 1).

  As shown in FIG. 7, a P-type buried region 104 is formed on the surface of an N-type charge storage region 103 formed in a P-type semiconductor well region 102 on the semiconductor substrate 101. An element isolation layer 111 made of an insulating layer is formed adjacent to the photodiode in the groove formed in FIG. The element isolation layer 111 is composed of a wide upper portion 109 and a narrow lower portion 110, and a P-type region 112 is formed around the narrow lower portion 110. In the figure, a floating diffusion 105, a gate insulating film 106, a read gate electrode 107, a reset gate electrode 108, a gate electrode 113, a via wiring 114, and a metal wiring 115 are further shown.

  According to the solid-state imaging device shown in FIG. 7, the photodiode is electrically isolated from other peripheral elements on the surface of the semiconductor substrate 101, and the width of the element isolation region can be reduced. Therefore, even when the pixel size is reduced, a sufficient amount of accumulated charge can be secured.

  FIG. 8 shows a cross-sectional configuration including a photodiode portion in the solid-state imaging device according to the second conventional example (see, for example, Patent Document 2).

  As shown in FIG. 8, a P-type well region 202 on a semiconductor substrate 201 is a buried photodiode including a first impurity region 206 as a surface inversion layer and a second impurity region 204 therebelow. A photoelectric conversion unit 215 is formed. Around the photoelectric conversion portion 215, a P-type region 205, an N-type region 203, and a P-type region 207 functioning as element isolation are formed. In the figure, an insulating film 208, a transfer gate electrode 209, a light shielding film 210, an interlayer insulating film 211, an antireflection film 212, and a surface protective film 213 are shown.

  According to the solid-state imaging device illustrated in FIG. 8, the first impurity region 206 constituting the embedded photodiode can reduce the influence of dark current and white scratches caused by crystal defects near the surface of the photoelectric conversion unit 215. By introducing indium having a smaller diffusion coefficient than conventional boron into the surface inversion layer, a steep impurity distribution can be maintained even after the heat treatment step after ion implantation. For this reason, an embedded photodiode having a surface inversion layer that is shallow and densely distributed from the surface of the photodiode is formed, so that it is possible to improve the saturation charge amount of the photodiode and to suppress the occurrence of dark current and white scratches. .

  FIG. 9 shows a cross-sectional configuration including a photodiode portion in a solid-state imaging device according to a third conventional example (see, for example, Patent Document 3).

As shown in FIG. 9, a P-type silicon layer 310, a P-type plug well 310, and a P-type surface side well 311 are formed on a P-type deep well 308 on the semiconductor substrate 301. An N-type silicon layer 318 is formed on the P-type silicon layer 310, and a P ⁺ -type channel stop layer 306 and an N-type silicon layer 319 are formed so as to cover the N-type silicon layer. A silicon oxide film 305 and an element isolation structure (STI) 307 are formed on the P ⁺ type channel stop layer 306.

According to the solid-state imaging device shown in FIG. 9, the photoelectric conversion unit 320 composed of the N-type silicon layer 318 and the P ⁺ -type silicon layer 319 is electrically separated by the element isolation structure 307, and in the vicinity of the element isolation interface. By forming the P-type region into which BF ₂ is implanted, the number of white scratches caused by crystal defects at the element isolation interface can be reduced.
JP 2005-191262 A JP 2006-186262 A JP 2004-39832 A

  However, the solid-state imaging devices according to the first to third conventional examples have the problems described below.

  First, in the solid-state imaging device according to the first conventional example shown in FIG. 7, the P-type region 112 is formed around the lower part 110 constituting the element isolation layer 111. Is not connected. For this reason, dark current from the interface of the element isolation layer 111 is generated at the bottom surface of the upper part 109 constituting the element isolation layer 111, that is, the boundary region between the P-type buried region 104 and the P-type region 112, and the characteristic Deterioration occurs. Further, since stress is concentrated on the edge of the upper portion 109 constituting the element isolation layer 111 and is not covered with the P-type region, further dark current is generated. Then, as a method for manufacturing the element isolation layer 111, the upper portion 109 of the element isolation layer 111 is formed using a lithography method and a dry etching method, and the lower portion constituting the element isolation layer 111 again using a lithography method and a dry etching method. 110, the formation position of the lower portion 110 is shifted due to variations in resist pattern dimensions in lithography and mask misalignment, and the size and position of the lower portion 110 constituting the element isolation layer 111 are between pixels and between wafers. It is different. As a result, performance variations in the number of stored electrons and sensitivity occur, and a high-performance solid-state imaging device cannot be realized. Furthermore, since the lithography process needs to be performed twice, the TAT becomes longer and the cost is increased.

  Further, in the solid-state imaging device according to the second conventional example shown in FIG. 8, in order to narrow the element isolation region with the adjacent pixels as the cell size of the MOS type solid-state imaging device is reduced, the STI is used. Since a structure is required, the improvement of dark current and white scratch characteristics generated at the STI interface cannot be expected only by introducing In to the surface inversion layer. Furthermore, a sufficient amount of indium for reducing the increase in the number of white scratches caused by crystal defects generated on the surface does not dissolve in silicon under the heat treatment conditions.

  Further, in the solid-state imaging device according to the third conventional example shown in FIG. 9, since B atoms are used when forming the P-type, B atoms having a light mass have a long diffusion distance due to heat, and the narrow channel effect. As a result, the number of accumulated charges decreases.

  In view of the above, an object of the present invention is a solid-state imaging device using STI as an element isolation region, which reduces the occurrence of dark current and white scratches, and realizes an increase in the number of accumulated charges, and its It is to provide a manufacturing method.

  In order to solve the above problems, a solid-state imaging device according to a first embodiment of the present invention is formed on an upper part of a substrate made of silicon, and includes an imaging region including a photoelectric conversion unit, and a portion surrounding the photoelectric conversion unit in the substrate A trench element isolation formed in at least a part of the MOS transistor, and a MOS transistor formed in a region of the imaging region that is electrically isolated from the photoelectric conversion unit by the trench element isolation. The portion surrounding the periphery of the bottom portion contains indium that is an impurity of a conductivity type different from the conductivity type of the charge storage region of the photoelectric conversion portion.

  According to the solid-state imaging device according to the first embodiment of the present invention, when the trench element isolation of the STI structure is used for the miniaturization of the cell size of the MOS type solid-state imaging device, the crystal defect near the trench element isolation interface is caused. The increase in the number of white scratches caused can be suppressed, and since the indium diffusion coefficient is low, the reduction in the number of charges accumulated in the photoelectric conversion portion due to the narrow channel effect can be improved.

  In the solid-state imaging device according to the first aspect of the present invention, the peak value of phosphorus or arsenic, which is a conductive impurity in the charge storage region of the photoelectric conversion unit, is formed between the peak value of indium and the trench element isolation interface. It has an unstructured structure.

  According to this structure, an increase in the number of white scratches caused by crystal defects near the trench element isolation interface can be suppressed, and P-type indium and N-type phosphorus or arsenic are formed in the region along the trench element isolation interface. A depletion layer capacitance is formed, and an increase in the amount of accumulated charge photoelectrically converted and an improvement in sensitivity are realized.

  In the solid-state imaging device according to the first aspect of the present invention, the peak value of phosphorus or arsenic, which is a conductive impurity in the charge storage region of the photoelectric conversion unit, is formed between the peak value of indium and the trench element isolation interface. Has a structure.

  According to this structure, phosphorus or arsenic has a mass number smaller than that of indium and has a wide dispersion during implantation. Further, in a heat treatment of about 900 ° C. or less, the diffusion coefficient of phosphorus and arsenic is larger than that of indium. A depletion layer with an N-type region of phosphorus or arsenic is formed adjacent to the type region. Furthermore, the electric field strength in the reverse bias characteristic of the PN junction can be reduced, the recombination current can be reduced, and the white scratch and dark current characteristics can be reduced.

  In the solid-state imaging device according to the first aspect of the present invention, the concentration of indium contained in the portion located at the bottom in the trench element isolation is higher than the concentration of indium contained in the portion located in the side in the trench element isolation. .

  With this configuration, since the spread of the depletion layer formed by the PN junction does not reach the trench element isolation interface, white scratches due to crystal defects can be reduced.

  The solid-state imaging device according to the second aspect of the present invention is formed on an upper part of a substrate made of silicon, and is formed on at least a part of an imaging region including a photoelectric conversion unit and a portion of the substrate surrounding the photoelectric conversion unit. Trench element isolation, a MOS transistor formed in a region of the imaging region that is electrically isolated from the photoelectric conversion unit by trench element isolation, and a floating diffusion layer to which charges accumulated in the photoelectric conversion unit are transferred An electrical isolation region containing indium is further provided between the photoelectric conversion unit and the floating diffusion layer.

  According to the solid-state imaging device according to the second aspect of the present invention, since the spread due to thermal diffusion of the P-type region that separates the photoelectric conversion unit and the floating diffusion layer can be reduced, the amount of accumulated charges increases. Also, since the spread of the indium implantation profile is small, the depletion layer capacitance can be increased and the conversion gain can be improved.

  In the solid-state imaging device according to the first or second aspect of the present invention, the upper part of the charge storage region of the photoelectric conversion unit contains indium which is an impurity having a conductivity type different from the conductivity type of the charge storage region.

  With this configuration, the N-type region of the charge storage region of the photoelectric conversion unit has a short indium diffusion distance. Therefore, even if the P-type region above the charge storage region and the trench element isolation interface layer are spread by heat, the charge storage region is Sufficiently secured. That is, a structure in which the accumulated charge amount is difficult to reduce by heat treatment is realized.

  In a method for manufacturing a solid-state imaging device according to one aspect of the present invention, an opening is formed in a hard mask film or a resist film by forming a hard mask film or a resist film on a substrate made of silicon and performing patterning. A step (a), a step (b) of forming a trench groove in the substrate by etching using a hard mask film or a resist film as a mask, and a side of the trench groove in the substrate after the step (b), and A step (c) of performing ion implantation of indium and an ion implantation of arsenic or phosphorus at the bottom, and a step (d) of forming trench element isolation in the trench groove after the step (c) are provided.

  As a result, the PN junction formed in the vicinity of the trench element isolation is formed by self-alignment without the need for a lithography process, so that variation in the amount of accumulated charge due to mask displacement for each photoelectric conversion unit can be reduced. .

  In the method for manufacturing a solid-state imaging device according to an embodiment of the present invention, in the step (c), the ion implantation energy of indium is smaller than the ion implantation energy of phosphorus or arsenic.

  Thereby, it is possible to prevent the depletion layer from spreading to the vicinity of the trench element isolation interface, and to reduce the number of white defects caused by crystal defects at the trench element isolation interface.

  According to the solid-state imaging device and the manufacturing method of the present invention, it is possible to reduce the number of white defects caused by crystal defects near the interface of the element isolation region and increase the number of accumulated charges even when the element isolation region of the STI structure is used. The solid-state imaging device and the manufacturing method thereof can be realized.

  First, a basic circuit configuration common to the MOS type solid-state imaging device according to each embodiment of the present invention will be described.

  FIG. 1 shows a basic circuit configuration of a MOS type solid-state imaging device.

  As shown in FIG. 1, an imaging region 17 in which a plurality of pixels 16 are arranged in a matrix, a vertical shift register 18 for selecting pixels, a horizontal shift register 19 for outputting a signal, a vertical shift register 18 and a horizontal A timing generation circuit 20 that supplies necessary pulses to the shift register 20 is provided on one substrate (not shown).

  Each pixel 16 arranged in the imaging region 17 includes a photodiode (photoelectric conversion unit) 11 that performs photoelectric conversion and a MOS transistor that accompanies the photodiode 11, and the electric charge photoelectrically converted by the photodiode 11 is transferred by the transfer transistor 12. And transferred to a floating diffusion part (not shown) which is a floating diffusion layer. The floating diffusion is shared with the source of the reset transistor 13 whose drain is connected to the power supply 23. The gate of the amplifying transistor 14 whose drain is connected to the power supply 23 is connected to the floating diffusion. The source of the amplification transistor 14 is connected to the drain of the selection transistor 15, and the source of the selection transistor 15 is connected to the output signal line 25.

  The gate of the transfer transistor 12, the gate of the reset transistor 13, and the gates of the selection transistor 15 are connected to the output pulse line 21, the output pulse line 22, and the output pulse line 24 from the vertical shift register 18, respectively.

  Hereinafter, specific features of the MOS solid-state imaging device according to the present invention will be described separately for each embodiment.

(First embodiment)
The solid-state imaging device according to the first embodiment of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a cross-sectional structure of a portion including a photodiode and an active region in the solid-state imaging device according to the first embodiment of the present invention. Note that wirings and interlayer films formed on the semiconductor substrate are omitted.

As shown in FIG. 1, the photodiode 30 that is a photoelectric conversion unit has a P ⁺ NP ⁻ type structure from the surface of the silicon substrate 31, and the P ⁺ NP ⁻ type structure is an N type. A P ⁺ type surface layer 36 (surface dark current suppression region) provided on the uppermost surface of the silicon substrate 31, an N type silicon layer 33, which is a charge storage region provided in order below the P ⁺ type surface layer 36, and And a P ⁻ type silicon layer 34.

When the light incident on the photodiode 30 reaches the PN junction interface, it is photoelectrically converted to generate holes and electrons. A signal charge (electrons) corresponding to the amount of incident light is generated between the N-type silicon layer 33 and the P ⁺ -type surface layer 36, and between the N-type silicon layer 33 and the P ⁻ -type silicon layer 32. The accumulated depletion layer region is mainly accumulated in the depletion layer region formed between the P ⁺ type side wall layer 38 (side wall dark current suppression region) and the N type silicon layer 33. The P ⁺ type surface layer 36 provided on the uppermost surface electrically mixes the charge generated randomly due to thermal energy or the like due to crystal defects on the surface of the photodiode 30 with the accumulated charge obtained by photoelectric conversion. Blocked by barriers.

The charges accumulated in the photodiodes 30 are read out using MOS transistors (see, for example, FIG. 1) that exist at positions adjacent to the photodiodes 30. In order to electrically isolate the photodiode 30 and the active region 37 of the MOS transistor, an element isolation region (trench element isolation) 39 made of STI (shallow trench isolation) is formed. P ⁺ -type sidewall layers 38 are provided on the side and bottom of the element isolation region 39, and are randomly generated from the interface of the silicon substrate 31 in contact with the element isolation region 39 with the same effect as the P ⁺ -type surface layer 36. An electric barrier prevents the generated charges from mixing with the photoelectrically stored charges. Therefore, the P ⁺ -type sidewall layer 38 is necessary for reducing the noise characteristics of the solid-state imaging device. Further, the P ⁺ type surface layer 36 and the P type silicon layer 34 are electrically connected by the P ⁺ type side wall layer 38.

Further, indium is introduced into the P ⁺ type sidewall layer 38. Indium has a larger mass number and a smaller diffusion coefficient than B (boron element) introduced conventionally. For example, the diffusion coefficient at 900 ° C. is about 2 × 10 ⁻¹⁵ (cm ² / s) for boron and about 3 × 10 ⁻¹⁶ (cm ² / s) for indium. The distance is short. For this reason, when heat treatment is added after the P ⁺ -type sidewall layer 38 is formed on the sidewall of the element isolation region 39, the spread of the P ⁺ region into which indium has been introduced becomes narrower than when boron is introduced. Therefore, since the narrow channel effect of the photodiode 30 is reduced, the amount of accumulated charge can be ensured. In addition, since P-type dopant indium is introduced into a region adjacent to the interface of the element isolation region 39, a decrease in pyroup of the oxide film formed on the interface surface can be reduced as compared with boron. A steep injection profile can be designed without increasing the injection amount. For this reason, white scratches and dark current characteristics of the photodiode 30 due to crystal defects in the vicinity of the oxide film interface are reduced. Further, if indium is introduced into the P ⁺ -type surface inversion layer 36, the accumulated charge amount of the photodiode 30 can be further ensured for the same reason as described above.

Hereinafter, a method for manufacturing the element isolation region 39 and the P ⁺ -type side wall layer 38 which are characteristic portions in the solid-state imaging device according to the first embodiment of the present invention illustrated in FIG. 2 will be described.

3A to 3D are process cross-sectional views for mainly explaining a process of manufacturing the element isolation region 39 and the P ⁺ type sidewall layer 38 in the solid-state imaging device according to the first embodiment of the present invention. Show.

  First, as shown in FIG. 3A, a pad insulating film 41 made of, for example, a silicon oxide film having a thickness of about 1 nm to 50 nm is formed on a silicon substrate 31. Subsequently, an oxidation resistant film 42 made of, for example, a silicon nitride film having a thickness of 50 nm to 400 nm is formed on the pad insulating film 41.

  Next, as shown in FIG. 3B, after forming a resist pattern (not shown) having an opening in a predetermined region on the oxidation resistant film 42, etching is performed using the resist pattern as a mask. Thus, the pad insulating film 41 and the oxidation resistant film 42 are selectively removed, and an opening 43 exposing a predetermined region on the silicon substrate 31 is formed. Thereafter, the resist pattern is removed. The width of the opening 43 is about 0.10 μm to 10.0 μm and depends on the pixel size to be developed and the CMOS process rule. Subsequently, a trench groove 44 communicating with the opening 43 is formed in the silicon substrate 31 by dry etching. The depth of the trench 44 is about 150 to 500 nm in order to electrically isolate the adjacent active region 39 (described later) and the photodiode 30 from each other. Here, the case where the trench groove 44 is formed using the oxidation resistant film 42 as a hard mask film after removing the resist pattern has been described. However, the trench groove 44 may be formed without removing the resist pattern. . Further, although a silicon nitride film is used here as the hard mask film, a silicon oxide film may be used.

Next, as shown in FIG. 3C, indium ion implantation is performed using an ion implantation method, thereby forming a P ⁺ -type sidewall layer 38 at the bottom and side portions of the trench groove 44. That is, the P ⁺ -type side wall layer 38 is located at the bottom and side of the element isolation region 39 (described later). In this process, since it is not necessary to perform a lithography process using the oxidation resistant film 42 as a mask, there is no variation between pixels due to mask misalignment, and indium is formed in regions located at the bottom and sides of an element isolation region 39 (described later). Can be introduced. In the present embodiment, indium is implanted with an implantation energy of about 30 keV to 500 keV and an implantation amount of about 1 × 10 ¹² to 1 × 10 ¹³ (pieces / cm ³ ). For the P ⁺ type sidewall layer 38, the indium injection amount contained in the region located on the side of the element isolation region 39 (described later) is larger than the indium injection amount contained in the region located on the bottom. That is, the implantation concentration is high. This prevents punch-through and secures electrical isolation characteristics from the adjacent active region 37 (see FIG. 2).

Next, as shown in FIG. 3D, after the silicon oxide film is embedded in the opening 43 and the trench groove 44, the surface is flattened by using a CMP (chemical mechanical polishing) method. Thereafter, by removing the oxidation resistant film 42, an element isolation region 39 in which the P ⁺ type side wall layer 38 is located at the bottom and side portions is formed. Subsequent steps include performing various implantation steps for forming the MOS transistor formation, various implantation steps for forming the photodiode 30, a gate formation step, and a wiring formation step by a known method. Is formed.

  According to the solid-state imaging device and the manufacturing method thereof according to the first embodiment of the present invention described above, the accumulated charge amount is 1.1 times or more than the conventional value, and the number of white scratches and the average dark current are also increased. A value less than half of the conventional value was realized.

(Second Embodiment)
A solid-state imaging device according to the second embodiment of the present invention will be described below with reference to the drawings.

  FIG. 4 shows a cross-sectional structure of a portion including a photodiode and an active region in a solid-state imaging device according to the second embodiment of the present invention. Note that the solid-state imaging device according to the second embodiment of the present invention further includes an N-type additional impurity region 51 as compared with the solid-state imaging device according to the first embodiment of the present invention described above. Since the other configurations are the same, different points will be mainly described below.

As shown in FIG. 4, the solid-state imaging device according to the second embodiment of the present invention is adjacent to both the P ⁺ type sidewall layer 38 into which indium is introduced and the N type silicon layer 33 constituting the photodiode 30. Thus, an N-type additional impurity region 51 is formed. As a result, a large capacity is formed by the depletion layer by the P ⁺ -type side wall layer 38 and the N-type additional impurity region 51 that reduce white defects caused by crystal defects generated at the interface of the element isolation region 39. Therefore, in the solid-state imaging device according to the second embodiment of the present invention, the charge accumulation amount obtained by photoelectric conversion increases and the sensitivity increases as compared with the solid-state imaging device according to the first embodiment.

Hereinafter, a method of manufacturing the element isolation region 39, the P ⁺ -type side wall layer 38, and the N-type additional impurity region 51, which are characteristic portions in the solid-state imaging device according to the second embodiment of the present invention illustrated in FIG. explain.

5A and 5B mainly show a process of manufacturing the element isolation region 39, the P ⁺ -type sidewall layer 38, and the N-type additional impurity region 51 in the solid-state imaging device according to the second embodiment of the present invention. Process sectional drawing for demonstrating is shown.

  First, steps similar to those described with reference to FIGS. 3A and 3B in the method for manufacturing the solid-state imaging device according to the first embodiment of the present invention described above are performed.

Next, as shown in FIG. 5A, by using an ion implantation method, an indium ion implantation and an arsenic or phosphorus ion implantation are performed to form P ⁺ on the bottom and side portions of the trench groove 44. A mold side wall layer 38 and an N-type additional impurity region 51 are formed in this order. In this process, since it is not necessary to perform a lithography process using the oxidation resistant film 42 as a mask, there is no variation between pixels due to mask misalignment, and indium is formed in regions located at the bottom and sides of an element isolation region 39 (described later). And arsenic or phosphorus can be introduced. In this embodiment, indium is implanted at an implantation energy of about 30 to 300 keV and an implantation amount of about 1 × 10 ¹² to 1 × 10 ¹³ (pieces / cm ³ ). Further, when arsenic is used when forming the N-type additional impurity region 51, it is performed with an implantation energy of about 30 to 260 keV and an implantation amount of about 1 × 10 ¹¹ to 1 × 10 ¹³ (pieces / cm ³ ). Yes. Further, when phosphorus is used when forming the N-type additional impurity region 51, it is performed with an implantation energy of about 20 to 120 keV and an implantation amount of about 1 × 10 ¹¹ to 1 × 10 ¹³ (pieces / cm ³ ). Yes.

  Next, as shown in FIG. 5B, after the silicon oxide film is embedded in the opening 43 and the trench groove 44, the surface is flattened using the CMP method. Thereafter, the element isolation region 39 is formed by removing the oxidation resistant film 42. Subsequent steps include performing various implantation steps for forming the MOS transistor formation, various implantation steps for forming the photodiode 30, a gate formation step, and a wiring formation step by a known method. Is formed.

  According to the solid-state imaging device and the manufacturing method thereof according to the second embodiment of the present invention described above, the accumulated charge amount is 1.2 times or more than the conventional value, and the number of white scratches and the average dark current are also increased. A value less than half of the conventional value was realized.

In the present embodiment, when the P ⁺ -type sidewall layer 38 and the N-type additional impurity region 51 are provided in the region serving as the interface of the element isolation region 39, the distance from the element isolation region 39 to the peak position of indium implantation is Alternatively, when the distance to the peak position of arsenic implantation is short, the capacity of the depletion layer can be increased, and the accumulated charge amount can be 1.3 times or more than the conventional value. Further, when the distance from the element isolation region 39 to the peak position of indium implantation is longer than the distance to the peak position of phosphorus or arsenic implantation, the element isolation region 3 can be formed without requiring a lithography process by indium implantation. It can be implanted deeply from the interface, can form a PN junction capacitance with the N-type additional impurity region 51, and the accumulated charge amount is 1.2 times or more than the conventional one. And the number of white scratches becomes 1/3 or less than the conventional one. That is, since the mass number of indium is larger than that of phosphorus or arsenic, the spread at the time of indium implantation can be narrowed. Therefore, the injection peak position can be separated from the interface of the element isolation region 39 when the P ⁺ -type sidewall layer 38 is formed using the oxidation resistant film 42. Therefore, the number of white scratches can be reduced as compared with the conventional one, and the accumulated charge amount can be secured.

-Modification-
FIG. 6 shows the solid state imaging device according to the first embodiment of the present invention described above, in which floating charges are diffused through the transfer gate 64 formed on the gate oxide film 63. A structure when applied to an FDA (Floating Diffusion Amplifier) type solid-state imaging device that transfers to a layer 61 is shown. Here, the present invention can be similarly applied to the solid-state imaging device according to the second embodiment.

  As shown in FIG. 6, when applied to an FDA type solid-state imaging device, it is necessary to provide a separate injection layer 62 for electrically separating the N-type silicon layer 33 and the floating diffusion layer 61. Therefore, boron which is a P-type dopant has been conventionally used. However, since the implantation profile of the P-type dopant can be sharpened by using the separation injection layer 62 into which indium is introduced, the depletion layer capacity of the floating diffusion layer 61 is reduced. The output voltage can be increased by 1.1 times or more compared to the conventional case. Further, since the spread of the thermal diffusion of the separation injection layer 62 in the direction of the N-type silicon layer 33 can be reduced, the amount of accumulated charges can be 1.1 times or more compared with the conventional case.

  As described above, according to the solid-state imaging device and the manufacturing method thereof according to the present invention, the P-type dopant of indium is used at the interface of the element isolation region, which is generated due to the edge portion and interface of the element isolation region. It is possible to realize a high-sensitivity solid-state imaging device that does not cause a reduction in sensitivity and can increase the number of accumulated charges even when the cell size is reduced by preventing the generation of random noise and white scratches derived from electric charges. In addition, by using a P-type dopant of indium for the isolation implantation layer that electrically isolates the N-type silicon layer and the floating diffusion layer in the charge storage region of the photodiode, the capacitance of the floating diffusion layer is increased and the output voltage is increased. Can be high. Furthermore, the number of accumulated charges can be increased. As described above, the present invention is useful for a solid-state imaging device in which an imaging region having a plurality of pixels is provided on a semiconductor substrate and a manufacturing method thereof.

It is a basic circuit block diagram of the solid-state imaging device common to each embodiment of this invention. 1 is a structural cross-sectional view including a photodiode portion in a solid-state imaging device according to a first embodiment of the present invention. (A)-(d) is process sectional drawing which shows the manufacturing method of the structure containing the photodiode part in the solid-state imaging device concerning the 1st Embodiment of this invention in order. FIG. 6 is a structural cross-sectional view including a photodiode portion in a solid-state imaging device according to a second embodiment of the present invention. (A) And (b) is process sectional drawing which shows the manufacturing method of the structure containing the photodiode part in the solid-state imaging device concerning the 2nd Embodiment of this invention in order. FIG. 6 is a structural cross-sectional view including a photodiode portion and a floating diffusion layer in a solid-state imaging device according to a modification of each embodiment of the present invention. It is structure sectional drawing containing the photodiode part in the solid-state imaging device which concerns on a 1st prior art example. It is structure sectional drawing containing the photodiode part in the solid-state imaging device which concerns on a 2nd prior art example. It is structure sectional drawing containing the photodiode part in the solid-state imaging device which concerns on a 3rd prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Photodiode 12 Transfer transistor 13 Reset transistor 14 Amplifying transistor 15 Selection transistor 16 Pixel 17 Imaging area 18 Vertical shift register 19 Horizontal shift register 20 Timing generation circuit 21 Output pulse line 22 Output pulse line 23 Power supply 24 Output pulse line 25 Output signal Line 31 Silicon substrate 30 Photodiode 32 P ^- type silicon layer 33 N-type silicon layer 34 P-type silicon layer 36 P ⁺ -type surface layer 37 Active region 38 P ⁺ -type side wall layer 39 Element isolation region 41 Pad insulating film 42 Oxidation resistance Film 43 Opening 44 Trench groove 51 N-type additional impurity region 61 Floating diffusion layer 62 Separation / implantation layer 63 Gate oxide film 64 Transfer gate

Claims (8)

An imaging region formed on a silicon substrate and including a photoelectric conversion unit;
Trench element isolation formed in at least part of a portion surrounding the photoelectric conversion portion of the substrate;
A MOS transistor formed in a region electrically isolated from the photoelectric conversion unit by the trench element isolation in the imaging region;
The part surrounding the periphery of the side and bottom of the trench element isolation is a solid-state imaging device including indium which is an impurity of a conductivity type different from the conductivity type of the charge storage region of the photoelectric conversion unit.   2. The structure according to claim 1, wherein a peak value of phosphorus or arsenic that is a conductive impurity in the charge storage region of the photoelectric conversion unit is not formed between the peak value of the indium and the trench element isolation interface. The solid-state imaging device described.   2. The structure according to claim 1, wherein a peak value of phosphorus or arsenic, which is a conductive impurity in the charge storage region of the photoelectric conversion unit, is formed between the peak value of the indium and the trench element isolation interface. The solid-state imaging device described.   The density | concentration of the said indium contained in the part located in the bottom part in the said trench element isolation is higher than the density | concentration of the said indium contained in the part located in the side part in the said trench element isolation. The solid-state imaging device according to claim 1. An imaging region formed on a silicon substrate and including a photoelectric conversion unit;
Trench element isolation formed in at least part of a portion surrounding the photoelectric conversion portion of the substrate;
Of the imaging region, a MOS transistor formed in a region electrically isolated from the photoelectric conversion unit by the trench element isolation;
A floating diffusion layer to which the charge accumulated in the photoelectric conversion unit is transferred,
A solid-state imaging device further comprising an electrical isolation region containing indium between the photoelectric conversion unit and the floating diffusion layer.   6. The solid-state imaging device according to claim 1, wherein an upper portion of the photoelectric conversion unit in the charge accumulation region includes indium which is an impurity having a conductivity type different from that of the charge accumulation region. Forming a hard mask film or a resist film on a substrate made of silicon and patterning to form an opening in the hard mask film or the resist film;
(B) forming a trench groove in the substrate by performing etching using the hard mask film or the resist film as a mask;
A step (c) of performing ion implantation of indium and ion implantation of arsenic or phosphorus into the side and bottom of the trench groove in the substrate after the step (b);
A method of manufacturing a solid-state imaging device, comprising: a step (d) of forming trench element isolation in the trench groove after the step (c).   The method for manufacturing a solid-state imaging device according to claim 7, wherein in the step (c), ion implantation energy of indium is smaller than ion implantation energy of phosphorus or arsenic.

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