JP4742661B2 - Manufacturing method of solid-state imaging device - Google Patents

Description

The present invention relates to a method of manufacturing a solid-state imaging device, more particularly to a method of manufacturing a CMOS solid-state imaging device.

There is an increasing demand for miniaturization of solid-state imaging devices, so-called image sensors, and the effective area of a charge storage region constituting a unit pixel of the device, that is, a photodiode (Photo Diode; PD), is decreasing.
Conventionally, a so-called STI (shallow trench isolation) structure in which a trench is formed in a substrate on which a charge accumulation region is formed and an insulating material is embedded in the trench has been used for element separation of a solid-state imaging device. However, it has been pointed out that crystal defects are likely to occur due to the difference in thermal expansion coefficient between the substrate material and the insulating material, and that the saturation signal amount in the charge accumulation region is reduced (for example, non-patent literature). 1).

  For this reason, as an element isolation structure that replaces the STI, an element isolation structure using a diffusion layer formed by impurity diffusion and an insulating film thereon as shown in FIGS. 11 and 12 has been proposed. 11B shows a cross-sectional structure corresponding to the aa line in FIG. 11A, and FIG. 12B shows a cross-sectional structure corresponding to the bb line in FIG. 12A.

The solid-state imaging device 101 having the element isolation structure has a configuration in which a plurality of unit pixels 102 are arranged on a first conductivity type, for example, an n-type semiconductor substrate (not shown). A diffusion layer 103 and an insulating layer 104 that form an element isolation region between matching pixels, a charge storage region 105 that constitutes a photoelectric conversion unit of the unit pixel 102, that is, a photodiode, and a floating that uses this charge storage region 105 as a source A transfer gate 108 and a drain portion 109 constituting a diffusion (FD), an accumulation layer 110 provided on the charge storage region 105, and the accumulation layer 110, the drain portion 109 and the transfer gate 108. And an oxide film 111 for isolation and insulation.
Then, by forming a gate electrode (not shown) on the transfer gate 108, a solid-state imaging device capable of driving by peripheral MOS transistors, that is, an imaging operation and a transfer operation is configured.

In the solid-state imaging device having such an element isolation structure, since substantial element isolation is performed by the diffusion layer 103 formed by ion implantation or the like, the isolation width is only the width of the diffusion layer 103, and the conventional STI configuration is used. The effective area of the charge storage region 105 in the unit pixel 102 can be widened as compared with FIG.
Kazuya Yonemoto, CQ Publisher “Basics and Applications of CCD / CMOS Image Sensors”

In the solid-state imaging device having this configuration, the n-type impurity implantation for forming the charge storage region 105 that greatly contributes to the optical characteristics of the device, that is, the image sensor may be performed using the previously formed insulating film 104 as a mask. Since the process is performed using a mask selected to have a shape corresponding to the insulating film 104, the shape and effective area of the charge storage region 105 have a structure defined by the inner edge of the insulating film 104.
Although the implanted n-type impurity diffuses slightly toward the bottom of the insulating film 104 after the implantation, all of the n-type impurity is canceled by the high-concentration p-type impurity constituting the diffusion layer 103 only by this diffusion. For this reason, it is difficult to substantially increase the effective area of the charge storage region.

However, the insulating film 104 is formed with the minimum dimension width in the standard, that is, the process rule for ensuring the overlap amount of the gate electrodes and the separation capability between elements, and it is difficult to reduce the width. . Therefore, as long as this configuration is used, further miniaturization of the unit pixel for miniaturization of the solid-state imaging device is inevitably caused by reduction of the area of the photoelectric conversion unit, that is, the photodiode by the charge accumulation region 105.
However, the reduction in the area of the photodiode is accompanied by a decrease in the charge storage amount and a deterioration in the S / N ratio, leading to a deterioration in imaging characteristics of the image sensor such as a reduction in dynamic range.

An object of the present invention is to solve these various problems and to provide a method for manufacturing a solid-state imaging device that enables miniaturization of unit pixels without sacrificing the effective area of the charge storage region.

In the method of manufacturing a solid-state imaging device according to the present invention, a pixel is configured by a first conductivity type charge storage region, and an element between the adjacent pixels is configured by a second conductivity type diffusion layer and an insulating film thereon. A method of manufacturing a solid-state imaging device separated by a separating unit, the first impurity diffusion layer having a first conductivity type having a predetermined concentration, adjacent to the outside of the first impurity diffusion layer, and First impurity type second impurity diffusion layers having a lower concentration than the impurity diffusion layer are formed at the same depth of the substrate, and then the first conductivity type impurities are added to the second impurity diffusion layer. The step of implanting and making the second impurity diffusion layer have the same impurity concentration as the first impurity diffusion layer is performed, and the first impurity diffusion layer and the first impurity concentration having the same impurity concentration are obtained . by the second impurity diffusion layer constitutes the charge accumulation region, the second Pure things diffusion layer before or after the step of said first impurity concentration of the same level as the impurity diffusion layer, the diffusion layer of the second conductivity type, and formed adjacent to said second impurity diffusion layer, After configuring the charge storage region, the second conductivity type diffusion layer and the second impurity diffusion layer are covered up to the boundary line between the first impurity diffusion layer and the second impurity diffusion layer. The insulating film is formed on the substrate .

According to the present invention, in the method of manufacturing the solid-state imaging device, a step of forming a first conductivity type impurity diffusion layer, and then a second conductivity type impurity is implanted into the first conductivity type impurity diffusion layer. Thus, the second conductivity type diffusion layer and the second impurity diffusion layer adjacent to the second conductivity type diffusion layer are formed, and the remaining first conductivity type impurity diffusion layer forms the first conductivity type. Forming a first impurity diffusion layer, and then performing a step of setting the second impurity diffusion layer to an impurity concentration comparable to that of the first impurity diffusion layer.
According to the present invention, in the method of manufacturing the solid-state imaging device, the first impurity diffusion layer and the second impurity diffusion are formed by injecting a first conductivity type impurity into the second conductivity type impurity region. And forming the second impurity diffusion layer at the same impurity concentration as the first impurity diffusion layer, and then adjoining the second impurity diffusion layer, The step of forming the diffusion layer of the second conductivity type is performed.
In the method of manufacturing the solid-state imaging device, the present invention further includes implanting a second conductivity type impurity above the second impurity diffusion layer to obtain the same degree as that of the second conductivity type diffusion layer. Forming a diffusion layer having an impurity concentration, and then implanting a second conductivity type impurity above the first impurity diffusion layer to form a second conductivity type accumulation layer; Is further performed.

According to the method for manufacturing a solid-state imaging device according to the present invention, the first impurity diffusion layer of the first conductivity type having a predetermined concentration, the first impurity diffusion layer adjacent to the outside of the first impurity diffusion layer, and the first impurity diffusion layer. A second impurity diffusion layer of the first conductivity type having a lower concentration than the first impurity diffusion layer is formed at the same depth of the substrate, and then an impurity of the first conductivity type is implanted into the second impurity diffusion layer. The step of setting the second impurity diffusion layer to the same impurity concentration as the first impurity diffusion layer is performed, and the first impurity diffusion layer and the second impurity having the same impurity concentration are obtained. Since the charge storage region is formed by the diffusion layer, the effective area of the charge storage region and the saturation signal amount can be increased.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of an embodiment of a solid-state imaging device according to the present invention. FIG. 1B shows a cross-sectional structure corresponding to the line b′-b ′ in FIG. 1A.
In the solid-state imaging device 1 according to this embodiment, that is, a CMOS solid-state imaging device, a second conductivity type, eg, p-type semiconductor well region is formed on a first conductivity type, eg, n-type silicon semiconductor substrate (not shown). In the p-type semiconductor well region, a plurality of unit pixels 2 are partitioned and formed in an element isolation region by the diffusion layer 3 and the insulating film 4.

  Each unit pixel 2 includes at least a charge storage region 7 that forms a photoelectric conversion unit, that is, a photodiode, a transfer gate 8 and a drain unit 9 that form a floating diffusion (FD) that uses the charge storage region 7 as a source, It has an accumulation layer 10 provided on the storage region 7, and an oxide film 11 that isolates and insulates the accumulation layer 10 and the drain portion 9 from the transfer gate 8.

The photoelectric conversion unit, that is, the photodiode, is formed in an HAD structure including an n-type substrate (not shown), a p-type semiconductor well region, an n-type charge storage region 7, and an accumulation layer 10 on the surface side thereof. The accumulation layer 10 suppresses the dark current caused by the interface state, that is, the cause of white spots in imaging.
The accumulation layer 10 is formed of a high concentration p-type impurity diffusion layer of, for example, 5 × 10 ¹⁷ cm ⁻³ or more.

FIG. 2 is an enlarged cross-sectional view of the solid-state imaging device in the vicinity of the element isolation region.
The charge storage region 7 includes not only a main portion 5 formed inside the inner edge of the insulating film 4 but also an extended portion 6 formed at a position continuous from the main portion 5 below the insulating film 4.
As will be described later, the extended portion 6 is formed by, for example, two or more impurity implantations independently of the main portion 5, so that the effective area of the charge storage region 7 is expanded and saturated while ensuring element isolation. The signal amount can be increased, and the n-type impurity concentration of the extended portion 6 can be adjusted to the same level as the n-type impurity concentration of the main portion 5.

In this embodiment, the extension diffusion layer 12 having a p-type impurity concentration comparable to that of the diffusion layer 3 is provided between the extension portion 6 of the charge storage region 7 and the insulating layer 4 and the diffusion layer 3. It is formed so as to connect the cue simulation layers 10. That is, the width of the extended diffusion layer 12 is not restricted by the extended portion 6 of the charge storage region 7, and only the narrowest portion of the diffusion layer 3 is defined by the extended portion 6.
As will be described later, this extended diffusion layer 12 is formed by, for example, two or more impurity implantations independently of the diffusion layer 3, so that the p-type impurity concentration of the extended diffusion layer 12 is also the impurity of the diffusion layer 3. It is possible to adjust to the same level as the concentration.
Note that the diffusion layer 3 may be configured to form an impurity concentration distribution in the depth direction so that the impurity concentration gradually decreases as the depth increases, for example.

Since the insulating film 4 is formed so that the bottom exists at a shallower position than the position of the pn junction formed at the interface between the charge storage region 7 and the accumulation layer 10, the insulating film 4 is caused by thermal stress. Generation of crystal defects can be avoided, and even when a gate electrode, wiring, or the like is formed on the insulating film 4, depletion or generation of a parasitic channel due to an inversion layer can be suppressed immediately below the insulating film 4. .
Further, even when the insulating film 4 is thinned, by increasing the p-type impurity concentration of the diffusion layer 3 and the extension diffusion layer 12 immediately below the insulating film 4, generation of a parasitic channel immediately below the insulating film 4 can be suppressed. The thickness of the insulating film can be selected between at least 1 nm and 1000 nm.

  Next, first and second embodiments of the method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS.

  A first embodiment of a method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS. In this embodiment, a manufacturing method in the case where a unit pixel and a transistor region are adjacent to each other with an element isolation region therebetween will be described.

First, as shown in FIG. 3A, a silicon substrate in which a second conductivity type, eg, p-type semiconductor well region 32 is formed on a first conductivity type, eg, n type silicon substrate 31, is prepared, and a silicon oxide film is formed on the surface of the silicon substrate. 11 and a silicon nitride film 34 serving as a hard mask is formed thereon, and then an n-type charge storage region 33 is ion-implanted into a region serving as a photodiode through a resist mask (not shown), for example. An n-type impurity concentration is formed by ion implantation with a dose of about 1 × 10 ¹² cm ⁻³ .

  As the n-type impurity, arsenic (As) can be used in consideration of diffusion suppression in the heat treatment process, or phosphorus (P) can be used. Further, when the charge accumulation region 33 is formed, the portion adjacent to the photodiode can be backed up with p-type impurities in a later step to form an element isolation region therebetween. Pixels can be formed continuously.

  Next, as shown in FIG. 3B, the silicon nitride film 34 in the portion where the element isolation region is to be formed, that is, the portion between the photodiodes of the adjacent pixels and the portion between the photodiode and the drain of the adjacent pixels are selectively formed. Then, the lower silicon oxide film 11 is selectively removed by etching to form an opening.

Next, as shown in FIG. 4C, using the silicon nitride film 34 and the silicon oxide film 11 as a mask, a shallow groove is dug in the surface of the silicon substrate exposed in the opening by a shallow etching process, and p-type impurities are ion-implanted to form the groove. A diffusion layer 3 that finally forms an element isolation region is formed on the bottom surface, and a resist 35 is formed on the diffusion layer 3 leaving an opening narrower than the width of the diffusion layer 3 formed here. Here, the ion implantation is performed, for example, with boron (B) at a dose of about 2 × 10 ¹² cm ⁻³ to a dose of about 1 × 10 ¹⁴ cm ⁻³ and an implantation energy of about keV to about 50 keV.

  Next, as shown in FIG. 4D, ion implantation for expanding the depth of the diffusion layer 3 was performed in the opening of the resist 35 formed earlier, that is, with a width narrower than the width of the diffusion layer 3 already formed. Thereafter, a resist 36 is formed above the position where ions are implanted. Here, the ion implantation is performed several times in the depth direction, and an impurity concentration distribution is formed in the depth direction so that, for example, the impurity concentration gradually decreases as the depth increases. You can also

  Next, as shown in FIG. 5E, the n-type impurity concentration reduced portions located at both ends of the charge storage region main portion 5 formed by element isolation by the diffusion layer 3 formed in the previous step are formed. On the other hand, the second implantation of the n-type impurity is performed using the resist 36 as a mask, and an impurity concentration comparable to that of the main portion 5 is formed under the region where the insulating film 4 of the finally obtained solid-state imaging device is formed. The extended portion 6 is formed independently of the formation of the main portion 5 to complete the charge storage region 7.

  Next, as shown in FIG. 5F, the surface of the diffusion layer 3 in which the concentration of the p-type impurity is lowered by the second implantation of the n-type impurity previously performed using the resist in the formation of the extended portion 6 as a mask. The second implantation of the p-type impurity is performed on the portion 37, and the same as the diffusion layer 3 between the extended portion 6 of the charge storage region 7 and the position where the insulating film 4 of the solid-state imaging device finally obtained is formed. An extended diffusion layer 12 having a p-type impurity concentration of about a degree is formed, and then the resist is removed.

Next, as shown in FIG. 6, the insulating layer 4 is deposited on the upper surfaces of the diffusion layer 3 and the extended diffusion layer 12, and planarized and polished by, for example, CMP (Chemical Mechanical Polishing) to the height of the surface of the silicon nitride film 34. Thereafter, the silicon nitride film 34 is removed, and thereafter, the drain region 9 and the accumulation layer 10 of the transistor are formed by a normal process to form the above-mentioned photodiode with the HAD structure.
Thereafter, although not shown, a gate insulating film and a gate electrode are formed to form a MOS transistor necessary for driving the solid-state imaging device, thereby obtaining a target CMOS solid-state imaging device.

  Next, a second embodiment of the method for manufacturing a solid-state imaging device according to the present invention will be described with reference to FIGS. In this embodiment, a manufacturing method in the case where only unit pixels are adjacent to each other with an element isolation region therebetween will be described.

  First, as shown in FIG. 7A, a silicon substrate in which a second conductivity type, eg, p-type semiconductor well region 22 is formed on a first conductivity type, eg, n type silicon substrate 21, is prepared, and a silicon oxide film is formed on the surface of the silicon substrate. 11 is formed, and a silicon nitride film 23 serving as a hard mask is formed thereon.

  Next, as shown in FIG. 7B, the silicon nitride film 23 in the portion where the element isolation region is to be formed, that is, the portion between the photodiodes of the adjacent pixels and the portion between the photodiode and drain of the adjacent pixels are selectively selected. Then, the lower silicon oxide film 11 is selectively removed by etching to form an opening.

Next, as shown in FIG. 8C, by using the silicon nitride film 23 and the silicon oxide film 11 as a mask, a shallow groove is dug in the surface of the silicon substrate exposed in the opening by a shallow etching process, and p-type impurities are ion-implanted to form the groove. A diffusion layer 3 that finally forms an element isolation region is formed on the bottom surface, and a resist 24 is formed on the diffusion layer 3. Here, the ion implantation is performed, for example, with boron (B) at a dose of about 2 × 10 ¹² cm ⁻³ to a dose of about 1 × 10 ¹⁴ cm ⁻³ and an implantation energy of about keV to about 50 keV.

Next, as shown in FIG. 8D, a resist 24 is deposited on the upper surface of the diffusion layer 3, and then, as shown in FIG. 9E, an n-type charge is applied to a region to be a photodiode using the resist 24 as a mask. The main portion 5 of the accumulation region is formed by ion implantation, for example, by ion implantation with an n-type impurity concentration of about 1 × 10 ¹² cm ⁻³ .

  Next, as shown in FIG. 9F, the n-type region 25 having a low n-type impurity concentration is formed on both sides of the main portion 5 of the charge storage region formed in the previous step using the resist 26 as a mask. An extension portion 6 having an impurity concentration similar to that of the main portion 5 is formed below the region where the insulating film 4 of the solid-state imaging device to be finally obtained is formed by performing the second implantation of impurities. The charge accumulation region 7 is completed by forming independently of the formation.

Next, as shown in FIG. 10, using the resist 26 used for forming the extension portion 6 as a mask, the diffusion layer in which the concentration of the p-type impurity is reduced by the second implantation of the n-type impurity previously performed. P-type impurity is injected into the surface portion 27 for the second time between the extended portion 6 of the charge storage region 7 and the position where the insulating film 4 of the solid-state imaging device finally obtained is formed. The extension diffusion layer 12 having a p-type impurity concentration equivalent to 3 is formed, and then the resist is removed. Then, the insulating layer 4 is deposited on the upper surfaces of the diffusion layer 3 and the extension diffusion layer 12, and the silicon nitride film After that, the drain region 9 of the transistor and the accumulation layer 10 are formed by a normal process to form the above-mentioned photodiode with the HAD structure.
Thereafter, although not shown, a gate insulating film and a gate electrode are formed to form a MOS transistor necessary for driving the solid-state imaging device, thereby obtaining a target CMOS solid-state imaging device.

  As mentioned above, although embodiment of the manufacturing method of the solid-state image sensor concerning this invention and a solid-state image sensor was described, this invention is not limited to this embodiment.

  For example, according to the method for manufacturing a solid-state imaging device according to the present invention, it is possible to set the charge accumulation region of the photodiode regardless of the width of the insulating film, so that the effective area of the charge accumulation region can be increased. Not limited to the desired element, such as narrowing the separation width by the diffusion layer for areas where the electric field strength between adjacent elements is weak around the photodiode, and increasing the separation width by the diffusion layer for areas where the electric field strength is strong. The present invention can also be applied to manufacture of a solid-state imaging device for the purpose of forming a separation pattern.

  In addition, for example, it is injected when an extension part constituting the charge storage region and an extension diffusion layer constituting the element isolation region are formed independently from the main part constituting the charge storage region and the diffusion layer constituting the element isolation region. The present invention can be variously modified and modified such that the impurity having the same polarity is not necessarily the same material as the impurity used for forming the main portion and the diffusion layer.

A and B are a schematic top view and a schematic cross-sectional view showing a configuration of an example of a solid-state imaging device according to the present invention. It is an expanded sectional view showing the composition of an example of the solid-state image sensing device concerning the present invention. A and B are process diagrams for explaining an example of a method for manufacturing a solid-state imaging device according to the present invention. C and D are process diagrams for explaining an example of a method for manufacturing a solid-state imaging device according to the present invention. E and F are process diagrams for explaining an example of a method for manufacturing a solid-state imaging device according to the present invention. It is process drawing with which it uses for description of an example of the manufacturing method of the solid-state image sensor which concerns on this invention. A and B are process diagrams for explaining another example of a method for manufacturing a solid-state imaging device according to the present invention. C, D It is process drawing with which it uses for description of the other example of the manufacturing method of the solid-state image sensor concerning this invention. E, F It is process drawing with which it uses for description of the other example of the manufacturing method of the solid-state image sensor concerning this invention. It is process drawing for description of the other example of the manufacturing method of the solid-state image sensor which concerns on this invention. A and B are a schematic top view and a schematic cross-sectional view showing a configuration of a conventional solid-state imaging device. A and B are a schematic top view and a schematic cross-sectional view showing a configuration of a conventional solid-state imaging device.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state image sensor, 2 ... Unit pixel, 3 ... Diffusion layer, 4 ... Insulating film, 5 ... Main part, 6 ... Extension part, 7 ... Charge storage area 8 ... Transfer gate, 9 ... Drain portion, 10 ... Accumulation layer, 11 ... Oxide film, 12 ... Extended diffusion layer, 21 ... Semiconductor substrate, 22 ... Semiconductor well region, 23 ... hard mask, 24 ... resist, 25 ... low impurity concentration region, 26 ... resist, 27 ... surface portion, 31 ... semiconductor substrate, 32 ... Semiconductor well region 33: Charge storage region 34 ... Hard mask 35 ... Resist 36 ... Resist 37 ... Surface portion 101 ... Solid-state image sensor 102 ... Unit pixel 103 ... Diffusion layer 104 ... Insulating film 105 ... Load storage area 108 ... transfer gate, 109 ... drain unit, 110 ... accumulation layer, 111 ... oxide film

Claims (4)

Manufactures a solid-state imaging device in which a pixel is constituted by a charge accumulation region of the first conductivity type, and the adjacent pixels are separated by an element separation means constituted by a diffusion layer of a second conductivity type and an insulating film thereon. A way to
A first impurity diffusion layer of a first conductivity type having a predetermined concentration, and a second impurity of the first conductivity type adjacent to the outside of the first impurity diffusion layer and having a lower concentration than the first impurity diffusion layer. Each of the diffusion layers is formed at the same depth of the substrate,
Thereafter, a step of injecting a first conductivity type impurity into the second impurity diffusion layer to make the second impurity diffusion layer have an impurity concentration comparable to that of the first impurity diffusion layer,
The charge storage region is configured by the first impurity diffusion layer and the second impurity diffusion layer having the same impurity concentration ,
Before or after the step of setting the second impurity diffusion layer to the same impurity concentration as that of the first impurity diffusion layer, the second conductivity type diffusion layer is adjacent to the second impurity diffusion layer. Forming,
After configuring the charge storage region, the second conductivity type diffusion layer and the second impurity diffusion layer are covered up to the boundary line between the first impurity diffusion layer and the second impurity diffusion layer. A method for manufacturing a solid-state imaging device , wherein the insulating film is formed on the substrate. Forming a first conductivity type impurity diffusion layer;
Thereafter, by implanting a second conductivity type impurity into the first conductivity type impurity diffusion layer, the second conductivity type diffusion layer and the second impurity adjacent to the second conductivity type diffusion layer. Forming a diffusion layer, and forming the first impurity diffusion layer with the remaining impurity diffusion layers of the first conductivity type,
2. The method for manufacturing a solid-state imaging element according to claim 1, wherein a step of setting the second impurity diffusion layer to an impurity concentration comparable to that of the first impurity diffusion layer is performed. By implanting a first conductivity type impurity into the second conductivity type impurity region, the first impurity diffusion layer and the second impurity diffusion layer are formed simultaneously;
Thereafter, a step of setting the second impurity diffusion layer to an impurity concentration comparable to that of the first impurity diffusion layer is performed.
2. The method for manufacturing a solid-state imaging element according to claim 1, wherein a step of forming the second conductivity type diffusion layer adjacent to the second impurity diffusion layer is performed. A step of implanting a second conductivity type impurity above the second impurity diffusion layer to form a diffusion layer having an impurity concentration comparable to that of the second conductivity type diffusion layer; by implanting an impurity of a second conductivity type above the impurity diffusion layer, further performing the step of forming the accumulation layer of the second conductivity type, to any one of claims 1 to 3 The manufacturing method of the solid-state image sensor of description.

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