JP2010087076A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the ohmic contact resistance of GaN-HEMT to ≤0.1 Ω/mm. <P>SOLUTION: A semiconductor device includes a GaN layer 19, a base 13 including an active region 11a formed owing to the GaN layer, a gate electrode 15 formed on the active region, and first and second main electrodes 17a and 17b formed in the active region apart from and opposite each other with the gate electrode interposed. Then widths W<SB>C1</SB>and W<SB>C2</SB>of first and second overlap regions 29a and 29b where the first and second main electrodes overlap with the active region, respectively, in a gate width direction 31 are ≥10 times as large as a width W<SB>G</SB>of a third overlap region 35 where the gate electrode overlap with the active region in the gate width direction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a structure of a semiconductor device, and more particularly to a structure for reducing ohmic contact resistance of a GaN-HEMT (High Electron Mobility Transistor).

  Conventionally, a HEMT is well known as a field effect transistor using a two-dimensional electron gas layer (hereinafter also referred to as a 2DEG layer) as a current path. In HEMT, reducing ohmic contact resistance is an important factor for improving device characteristics. In particular, in the GaN-HEMT, since a base having a large energy band gap based on GaN having a strong crystal structure is used, a large amount of energy is required for alloying the base and the ohmic metal material. Therefore, ohmic contact due to alloying is difficult to take, and the ohmic contact resistance increases due to the large band gap. Therefore, in particular, in GaN-HEMT, it is desired to greatly reduce the ohmic contact resistance.

In HEMT, in order to reduce the ohmic contact resistance, the region where the ohmic electrode in ohmic contact contacts the active region of the base, the width W _{C (hereinafter,} also referred to as the contact width W _C) along the gate width direction, the gate width W is a well-known structure to set shorter than the _G (e.g., see Patent Document 1, Patent Document 2, and non-Patent Document 1).

In Patent Document 1, a GaAs layer as an electron transit layer, and in GaAs-HEMT which uses AlGaAs layer as an electron supply layer, the contact width _{W C,} by setting shorter than the gate width _{W G,} ohmic contact resistance A structure for reducing the above is disclosed. In the GaAs-HEMT according to Patent Document 1, the width along the gate width direction of the region where the ohmic electrode and the active region overlap, that is, the substantial contact width W _C, and the region where the gate electrode and the active region overlap. the gate width direction along the width, that is, the substantial gate width _{W G, 1 (μm) +} W G < to satisfy W C <5W _G, the active region, a gate electrode, and forming an ohmic electrode Yes.

In Patent Document 2, in the GaN-HEMT using a GaN layer as an electron transit layer and using an AlGaN layer as an electron supply layer, the contact width is set larger than the gate width as in Patent Document 1 described above. Thus, a structure for reducing ohmic contact resistance is disclosed. In GaN-HEMT according to the patent document 2, the ohmic electrode by the uneven surface side facing the gate electrode, a substantial contact width W _C, is set larger than the gate width W _G.

Moreover, in GaN-HEMT by patent document 2, the ohmic electrode is penetrated and formed in the base from the upper surface of the base to a deeper position than the two-dimensional electron gas layer. By forming the ohmic electrode in this manner, in the GaN-HEMT according to Patent Document 2, the ohmic electrode makes an ohmic contact directly with the two-dimensional electron gas layer. By adopting such a structure, the GaN-HEMT according to Patent Document 2 can remarkably reduce the contact specific resistance between the ohmic electrode and the base. As a result, the GaN-HEMT according to Patent Document 2, structure coupled with the set larger than the gate width W _G of the contact width W _C described above, effectively the ohmic contact resistance is reduced.

Furthermore, the GaN-HEMT according to Non-Patent Document 1, by forming a trench in a portion of an active region of the gate electrode lower side to reduce the gate width W _G. In the GaN-HEMT according to Non-Patent Document 1, a plurality of trenches separated from each other along the gate width direction are formed below the gate electrode. As a result, in the GaN-HEMT according to Non-Patent Document 1, the gate electrode and the active region are not in contact with each other in the region where the trench is formed, and the substantial gate width WC is shortened. Therefore, the GaN-HEMT according to Non-Patent Document 1, the contact width _{W C} is larger than the gate width _{W G.}

As another method for reducing the ohmic contact resistance of the HEMT, a technique is well known in which a GaN layer doped with Si at a high concentration is formed as a cap layer on the uppermost layer of the base (for example, see Non-Patent Document 2). . In this non-patent according to Document 2 structure, in GaN-HEMT, thereby reducing the ohmic contact resistance per unit width of the contact width _{W C} until 0.5 .OMEGA / mm.
JP 7-99210 A JP 2007-165446 A IEEJ Technical Material Electronic Materials Research Society EFM-07-17, Tamura, et al. “Characteristics of AlGaN / GaN HEMT with Multiple Trapezoidal Channels” H. Okita, et. al, "High Trans-conductance AlGaN / GaN-HEMT with Recessed Gate on Sapphire Substrate," phy. Stat. Sol. (A) 200, No. 1, pp. 187-190, 2003.

However, when the inventors of this invention made various investigations, in order to pull out the element characteristics of the GaN-HEMT sufficiently reduces the ohmic contact resistance per unit width of the contact width W _C below 0.1 [Omega / mm (The details will be described in the first embodiment to be described later).

  However, as described above, since the GaN-HEMT has a large energy band gap, when the ohmic contact resistance is reduced in the GaN-HEMT, the above-mentioned Patent Document 1, Patent Document 2, Non-Patent Document 1, and Non-Patent Document 1 The structure according to Patent Document 2 is insufficient.

  Patent Document 1 discloses a structure for reducing ohmic contact resistance in a GaAs-HEMT. However, in the structure according to Patent Document 1, a good ohmic contact resistance can be obtained in a GaAs-HEMT having a small energy band gap as compared with a GaN-HEMT. However, when this structure is applied to a GaN-HEMT, Cannot reduce the ohmic contact resistance to 0.1 Ω / mm or less.

  In any structure according to Patent Document 2, Non-Patent Document 1, and Non-Patent Document 2, there is room for improvement in reducing the ohmic contact resistance to 0.1 Ω / mm or less.

  An object of the present invention is to provide a structure of a semiconductor device capable of reducing ohmic contact resistance to 0.1 Ω / mm or less in a GaN-HEMT.

  In order to achieve the above object, according to the present invention, a semiconductor device has the following characteristics.

  That is, the semiconductor device according to the present invention includes a GaN layer and a base including an active region generated due to the GaN layer. The semiconductor device includes a gate electrode formed on the active region. In addition, the semiconductor device includes first and second main electrodes that are formed in the active region and are spaced apart from and opposed to each other with the gate electrode interposed therebetween.

The width W _C1 and the width W _C2 along the gate width direction of the first and second overlapping regions where the first and second main electrodes and the active region overlap are the third overlap where the gate electrode and the active region overlap. region is at least 10 times the width W _G along the gate width direction.

In the semiconductor device according to the present invention, the widths W _C1 and W _C2 along the gate width direction of the first and second overlapping regions, that is, the substantial contact widths W _C1 and W _C2 are set to the gates of the third overlapping region. The width W _G along the width direction, that is, 10 times or more the substantial gate width W _G is set. As a result, the contact width _{W C1} and _{W C2} and the gate width _{W G} than the HEMT in the case of the same, the ohmic contact resistance per unit width may be less than 1/10. Therefore, the present invention is applied to a device having an ohmic contact resistance per unit width larger than 0.1 Ω / mm and 1.0 Ω / mm or less, such as the GaN-HEMT according to Non-Patent Document 2 described above. By applying the structure according to the above, the ohmic contact resistance per unit width can be reduced to 0.1 Ω / mm or less.

  A semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be described below with reference to the drawings. Each drawing merely schematically shows the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood. Therefore, the configuration of the present invention is not limited to the illustrated configuration example.

<First Embodiment>
In the first embodiment, the contact width _{W C1} and _{W C2} of the GaN-HEMT is described semiconductor device is 10 times the gate width _{W G.}

  FIG. 1A is a schematic diagram for explaining a first embodiment of the present invention, and is a plan view of a base as viewed from an upper surface, that is, a surface on which an element such as an FET is formed. FIG. 1B is an end view of the cut along the line II shown in FIG. Normally, in an actual semiconductor device, an upper layer such as an interlayer insulating layer or an upper wiring layer is formed above the structure shown in FIGS. 1A and 1B. In (B) and (B), in order to clearly show the characteristic portions according to the first embodiment, the upper layers thereof are omitted.

  The semiconductor device according to the first embodiment includes a base 13 including an active region 11a.

  The base 13 is a semiconductor substrate having a conventionally known heterojunction surface of AlGaN / GaN. That is, the base 13 includes a GaN layer 19 formed as an electron transit layer and an AlGaN layer 21 formed as an electron supply layer on the GaN layer 19. More specifically, the base 13 is first formed of a substrate 23 made of, for example, Si, SiC, or sapphire, and a buffer layer 25 made of, for example, AlN or GaN formed on the upper side of the substrate 23 by a known MOCVD method. It has. An impurity-free GaN layer 19 as an electron transit layer and an impurity-free AlGaN layer 21 as an electron supply layer are sequentially formed on the buffer layer 25 by a well-known MOCVD method or MBE method. When such a stacked structure is formed, a two-dimensional electron gas layer (hereinafter referred to as a current path) is formed near the boundary between the GaN layer 19 and the AlGaN layer 21 due to the difference in energy band gap between the GaN layer 19 and the AlGaN layer 21. 2DEG layer) 27 is formed. The 2DEG layer 27 is formed in a planar shape perpendicular to the thickness direction of the GaN layer 19. The active region 11 a is formed as a region corresponding to the 2DEG layer 27 generated on the base 13 due to the GaN layer 21. Therefore, in other words, the 2DEG layer 27 is formed in a planar shape in the base 13 over the active region 11a. Details of the shape of the active region 11a in the base 13, that is, the planar shape in a plane perpendicular to the thickness direction of the base 13, will be described later.

  In the semiconductor device according to the first embodiment, the GaN-HEMT is composed of the base 13, the gate electrode 15 formed in the active region 11a of the base 13, and the first and second main electrodes 17a and 17b. Has been.

  The gate electrode 15 is formed on the active region 11a using, for example, Ni and Au as materials.

  The first and second main electrodes 17 a and 17 b function as ohmic electrodes for making ohmic contact with the 2DEG layer 27. Accordingly, one of the first and second main electrodes 17a and 17b functions as a source electrode and the other functions as a drain electrode. For this purpose, the first and second main electrodes 17a and 17b, such as Ti and Al, are formed in the active region 11a so as to be spaced apart from each other with the gate electrode 15 therebetween.

  The first and second main electrodes 17 a and 17 b are formed so as to penetrate from the upper surface 13 a of the base 13 into the base 13 to a position deeper than the 2DEG layer 27. In the semiconductor device according to the first embodiment, the first and second main electrodes 17a and 17b are formed in this manner, whereby the first and second main electrodes 17a and 17b and the 2DEG layer 27 are in direct contact with each other. As a result, an ohmic contact can be made directly between the first and second main electrodes 17a and 17b and the 2DEG layer 27. Therefore, for example, the contact specific resistance between the first and second main electrodes 17a and 17b and the active region 11a can be reduced as compared with the case where an ohmic electrode is formed on the active region 11a. As a result, the semiconductor device according to the first embodiment has a structure advantageous in reducing the ohmic contact resistance generated between the first and second main electrodes 17a and 17b and the 2DEG layer 27.

In addition, by making an ohmic contact directly between the first and second main electrodes 17a and 17b and the 2DEG layer 27 in this way, in the semiconductor device according to the first embodiment, the value of the ohmic contact resistance is Width of the first and second overlapping regions 29a and 29b where the first and second main electrodes 17a and 17b overlap the active region 11a along the gate width direction 31 indicated by an arrow (hereinafter also referred to as contact width) W Depends only on _C1 and _WC2 . Therefore, the lengths (hereinafter also referred to as contact lengths) L _C1 and L _C2 along the gate length direction 33 indicated by the arrows of the first and second overlapping regions 29a and 29b can be freely set according to the design. it can. Here, in general, in the HEMT, the pad capacitance between the first and second main electrodes 17a and 17b and the active region 11a is suppressed to 100 fF / μm ² or less in order to prevent characteristic deterioration such as operation delay. Is preferred. The pad capacitance is proportional to the areas of the first and second overlapping regions 29a and 29b. Therefore, in the first embodiment, by setting shorter length _{L C1} and _{L C2} along the gate length direction 33 of the first and second overlapping regions 29a and 29 b, the first and second overlapping regions 29a And the area of 29b is reduced and the pad capacitance is suppressed. More specifically, the lengths L _C1 and L _C2 are preferably set to 0.5 to 10.0 μm in order to surely suppress the pad capacitance to 100 fF / μm ² or less.

In the semiconductor device according to the first embodiment, in order to reduce ohmic contact resistance, the gate width direction 31 of the region where the first and second main electrodes 17a and 17b are in ohmic contact with the active region 11a. , Ie, the contact widths W _C1 and W _C2 described above, and the gate width W _G , that is, the width W _G along the gate width direction 31 of the third overlapping region 35 where the gate electrode 15 and the active region 11a overlap. Set larger than.

FIG. 2 is a diagram showing the correlation between the ohmic contact resistance and the drain current in the GaN-HEMT obtained by simulation. In FIG. 2, the vertical axis indicates the drain current per unit in the contact width in units of mA / mm. The horizontal axis is a scale of ohmic contact resistance per unit in contact width in Ω / mm. 2 assumes a GaN-HEMT having a sheet resistance of 500Ω / □, and the simulation is performed under the conditions of V _g (gate voltage) = 0V and V _ds (source-drain voltage) = 10V. The results are shown. In addition, this simulation was performed using well-known Gateway PISCES ver3.2.

  As is apparent from the results of FIG. 2, it can be seen that when the ohmic contact resistance per unit is 0.1 Ω / mm or less, the drain current per unit width is saturated. On the other hand, when the ohmic contact resistance per unit is larger than 0.1 Ω / mm, the drain current is significantly reduced. Therefore, from the result of FIG. 2, in the GaN-HEMT, if the ohmic contact resistance per unit is reduced to 0.1 Ω / mm or less, the voltage applied to the 2DEG layer can be prevented from dropping due to the ohmic contact resistance. I understand.

Therefore, in this first embodiment, the ohmic contact resistance per unit width to allow reduced to below 0.1 [Omega / mm, to set the contact width W _C1 and W _C2 and the gate width W _G.

Here, as already described, in the semiconductor device according to the first embodiment, the first and second main electrodes 17a and 17 are formed so as to penetrate deeper than the 2DEG layer 27, so that the ohmic contact resistance is increased. The value of depends on the contact widths W _C1 and W _C2 . Therefore, the contact width W _C1 and W _C2, by 10 times or more the gate width W _G, the ohmic contact resistance per unit width of the contact width may be less than 1/10.

In the semiconductor device according to the first embodiment, the contact width _{W C1} and _{W C2,} and more than 10 times the gate width _{W G.} By thus setting the contact width W _C1 and W _C2 and the gate width W _G, in the semiconductor device according to the first embodiment, the ohmic contact resistance per unit width can be set to 1/10 or less. Therefore, the first embodiment is applied to a device (for example, GaN-HEMT according to Non-Patent Document 2 described above) having an ohmic contact resistance larger than 0.1 Ω / mm and 1.0 Ω / mm or less. By applying the structure according to, the ohmic contact resistance per unit width can be reduced to 0.1 Ω / mm or less.

In the semiconductor device according to the first embodiment, in order to make contact width W _C1 and W _C2 and 10 times the gate width W _G, the active region 11a is described below in such a planar shape, a basement 13 It is formed in a planar shape in a plane perpendicular to the thickness direction. Hereinafter, when simply referred to as a planar shape, it means a planar shape in a plane perpendicular to the thickness direction of the base 13.

In the first embodiment, in the active region 11a, the first and second overlapping regions 29a and 29b, which are substantially in ohmic contact, are substantially the same as the gate electrode 15 with respect to the active region 11a. Compared with the third overlapping region 35, which is a region to which a voltage is applied, it is formed with a width 10 times or more along the gate width direction 31. As a result, the contact width _{W C1} and _{W C2} is 10 times or more the width of the gate width _{W G.}

  Further, the active region 11a is located in the gate width direction 31 from the first overlapping region 29a toward the third overlapping region 35 in the region between the first overlapping region 29a and the third overlapping region 35, that is, in the first intermediate region 39. It has a flat shape that gradually becomes narrower. In addition, the active region 11a extends in the gate width direction from the second overlapping region 29b toward the third overlapping region 35 in the region between the second overlapping region 29b and the third overlapping region 35, that is, in the second intermediate region 41. It has a planar shape in which the width gradually decreases.

  Further, the region outside the active region 11a of the base 13 is formed as an element isolation region by introducing, for example, Ar ions or the like deeper than the 2DEG layer 27 from the upper surface 13a of the base 13 by a known ion implantation technique, or The inactive region 43 is formed by forming a trench deeper than the 2DEG layer 27 by a known etching technique. Note that FIG. 1B shows a configuration example when the inactive region 43 is formed by ion implantation.

In the semiconductor device according to the first embodiment, the width W _C1 and the width W _C2 along the gate width direction 31 of the first and second overlapping regions 29a and 29b, that is, the substantial contact widths W _C1 and W _C2 are set. The width W _{G of} the third overlapping region 35 along the gate width direction 31, that is, 10 times or more the substantial gate width W _G is set. As a result, the contact width _{W C1} and _{W C2} and the gate width _{W G} than the HEMT in the case of the same, the ohmic contact resistance per unit width may be less than 1/10. Therefore, for example, a device having an ohmic contact resistance per unit width larger than 0.1 Ω / mm and 1.0 Ω / mm or less, such as the GaN-HEMT according to Non-Patent Document 2 described above. By applying the structure according to the first embodiment, the ohmic contact resistance per unit width in the GaN-HEMT can be reduced to 0.1 Ω / mm or less.

<Second Embodiment>
In the second embodiment, as in the first embodiment described above, the contact width _{W C1} and _{W C2} of the GaN-HEMT is described semiconductor device is 10 times the gate width _{W G.}

  The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in the planar shape of the active region. Since other components and operational effects are the same as those of the first embodiment, common components are denoted by the same reference numerals, and redundant description thereof is omitted.

  FIG. 3 is a schematic diagram for explaining the second embodiment of the present invention, and is a plan view of the base as seen from the upper surface, that is, the surface on which elements such as FETs are formed. In FIG. 3, as in FIG. 1, for example, an upper layer such as an interlayer insulating layer and an upper wiring layer is omitted in order to clearly show the characteristic portion according to the second embodiment.

  In the second embodiment, the region between the first overlapping region 29a and the third overlapping region 35, that is, the first intermediate region 45, and the region between the second overlapping region 29b and the third overlapping region 35, that is, the second intermediate region. The planar shape of the region 47 is changed from the planar shape of the first intermediate region 39 and the second intermediate region 41 (see FIG. 1A) in the first semiconductor device described above.

That is, in the second embodiment, as in the first embodiment described above, the first and second overlapping regions 29a and 29b, which are regions that are substantially in ohmic contact in the active region 11b, The gate electrode 15 is formed with a width of 10 times or more along the gate width direction 31 as compared with the third overlapping region 35 which is a region for applying a voltage to the active region 11b. As a result, the contact width _{W C1} and _{W C2} is 10 times or more the width of the gate width _{W G.}

  A region between the first overlapping region 29 a and the third overlapping region 35, that is, the first intermediate region 45 includes a first contact width region 49 and a first gate width region 51.

The first contact width region 49 has the same width as the contact width W _C1 along the gate width direction 31, and extends from the first overlap region 29 a toward the third overlap region 35 along the gate length direction 33. is doing.

The first gate width region 51 has a width along the gate width direction 31 is the gate width W _G of the same width, extending from the third overlapping region 35 along the gate length direction towards the first overlapping region 29a ing.

  A region between the second overlapping region 29 b and the third overlapping region 35, that is, the second intermediate region 47 includes a second contact width region 53 and a second gate width region 55.

The second contact width region 53 has the same width as the contact width _WC2 along the gate width direction 31 and extends from the second overlapping region 29b toward the third overlapping region 35 along the gate length direction 33. is doing.

The first gate width region 55 has a width along the gate width direction 31 is the gate width W _G of the same width, extending from the third overlapping region 35 along the gate length direction towards the second overlapping region 29b ing.

  The region outside the active region 11b of the base 13 is an inactive region 43 as an element isolation region, as in the first embodiment described above.

  By forming the active region 11b in such a planar shape, in the semiconductor device according to the second embodiment, the areas of the first intermediate region 45 and the second intermediate region 47 are set to the above-described first embodiment. As compared with the first intermediate region 39 and the second intermediate region 41 (see FIG. 1A) in the semiconductor device according to FIG.

That is, the widths along the gate width direction 31 of the first intermediate region 39 and the second intermediate region 41 (see FIG. 1A) in the first semiconductor device described above gradually toward the third overlapping region 35, respectively. It becomes narrow. On the other hand, in the semiconductor device according to the second embodiment, the first intermediate region 45 includes a first contact width region 49 whose width along the gate width direction 31 is the same as the contact width W _C1 , and width along the gate width direction 31 consists of a first gate width region 51 is the same width and the gate width W _G. The second intermediate region 47 includes a second contact width region 53 and a second gate width region 55. Therefore, in the semiconductor device according to the second embodiment, the lengths L _G-C1 and L _G-C2 of the first gate width region 51 and the second gate width region 55 along the gate length direction 33 are made as short as possible. By setting the ratio of the area occupied by the first contact width region 49 and the second contact width region 53 in the first intermediate region 45 and the second intermediate region 47, the first gate width region 51 and the second gate width region Larger than 55. Thus, in the semiconductor device according to the second embodiment, the areas of the first intermediate region 45 and the second intermediate region 47 are set to be the same as the first intermediate region 39 and the second intermediate region 41 (see FIG. 1 (A)).

  As a result, in the semiconductor device according to the second embodiment, during the operation of the semiconductor device, the resistance generated between the gate electrode 15 and the first and second main electrodes 17a and 17b is reduced in the first half implementation. It can reduce compared with the semiconductor device by a form. Therefore, as a matter of course, the source-gate resistance generated between the first main electrode 17a or the second main electrode 17b used as the source electrode and the gate electrode 15 during the operation of the semiconductor device is reduced. Thereby, in the semiconductor device according to the second embodiment, the source resistance which is the sum of the source-gate resistance and the ohmic contact resistance is reduced as compared with the semiconductor device according to the first semi-embodiment. As a result, since the semiconductor device according to the second embodiment can efficiently suppress the parasitic resistance of the mutual conductance, it can be said to be an advantageous structure in improving the operating characteristics of the HEMT.

By the way, in the semiconductor device according to the second embodiment, in the manufacturing process, first, a mask is formed on the base 13 using, for example, a well-known resist technique, and then a well-known etching technique or ion implantation technique is used. To form an inactive region 43. Then, the remaining non-etched region or non-ion-implanted region as the lower region of the mask becomes the active region 11b. As already described, in the semiconductor device according to the second embodiment, the first gate width region 51 and the second gate width are set to increase the areas of the first intermediate region 45 and the second intermediate region 47. The lengths L _G-C1 and L _G-C2 of the region 55 are set as short as possible. Therefore, in the semiconductor device according to the second embodiment, the dimensional error of the non-active region 43 and the active region 11b formed in the step of forming the non-active region 43 and the active region 11b, that is, for example, pattern matching of the mask described above. taking into account the margin and the like, the length _{L G-C1} and _{L G-C2} for example, preferably set to about 0.4 .mu.m.

  As described above, in the semiconductor device according to the second embodiment, the active region 11b is formed in the above-described planar shape, so that the ohmic contact resistance in the GaN-HEMT is 0.1Ω as in the first embodiment. In addition to being able to reduce to / mm or less, the source resistance can also be reduced.

<Third Embodiment>
In the third embodiment, as in the first embodiment and the second embodiment described above, is 10 times or more contact width _{W C1} and _{W C2} of the gate width _{W G} of the GaN-HEMT semiconductor The apparatus will be described.

The semiconductor device according to the third embodiment, described above in that formed for the contact width W _C1 and W _C2 and the gate width W _G to be formed in the above-mentioned ratio, a non-active region below the gate electrode This is different from the semiconductor device according to the first embodiment and the second embodiment. Since other components and operational effects are the same as those of the first embodiment and the second embodiment, common components are denoted by the same reference numerals, and redundant description thereof is omitted. .

  FIG. 4 is a schematic diagram for explaining the third embodiment of the present invention, and is a plan view of the base as seen from the upper surface, that is, the surface on which an element such as an FET is formed. In FIG. 4, as in FIGS. 1 and 3, for example, an upper layer such as an interlayer insulating layer and an upper wiring layer is omitted in order to clearly show the characteristic portion according to the third embodiment.

  In the third embodiment, the active region 11c is formed in a rectangular shape by a non-active region 43 as an element isolation region, as in a known general semiconductor device (for example, see Patent Document 2 described above). Has been.

  In the third embodiment, similarly to the first and second embodiments described above, the first and second regions which are regions that substantially take ohmic contact in the active region 11c. The overlapping regions 29a and 29b have a width of 10 times or more along the gate width direction 31 as compared with the third overlapping region 35 in which the gate electrode 15 substantially applies a voltage to the active region 11c. To do. Therefore, in the third embodiment, the inactive region 57 is formed below the lower gate electrode 15 of the gate electrode 15, that is, in the third overlapping region 35 in the active region 11 c of the base 13. .

Thus, by forming the inactive region 57 in the third overlapping region 35, the region where the gate electrode 15 contacts the active region 11 c in the third overlapping region 35 is divided by the inactive region 57. Thus, even substantial gate width W _G is divided, shortened. Zunawachi, in the third overlapping region 35, of each region 35a in which the non-active region 57 remained as an active region without being formed, the sum of the width W _g along the gate width direction 31 is substantially gate width the W _G. Accordingly, in the third embodiment, by adjusting the respective width W _g, it is possible to contact width W _C1 and W _C2 and 10 times the width of the gate width W _G.

In the third embodiment, by forming a non-active region 57, to the contact width W _C1 and W _C2 and 10 times the width of the gate width W _G, the area of the active region 11c, the above-described 1 Compared with the active regions 11a and 11b in the second embodiment and the second embodiment, it can be further expanded. Therefore, in the third embodiment, not only can the ohmic contact resistance be reduced to 0.1 Ω / mm or less in the GaN-HEMT, as in the first embodiment and the second embodiment, but also the first Compared with the second embodiment and the second embodiment, the source resistance can be reduced more efficiently.

  At least one inactive region 57 is disposed so as to be separated from each other along the gate width direction 31. In the third embodiment, the entire inactive region 57 is disposed in the third overlapping region 35, or the inactive region 57 is disposed from the third overlapping region 35 to the outside of the third overlapping region 35. Any of the configurations arranged across the board may be used. FIG. 4 shows a configuration example in which four inactive regions 57 are respectively disposed in the third overlapping region 35 as a whole.

  The inactive region 57 is not formed as a trench by etching but is formed as an impurity introduction region into which Ar ions or the like are introduced by ion implantation without providing a step on the upper surface 13a of the base 13. preferable. Thus, by forming the inactive region 57 as the impurity introduction region, in the semiconductor device according to the third embodiment, the heat concentration generated in each region 35a during operation is dispersed. As a result, in the third embodiment, not only the ohmic contact resistance and the source resistance can be reduced, but also a semiconductor device having good temperature characteristics can be provided.

FIG. 2A is a plan view for explaining a first embodiment of the present invention. (B) is the end elevation which looked at the cut in the II line | wire shown to (A) from the arrow direction. It is the figure which simulated the correlation of the ohmic contact resistance in GaN-HEMT, and drain current. It is a top view explaining 2nd Embodiment of this invention. It is a top view explaining the 3rd Embodiment of this invention.

Explanation of symbols

11a, 11b, 11c: active region 13: base 15: gate electrodes 17a, 17b: first and second main electrodes 19: GaN layer 21: AlGaN layer 23: substrate 25: buffer layer 27: two-dimensional electron gas layer (2DEG layer)
29a, 29b: first and second overlapping regions 31: gate width direction 33: gate length direction 35: third overlapping region 39, 45: first intermediate region 41, 47: second intermediate region 43, 57: inactive region 49: First contact width region 51: First gate width region 53: Second contact width region 55: Second gate width region

Claims (7)

A substrate including a GaN layer and an active region generated due to the GaN layer;
A gate electrode formed on the active region;
A first and a second main electrode formed in the active region, spaced apart and opposed to each other across the gate electrode;
The width W _C1 and the width W _C2 along the gate width direction of the first and second overlapping regions where the first and second main electrodes and the active region overlap each other are such that the gate electrode and the active region overlap each other. of 3 overlapping region, wherein a said at least 10 times the gate width direction to the width W _G along. The semiconductor device according to claim 1,
The base comprises a two-dimensional electron gas layer across the active region in a plane perpendicular to the thickness direction of the GaN layer in the GaN layer,
The semiconductor device according to claim 1, wherein the first and second main electrodes are formed so as to penetrate from the upper surface of the base into the base to a position deeper than the two-dimensional electron gas layer. The semiconductor device according to claim 2,
A length of the first and second overlapping regions along the gate length is 0.5 to 10.0 μm. The semiconductor device according to any one of claims 1 to 3,
In the region between the first overlap region and the third overlap region, the active region gradually decreases in width along the gate width direction from the first overlap region toward the third overlap region. Continue
In the region between the second overlap region and the third overlap region, the width along the gate width direction gradually decreases from the second overlap region toward the third overlap region. A semiconductor device. The semiconductor device according to any one of claims 1 to 3,
The active region has the same width as the width W _{C1 in the} region between the first overlap region and the third overlap region, and extends from the first overlap region toward the third overlap region along the gate length direction. a first contact width region extending Te, with the same width and the width W _G, a first gate width region extending towards the first overlapping region from the third overlap region along the gate length direction Consisting of
In the region between the second overlap region and the third overlap region, the second overlap region has the same width as the width W _C2 and extends from the second overlap region toward the third overlap region along the gate length direction. features and second contact width region, in the width W _G of the same width, that consist in the gate length direction from the third overlapping region and the second gate width region extending towards the second overlap area A semiconductor device. The semiconductor device according to any one of claims 1 to 3,
The underlayer includes at least one inactive region disposed in the active region and below the gate electrode and spaced from each other along the gate width direction. apparatus. The semiconductor device according to claim 6,
A semiconductor device characterized in that the inactive region in the previous period is formed as an impurity introduction region.

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