CN110364561B - Semiconductor structure and forming method thereof - Google Patents

Abstract

The invention discloses a semiconductor structure and a method for forming the same. The semiconductor structure includes: a first active region and a second active region formed in a semiconductor substrate at intervals; a connecting gate, one of which is formed On one of the first active regions and one of the second active regions, and one of the connection gates is located between one of the first active regions and one of the second active regions, there is a connecting portion , the extension direction of the connecting portion is inconsistent with the arrangement direction of the first active region and the second active region; and a silicide layer, the silicide layer covers the first active region and the second active region on the two active regions and across the connecting portion along the connecting portion. Therefore, through the special design of the silicide layer, the silicide on the connection portion connected to the gate is complete, that is, the quality of the silicide is guaranteed, thereby effectively reducing the load of the active region and increasing the saturation current of the device during operation.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a forming method thereof.

Background technique

With the continuous development of CMOS technology, submicron devices have been widely used. However, contact resistance and sheet resistance increase due to the small gate and source/drain contact areas formed in sub-micron MOS devices. This greatly reduces the operating speed of the semiconductor device.

Salicide formation process The formation of silicides in the gate and source/drain regions can effectively reduce the sheet resistance and contact resistance, so that the saturation current of the device can be improved. However, how to ensure the quality of silicide still needs to be optimized.

Contents of the invention

The object of the present invention is to provide a semiconductor structure and its forming method, which can improve the quality of silicide.

In order to solve the above technical problems, the present invention provides a semiconductor structure, comprising:

separating the first active region and the second active region formed in the semiconductor substrate;

A connection gate, one of the connection gates is formed on one of the first active regions and one of the second active regions, and one of the connection gates is located on one of the first active regions and one of the There is a connecting portion between the second active regions, and the extending direction of the connecting portion is not consistent with the arrangement direction of the first active region and the second active region; and

A silicide layer, the silicide layer covering the first active region and the second active region, and straddling the connecting portion along the connecting portion.

Optionally, for the semiconductor structure, the connecting portion is in the shape of a zigzag line, including a first part, a second part and a third part connected in sequence.

Optionally, for the semiconductor structure, the second portion is perpendicular to the first portion and the third portion.

Optionally, for the above semiconductor structure, the silicide layer includes a first following part, a spanning part and a second following part connected in sequence, the first following part corresponds to the first part and is located in the The first part is close to the side of the second part, the spanning part straddles the second part, the second following part corresponds to the third part and is located on the side of the third part close to the second part .

Optionally, for the above semiconductor structure, the first following portion partially overlaps the first portion.

Optionally, for the above semiconductor structure, the second following portion partially overlaps the third portion.

Optionally, for the semiconductor structure, the width of the overlapping portion is less than or equal to 0.1 μm.

Optionally, for the above semiconductor structure, the first following portion is just adjacent to the first portion.

Optionally, for the above semiconductor structure, the second following portion is just adjacent to the third portion.

Optionally, for the semiconductor structure, the first follower portion is separated from the first portion.

Optionally, for the semiconductor structure, the second follower portion is separated from the third portion.

Optionally, for the semiconductor structure, the separation distance is less than or equal to 0.05 μm.

Optionally, for the semiconductor structure, the material of the silicide layer includes at least one element among cobalt, tantalum, titanium, molybdenum, nickel, and tungsten.

The present invention also provides a method for forming a semiconductor structure, comprising:

forming a first active region and a second active region at intervals in the semiconductor substrate;

A connection gate is formed on the semiconductor substrate, one of the connection gates is located on one of the first active regions and one of the second active regions and one of the connection gates is located on one of the first active regions. There is a connecting portion between the active region and one of the second active regions, and the extending direction of the connecting portion is not consistent with the arrangement direction of the first active region and the second active region;

forming a material layer on the semiconductor substrate, covering the first active region and the second active region, and straddling the connecting portion along the connecting portion; and

A silicide treatment is performed on the material layer to form a silicide layer.

In the semiconductor structure and its forming method provided by the present invention, the semiconductor structure includes: a first active region and a second active region formed in a semiconductor substrate at intervals; a connection gate, one of the connection gates is formed on On one of the first active regions and one of the second active regions, and one of the connection gates is located between one of the first active regions and one of the second active regions and has a connection portion, The extension direction of the connecting portion is inconsistent with the arrangement direction of the first active region and the second active region; and a silicide layer covering the first active region and the second active region on the active region and across the connecting portion along the connecting portion. Therefore, by passing the silicide layer across the connection portion along the connection portion, the silicide on the connection portion connected to the gate is complete, that is, the quality of the silicide is guaranteed, thereby effectively reducing the load on the active region and improving the performance of the device. Saturation current during operation.

Description of drawings

1 is a schematic diagram of a semiconductor structure;

Fig. 2 is a schematic cross-sectional view along AA' in Fig. 1;

3 is a schematic diagram of a semiconductor structure in an embodiment of the present invention;

Fig. 4 is a schematic diagram of area S in Fig. 3;

Fig. 5 is another schematic diagram of area S in Fig. 3;

Fig. 6 is another schematic diagram of area S in Fig. 3;

Fig. 7 is a schematic cross-sectional view along BB' in Fig. 3;

FIG. 8 is a schematic diagram of the sheet resistance distribution after detection of the wafer having the semiconductor structure shown in FIG. 1;

FIG. 9 is a current and voltage distribution diagram after detection of a wafer having the semiconductor structure shown in FIG. 1;

FIG. 10 is a schematic diagram of the sheet resistance distribution after detection of the wafer having the semiconductor structure shown in FIG. 3;

FIG. 11 is a current and voltage distribution diagram after inspection of a wafer having the semiconductor structure shown in FIG. 3 .

Detailed ways

The semiconductor structure of the present invention and its formation method will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is represented, it should be understood that those skilled in the art can modify the present invention described here, and still realize the present invention beneficial effect. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

In the following paragraphs the invention is described more specifically by way of example with reference to the accompanying drawings. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

In the following description, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region, pad and/or pattern, it may directly on another layer or substrate, and/or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being 'under' another layer, it can be directly under, and/or one or more intervening layers may also be present. In addition, designations regarding 'on' and 'under' each layer may be made based on drawings.

The inventor has studied a semiconductor structure, as shown in FIG. 1, including a semiconductor substrate 1, and an active region 3 is formed in the semiconductor substrate 1, wherein the active region 3 includes a plurality of, and FIG. 1 shows two One, the two active regions 3 are isolated, the gate structure 4 is formed on the two active regions 3, and spans the two active regions 3, and the gate structure 4 between adjacent active regions 3 The pole structure 4 has a connection part, and the silicide layer 2 is formed on the active region 3 and spans the connection part, specifically, the silicide layer 2 only crosses in the middle of the connection part. It can be seen from FIG. 2 that the gate structure 4 has sidewalls 41 , and the silicide layer 2 covers the sidewalls 41 .

However, the actual detection found that before the input voltage of 0.7V, the current is basically not detected, but after 0.7V, there is a large change, which is quite different from the expected, and the saturation current (Idsat) of the device is reduced by about 50% when it is working. %. It can be seen that the device performance is greatly affected.

After experimental analysis, it is found that, as shown in FIG. 2, there is an abnormality in the transition between the silicide layer 2 and the connection part. Specifically, at the side wall 41, it is found that part of the polysilicon layer 22 is not metallized, that is, the silicide layer 2 is here. is incomplete and, therefore, results in increased loading of the active area.

Based on the above research, the inventor of the present application provides an improved semiconductor structure, including:

separating the first active region and the second active region formed in the semiconductor substrate;

A connection gate, one of the connection gates is formed on one of the first active regions and one of the second active regions, and one of the connection gates is located on one of the first active regions and one of the There is a connecting portion between the second active regions, and the extending direction of the connecting portion is not consistent with the arrangement direction of the first active region and the second active region; and

A silicide layer, the silicide layer covers the first active region and the second active region, and crosses the connecting portion along (extending direction of) the connecting portion.

In one embodiment, as shown in Figure 3, the semiconductor structure of the present invention comprises:

The semiconductor substrate 10, the constituent material of the semiconductor substrate 10 can be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI) and the like. As an example, in this embodiment, the semiconductor substrate 10 is made of single crystal silicon. A buried layer (not shown in the figure) and the like may also be formed in the semiconductor substrate 10 . In addition, for PMOS, an N well (not shown in the figure) can also be formed in the semiconductor substrate 10, and one or more low-dose boron implants can be performed on the entire N well to adjust the threshold of PMOS Voltage Vth.

The first active region 31 and the second active region 32 formed in the semiconductor substrate 10 at intervals; according to actual needs, the first active region 31 and the second active region 32 may be doped with N Type or P-type ions, the doping types can be the same or different.

It can be understood that, in the semiconductor substrate 10 , the first active region 31 and the second active region 32 are surrounded by an isolation structure, that is, the isolation structure isolates each active region.

A connection gate 410, the connection gate 410 is formed on the first active region 31 and the second active region 32, and the connection gate 410 is located on the first active region 31 and the second active region 32 There is a connecting portion between the second active regions 32 , and the extending direction of the connecting portion is not consistent with the arrangement direction of the first active region 31 and the second active region 32 .

That is to say, the connection gate 410 includes a portion located on the active region and a portion located on the isolation structure, and the connection portion is the connection gate 410 located on the isolation structure.

It may include a plurality of first active regions 31 and a plurality of second active regions 32, and a plurality of corresponding connection gates 410, so that each connection gate 410 can be formed on a corresponding first active region 32. region 31 and a second active region 32.

As shown in FIG. 3 , the connecting portion is in the shape of a broken line, and includes a first part 4101 , a second part 4102 and a third part 4103 connected in sequence. It can be understood that, the connecting portion can also be in other shapes, such as oblique lines (that is, the direction intersects with the arrangement direction of the first active region 31 and the second active region 32 ), arcs, etc., all of which are included in Within the idea of the present invention.

One end of the first part 4101 is connected to a part of the connection gate 410 located on the first active region 31, the other end is connected to one end of the second part 4102, and the other end of the second part 4102 is connected to the first One end of the three parts 4103 , the other end of the third part 4103 is connected to a part of the connecting gate 410 on the active region 32 .

Optionally, the second portion 4102 is perpendicular to the first portion 4101 and the third portion 4103 .

A silicide layer 20 , the silicide layer 20 covers the first active region 31 and the second active region 32 , and crosses the connecting portion along the connecting portion.

Optionally, the silicide layer 20 includes a first following portion 201, a spanning portion 202 and a second following portion 203 connected in sequence, the first following portion 201 corresponds to the first portion 4101 and is located at the second A part 4101 is close to one side of the second part 4102, the spanning part 202 straddles the second part 4102, and the second following part 203 corresponds to the third part 4103 and is located close to the third part 4103. One side of the second portion 4102.

In one embodiment, the first following part 201 and the second following part 203 may also be located on opposite sides of the corresponding first part 4101 and third part 4103, in which case it may be necessary to cross the The connecting portion, so the structure shown in FIG. 3 may be a better choice.

Optionally, the widths of the first following portion 201 , the spanning portion 202 and the second following portion 203 may be 100 nm˜500 nm.

Wherein, the positional relationship between the first following part 201 , the second following part 203 and various corresponding first part 4101 and third part 4103 is described below as an example.

As shown in FIGS. 4-6 , the area S in FIG. 3 is taken as an example for illustration, and the area S' in FIG. 3 may be consistent with various situations of the area S, but not limited to being consistent at the same time. As shown in FIG. 4 , the first following portion 201 partially overlaps the first portion 4101 , and it can be understood that the overlapping of the first following portion 201 partially covers the first portion 4101 .

Optionally, the width of the overlapping portion is less than or equal to 0.1 μm.

Correspondingly, for the region S′, the second following portion 203 partially overlaps the third portion 4103 , and similarly, the overlapping of the second following portion 203 partially covers the third portion 4103 .

Optionally, the width of the overlapping portion is less than or equal to 0.1 μm.

As shown in FIG. 5 , it may be that the first following portion 201 is just adjacent to the first portion 4101 .

Correspondingly, for the area S′, the second following portion 203 may be just adjacent to the third portion 4103 .

As shown in FIG. 6 , the first following part 201 may be separated from the first part 4101 .

Optionally, the separation distance is less than or equal to 0.05 μm.

Correspondingly, for the area S′, the second following portion 203 may be separated from the third portion 4103 .

Optionally, the separation distance is less than or equal to 0.05 μm.

In one embodiment, the material of the silicide layer 20 includes at least one element among cobalt, tantalum, titanium, molybdenum, nickel, and tungsten.

Then, the cross-sectional view at BB' of the semiconductor structure of the present invention is shown in FIG. 7 . It can be seen that through the special design of the silicide layer, the gate density at the connection gate 410 is improved, so that the silicide layer 20 is complete, and there is no partial unmetallized situation as shown in FIG. 2 . Then, the silicide on the connecting portion connected to the gate 410 is complete, that is, the quality of the silicide is guaranteed, thereby effectively reducing the load on the active region and increasing the saturation current of the device during operation.

Please refer to Figures 8-11 below, wherein Figure 8 is a schematic diagram of the sheet resistance distribution of the wafer having the semiconductor structure shown in Figure 1 after detection; Figure 9 is the current and voltage of the wafer having the semiconductor structure shown in Figure 1 after detection Distribution diagram; FIG. 10 is a schematic diagram of the sheet resistance distribution of the wafer having the semiconductor structure shown in FIG. 3 after detection; FIG. 11 is a current and voltage distribution diagram of the wafer having the semiconductor structure shown in FIG. 3 after detection.

It can be seen that the square resistance Rs≤15ohm/SQ of the chip unit (shot) shown in FIG. 8 is less, and more are between 15ohm/SQ<Rs≤100ohm/SQ, and some Rs are greater than 100ohm/SQ. Corresponding to the voltage-current relationship diagram shown in Figure 9, the voltage-current relationship shows two parts, including the first relationship part L1 and the second relationship part L2, and the first relationship part L1 shows that in a chip unit The voltage-current relationship of the chip particles (die) in the non-edge part, the second relationship part L2 shows the voltage-current relationship of the chip particles in the edge part in a chip unit, on the one hand, when the voltage is below 0.7V, the current is relatively low Small, it can be seen that especially for the second relationship part L2, when the voltage is below 0.7V, the current is basically 0, and when the voltage is above 0.7V, there is a large change, showing a diode phenomenon, which is different from the active area load analyzed above increase coincides. On the other hand, it can be clearly seen from Fig. 9 that for the same voltage, the current is discrete and the convergence is poor, which means that the performance of different chip particles is quite different.

While the sheet resistance Rs of the chip unit (shot) shown in FIG. 10 is all below 15 ohm/SQ, it can be seen that the structure is better. Corresponding to the voltage-current relationship diagram shown in Figure 11, the voltage-current relationship shows two parts, including the first relationship part L3 and the second relationship part L4, and the first relationship part L3 shows that in a chip unit The voltage-current relationship of the chip particles (die) in the non-edge part. The second relationship part L4 shows the voltage-current relationship of the chip particles in the edge part of a chip unit. On the one hand, the voltage-current variation law is basically linear Changes, showing a resistance relationship between them, not a diode phenomenon. On the other hand, it can be clearly seen from Figure 11 that for the same voltage, the current convergence is good, which means that the performance of different chip particles is not much different, and the reliability is high.

In addition, the present invention also provides a method for forming a semiconductor structure, including:

Step S11, forming a first active region and a second active region at intervals in the semiconductor substrate;

Step S12, forming a connection gate on the semiconductor substrate, one of the connection gates is located on one of the first active regions and one of the second active regions, and one of the connection gates is located on one of the There is a connecting portion between the first active region and one of the second active regions, and the extending direction of the connecting portion is not consistent with the arrangement direction of the first active region and the second active region;

Step S13, forming a material layer on the semiconductor substrate, covering the first active region and the second active region, and crossing the connecting portion along the connecting portion; and

Step S14, performing metallization treatment on the material layer to form a silicide layer.

Combining with the specific structure of the above-mentioned semiconductor structure, those skilled in the art should be able to understand and implement the method of the present invention correctly, and no detailed description is given here.

To sum up, in the semiconductor structure and its forming method provided by the present invention, the semiconductor structure includes: a first active region and a second active region formed in a semiconductor substrate at intervals; a connecting gate, one of the The connection gate is formed on one of the first active regions and one of the second active regions, and one of the connection gates is located between one of the first active regions and one of the second active regions There is a connection part between them, the extension direction of the connection part is not consistent with the arrangement direction of the first active region and the second active region; and a silicide layer, the silicide layer covers the first active region On the source region and the second active region, and across the connecting portion along the connecting portion. Therefore, through the special design of the silicide layer, the silicide on the connection portion connected to the gate is complete, that is, the quality of the silicide is guaranteed, thereby effectively reducing the load of the active region and increasing the saturation current of the device during operation.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (7)

1. A semiconductor structure, characterized in that, comprising: separating the first active region and the second active region formed in the semiconductor substrate; A connection gate, one of the connection gates is formed on one of the first active regions and one of the second active regions, and one of the connection gates is located on one of the first active regions and one of the There is a connecting portion between the second active regions, and the extending direction of the connecting portion is not consistent with the arrangement direction of the first active region and the second active region; and a silicide layer, the silicide layer covering the first active region and the second active region, and straddling the connecting portion along the connecting portion; The connection part includes a first part, a second part and a third part connected in sequence, and the silicide layer includes a first follower part, a span part and a second follower part connected in sequence, the first follower part partially overlaps, Adjacent to or separated from the first portion, the spanning portion straddles the second portion, the second following portion partially overlaps, adjacent to, or separated from the third portion, and the separation distance is less than or equal to 0.05 μm . 2 . The semiconductor structure according to claim 1 , wherein the connecting portion is in a zigzag shape. 3 . 3. The semiconductor structure of claim 2, wherein the second portion is perpendicular to the first portion and the third portion. 4. The semiconductor structure according to claim 3, wherein the first following portion corresponds to the first portion and is located on a side of the first portion close to the second portion, and the second following portion is connected to the second portion. The third part corresponds to and is located on a side of the third part close to the second part. 5. The semiconductor structure according to claim 4, wherein the width of the overlapping portion is less than or equal to 0.1 μm. 6 . The semiconductor structure according to claim 1 , wherein the material of the silicide layer comprises at least one element among cobalt, tantalum, titanium, molybdenum, nickel, and tungsten. 7. A method for forming a semiconductor structure, comprising: forming a first active region and a second active region at intervals in the semiconductor substrate; A connection gate is formed on the semiconductor substrate, one of the connection gates is located on one of the first active regions and one of the second active regions and one of the connection gates is located on one of the first active regions. There is a connecting portion between the active region and one of the second active regions, and the extending direction of the connecting portion is not consistent with the arrangement direction of the first active region and the second active region; forming a material layer on the semiconductor substrate, covering the first active region and the second active region, and straddling the connecting portion along the connecting portion; and performing metallization treatment on the material layer to form a silicide layer; The connection part includes a first part, a second part and a third part connected in sequence, and the silicide layer includes a first follower part, a span part and a second follower part connected in sequence, the first follower part partially overlaps, Adjacent to or separated from the first portion, the spanning portion straddles the second portion, the second following portion partially overlaps, adjacent to, or separated from the third portion, and the separation distance is less than or equal to 0.05 μm .

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