JP2010278280A - High frequency semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-frequency semiconductor device which, for an arbitrary operating frequency, allows selective arrangement of resistances having the optimum resistance value between gate terminal electrodes and suppresses loop oscillation. <P>SOLUTION: The high-frequency semiconductor device includes: gate finger electrodes 24, source finger electrodes 20, and drain finger electrodes 22 each of which is arranged on a first surface of a substrate 10 and has a plurality of fingers; FET cells 40 each having a gate terminal electrode formed by bundling together the fingers of the gate finger electrode 24, a source terminal electrode formed by bundling together the fingers of the source finger electrode 20, and a drain terminal electrode formed by bundling together the fingers of the drain finger electrode 22; and resistors 30 each arranged between gate terminal electrodes. A plurality of distances between gate terminal electrodes of adjacent FET cells 40 can be selected depending on the determined position of the resistance 30. The gate terminal electrode has an electrode pattern that allows selection of a plurality of values for the resistor 30 without changing the pattern size thereof. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a high-frequency semiconductor device, and in particular, to a high-frequency semiconductor device using a semiconductor material suitable for high-frequency operation such as GaAs and GaN, which suppresses loop oscillation at an arbitrary operating frequency. It is in.

  In a high-gain field effect transistor (FET), loop oscillation or frequency division oscillation may occur during high-frequency operation. The presence of FET loop oscillation and frequency division oscillation has a fatal adverse effect on the normal operation of the FET. For this reason, suppressing the loop oscillation of the FET by adjusting the matching circuit is generally performed.

  In general, as the loop oscillation frequency increases, this loop becomes smaller, and thus oscillation occurs in the loop between the FET cells constituting the high-frequency semiconductor device. In order to suppress this loop oscillation, it is effective to electrically divide the high-frequency semiconductor device in units of FET cells.

  Further, during high frequency operation, a phase difference generated between the FET cells causes oscillation. Oscillation based on this phase difference can be suppressed by eliminating a potential difference generated between the FET cells by inserting an appropriate resistor between the divided FET cells.

  For example, as shown in FIG. 23, the conventional high-frequency semiconductor device 125 is formed on a substrate 100, and gate terminal electrodes G <b> 1 to G <b> 4, source terminal electrodes S <b> 1 to S <b> 5 and drain terminals disposed on the first surface of the substrate 100. Electrodes D1 to D4 are provided. In order to suppress oscillation based on the phase difference generated between the FET cells 400, a resistor 300 is inserted between adjacent gate terminal electrodes G1 and G2, G2 and G3, and G3 and G4.

  In the example of FIG. 23, via holes (VIA: through-holes) SC1 to SC5 are formed from the back surface of the substrate 100 in the source terminal electrodes S1 to S5, and a ground conductor is formed on the back surface of the substrate 100. When the circuit element is grounded, the circuit element provided on the substrate 100 and the ground conductor formed on the back surface of the substrate 100 are electrically connected via the VIA holes SC1 to SC5 penetrating the substrate 100.

  Each FET cell 400 includes a multi-finger structure including a plurality of source finger electrodes 200, a plurality of gate finger electrodes 240, and a plurality of drain finger electrodes 220.

  The phase difference generated between the FET cells 400 is caused by, for example, a difference in electrical length from each gate terminal electrode G1 to G4 of each FET cell 400 to each gate finger electrode 240, and the layout and operating frequency of the FET cell 400 and the matching circuit. It depends on the oscillation mode. This means that an appropriate resistance value of the resistor 300 to be inserted between the adjacent gate terminal electrodes G1 and G2, G2 and G3, and G3 and G4 of the FET cell 400 changes for each operating frequency.

  Conventionally, the resistance between FET cells is formed of a semiconductor substrate or a metal thin film, and a method of changing the resistance value according to the pattern size is used. In particular, Patent Document 1 discloses a technique in which the resistance value of a resistor disposed between the drain electrodes of an FET cell is changed according to the pattern size of the semiconductor substrate (see, for example, Patent Document 1).

  Therefore, in order to change the resistance value, the pattern size of the resistor, the distance between adjacent gate terminal electrodes, the sheet resistance of the semiconductor substrate constituting the resistor, the film thickness of the metal thin film constituting the resistor, etc. There was a need to change.

  However, the method of changing the sheet resistance of the semiconductor substrate that constitutes the resistor, the film thickness of the metal thin film that constitutes the resistor, and the like cannot greatly change the resistance value of the resistor.

  In addition, changing the pattern size of the resistor requires a great deal of cost because it is necessary to create a new exposure mask.

  In addition, changing the pattern size of the resistor for each high-frequency semiconductor device having a different operating frequency increases the cost and becomes a problem.

Japanese Patent No. 2735403 (2nd page, FIG. 3)

  The object of the present invention is that a resistor having an optimum resistance value can be selectively arranged between the gate terminal electrodes and / or between the drain terminal electrodes for any operating frequency without changing the pattern size. An object of the present invention is to provide a high-frequency semiconductor device that suppresses loop oscillation and frequency division oscillation.

  According to one aspect of the present invention for achieving the above object, a substrate, a gate finger electrode, a source finger electrode and a drain finger electrode which are disposed on a first surface of the substrate and each have a plurality of fingers, and the substrate An FET cell having a gate terminal electrode, a source terminal electrode and a drain terminal electrode formed by bundling a plurality of fingers for each of the gate finger electrode, the source finger electrode and the drain finger electrode, A resistor disposed between the gate terminal electrodes of the adjacent FET cells, and a plurality of distances between the gate terminal electrodes of the adjacent FET cells can be selected depending on a position where the resistor is disposed. A high frequency semiconductor device is provided.

  According to the present invention, a resistor having an optimum resistance value can be selectively arranged between the gate terminal electrodes and / or between the drain terminal electrodes without changing the pattern size with respect to an arbitrary operating frequency. A high-frequency semiconductor device that suppresses loop oscillation and frequency division oscillation can be provided.

1 is a schematic plane pattern configuration diagram of a high-frequency semiconductor device according to a first embodiment of the present invention. The typical circuit block diagram of the high frequency semiconductor device which concerns on the 1st Embodiment of this invention corresponding to FIG. The typical cross-section block diagram which follows the II line | wire of FIG. 1 (the example 1 of a structure of a resistor). The typical cross-section block diagram which follows the II line | wire of FIG. 1 (example 2 of a structure of a resistor). The typical cross-section block diagram which follows the II line | wire of FIG. 1 (the example 3 of a structure of a resistor). FIG. 2 is a schematic cross-sectional configuration diagram taken along line II-II in FIG. 1 (FET cell structure example 1). FIG. 2 is a schematic cross-sectional configuration diagram taken along the line II-II in FIG. 1 (structure example 2 of an FET cell). FIG. 2 is a schematic cross-sectional configuration diagram taken along the line II-II in FIG. 1 (structure example 3 of an FET cell). FIG. 2 is a schematic cross-sectional configuration diagram taken along line II-II in FIG. 1 (structure example 4 of an FET cell). The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 1 of the 1st Embodiment of this invention. (A) A schematic plane pattern configuration diagram of a gate terminal electrode and a resistor portion of a high-frequency semiconductor device according to Modification 2 of the first embodiment of the present invention, (b) of the first embodiment of the present invention. The typical plane pattern block diagram of the gate terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 3. FIG. (A) A schematic plane pattern configuration diagram of a gate terminal electrode and a resistor portion of a high-frequency semiconductor device according to Modification 4 of the first embodiment of the present invention, (b) of the first embodiment of the present invention. The typical plane pattern block diagram of the gate terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 5. FIG. (A) Schematic plane pattern block diagram of the gate terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 6 of the 1st Embodiment of this invention, (b) Of the 1st Embodiment of this invention The typical plane pattern block diagram of the gate terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 7. FIG. (A) Schematic plane pattern block diagram of the gate terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 8 of the 1st Embodiment of this invention, (b) Of the 1st Embodiment of this invention The typical plane pattern block diagram of the gate terminal electrode of a high frequency semiconductor device which concerns on the modification 9, and a resistor part. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the 2nd Embodiment of this invention. The schematic circuit block diagram of the high frequency semiconductor device which concerns on the 2nd Embodiment of this invention corresponding to FIG. The typical circuit block diagram of the high frequency semiconductor device which concerns on the modification 1 of the 2nd Embodiment of this invention. The typical plane pattern block diagram of the high frequency semiconductor device which concerns on the modification 2 of the 2nd Embodiment of this invention. (A) Schematic plane pattern block diagram of the drain terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 3 of the 2nd Embodiment of this invention, (b) Of the 2nd Embodiment of this invention The typical plane pattern block diagram of the drain terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 4. FIG. (A) Schematic plane pattern block diagram of the drain terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 5 of the 2nd Embodiment of this invention, (b) Of the 2nd Embodiment of this invention The typical plane pattern block diagram of the drain terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 6. FIG. (A) Schematic plane pattern block diagram of the drain terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 7 of the 2nd Embodiment of this invention, (b) Of the 2nd Embodiment of this invention The typical plane pattern block diagram of the drain terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 8. FIG. (A) Schematic plane pattern block diagram of the drain terminal electrode and resistor part of the high frequency semiconductor device which concerns on the modification 9 of the 2nd Embodiment of this invention, (b) Of the 2nd Embodiment of this invention FIG. 16 is a schematic plan pattern configuration diagram of a drain terminal electrode and a resistor portion of a high-frequency semiconductor device according to Modification 10; The typical plane pattern block diagram of the high frequency semiconductor device which concerns on a prior art example.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following, the same reference numerals are assigned to the same blocks or elements to avoid duplication of explanation and simplify the explanation. It should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention. In the embodiments of the present invention, the arrangement of each component is as follows. Not specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
(High-frequency semiconductor device)
A schematic planar pattern configuration of the high-frequency semiconductor device according to the first embodiment of the present invention is expressed as shown in FIG. A schematic circuit configuration corresponding to FIG. 1 is expressed as shown in FIG.

  In the high-frequency semiconductor device 25 according to the first embodiment, the FET cell 40 is disposed on the substrate 10 and the first surface of the substrate 10, each having a plurality of fingers, a gate finger electrode 24, a source finger electrode 20, and a drain. A finger terminal 22 and gate terminal electrodes G1 to G4 disposed on the first surface of the substrate 10 and formed by bundling a plurality of fingers for each of the gate finger electrode 24, the source finger electrode 20 and the drain finger electrode 22, and a source terminal electrode S1 to S5 and drain terminal electrodes D1 to D4.

  In the FET cell 40, the plurality of gate finger electrodes 24 are connected to the gate bus line 24a, and the gate bus line 24a is connected to the gate terminal electrodes G1 to G4 via the gate bus line 24b.

  A resistor 30 is disposed between the gate terminal electrodes G1 to G4 of the adjacent FET cells 40. A plurality of distances between the gate terminal electrodes G <b> 1 to G <b> 4 of the adjacent FET cells 40 can be selected depending on the position where the resistor 30 is disposed.

  Further, the gate terminal electrodes G1 to G4 have an electrode pattern shape in which a plurality of pattern sizes of the resistor 30 can be selected. That is, FIG. 1 discloses an example in which the gate terminal electrodes G1 to G4 have an inverted trapezoidal shape, and the distance between the side portions between the adjacent gate terminal electrodes G1 to G4 is an upper bottom portion of the trapezoid. And the bottom is very different. For this reason, by appropriately selecting the patterning position of the resistor 30, a plurality of values of the resistor 30 can be selected without changing the pattern size. That is, in FIG. 1, the pattern size of the resistor 30 is not changed by performing the patterning of the resistor 30 on the vertical positions between the adjacent gate terminal electrodes G1 and G2, G2 and G3, and G3 and G4. In addition, the resistance value can be changed.

  In the high-frequency semiconductor device 25 according to the first embodiment, the value of the resistor 30 necessary to stop the loop oscillation of each mode such as the odd mode and the even mode or the division oscillation of the operating frequency is optimized. can do. In addition, the required value of the resistor 30 can be optimized according to the operating frequency of the high-frequency semiconductor device 25. In FIG. 2, the resistor 30 is represented by RG, and the FETs constituting the FET cell 40 are represented by Q1 to Q4, and the gate terminal electrode G1 adjacent to the loop oscillation or the divided oscillation of the operating frequency is provided. It can be stopped by a resistor RG connected between .about.G4.

  Here, the value of the resistor 30 can be appropriately selected from several Ω to several hundred Ω depending on the operating frequency. In the high-frequency semiconductor device 25 according to the first embodiment, the value of the resistor 30 is, for example, about 50Ω to 100Ω for an operating frequency of about 8 GHz to 14 GHz.

  In the configuration example of FIG. 1, for example, the cell width W1 is about 120 μm, W2 is about 80 μm, the cell length W3 is about 100 μm, W4 is about 120 μm, and the gate width is 100 μm × 6 lines × 4 cells = 2.40 mm or so.

  As shown in FIG. 1, in the high-frequency semiconductor device 25 according to the first embodiment, the VIA holes SC1 to SC5 arranged below the source terminal electrodes S1 to S5 and the first surface of the substrate 10 are opposite to each other. A ground electrode disposed on the second surface on the side and connected to the source terminal electrodes S1 to S5 via the VIA holes SC1 to SC5 may be provided.

  On the other hand, there is a structure in which the VIA holes SC1 to SC5 are not particularly arranged below the source terminal electrodes S1 to S5. In this case, for example, a side electrode is disposed on the side surface of the substrate 10 to provide a ground potential to the source terminal electrodes S1 to S5, and the source terminal electrodes S1 to S5 and the second surface of the substrate 10 are provided. You may employ | adopt the structure which connects the arrange | positioned grounding conductor. Alternatively, the ground potential can be applied to the source terminal electrodes S1 to S5 by wire bonding.

  In the high-frequency semiconductor device according to the first embodiment, the substrate 10 is, for example, a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, or GaN / AlGaN on a SiC substrate. The heterojunction epitaxial layer can be formed of any one of a substrate, a sapphire substrate, and a diamond substrate.

(Configuration of resistor)
(Configuration example 1)
As a schematic cross-sectional configuration taken along the line I-I in FIG. 1, the configuration example 1 of the resistor 30 includes a metal thin film layer 36 disposed directly on the substrate 10 and a metal thin film layer 36 as shown in FIG. 3. Gate terminal electrodes G1 and G2 are provided at both ends. A predetermined resistance RG can be formed between the gate terminal electrodes G1 and G2 by adjusting the thickness and pattern size of the metal thin film layer 36 disposed directly on the substrate 10. The metal thin film layer 36 can be formed of, for example, Al, Au, Pt, Ti, Mo, W, or a multilayer film thereof. The substrate 10 can be formed of, for example, a semi-insulating GaAs substrate. The gate terminal electrodes G1 and G2 can be made of, for example, Al.

  In FIG. 3, the structure of the resistor 30 disposed between the gate terminal electrodes G1 and G2 has been described. However, the resistor 30 disposed between the gate terminal electrodes G2 and G3, and between the gate terminal electrodes G3 and G4. The resistor 30 and the like disposed on the substrate can be formed in the same manner as in FIG.

(Configuration example 2)
As a schematic cross-sectional configuration along the line II in FIG. 1, the configuration example 2 of the resistor 30 includes a diffusion layer 32 formed by ion implantation or the like on the substrate 10 and a diffusion layer as shown in FIG. Insulating layer 34 disposed on 32, and gate terminal electrodes G 1 and G 2 disposed on both ends of diffusion layer 32 by patterning insulating layer 34. By adjusting the depth and pattern size of the diffusion layer 32 formed on the substrate 10, a predetermined resistance RG can be formed between the gate terminal electrodes G1 and G2. The diffusion layer 32 can be formed by ion implantation of B, Al, or the like, for example. The substrate 10 can be formed of, for example, a semi-insulating GaAs substrate. The gate terminal electrodes G1 and G2 can be made of, for example, Al. The insulating layer 34 can be formed by, for example, an oxide film, a nitride film, or the like formed by a chemical vapor deposition (CVD) method.

  When forming the resistor 30, the diffusion layer is formed only in the region for forming the isolation region, and only the patterning of the substrate 10 is performed without forming the diffusion layer 32 in the formation portion of the resistor 30. You may do it.

  In FIG. 4, the structure of the resistor 30 disposed between the gate terminal electrodes G1 and G2 has been described. However, the resistor 30 disposed between the gate terminal electrodes G2 and G3 and between the gate terminal electrodes G3 and G4 are described. The resistor 30 and the like arranged in the above can be formed in the same manner.

(Configuration example 3)
As a schematic cross-sectional configuration taken along the line I-I in FIG. 1, a configuration example 3 of the resistor 30 includes an insulating layer 34 disposed on the substrate 10, and an insulating layer 34 as illustrated in FIG. 5. After patterning the metal thin film layer 36, the insulating layer 34, and the metal thin film layer 36, gate terminal electrodes G1 and G2 disposed at both ends of the metal thin film layer 36 are provided. A predetermined resistance RG can be formed between the gate terminal electrodes G1 and G2 by adjusting the thickness and pattern size of the metal thin film layer 36 disposed on the substrate 10 via the insulating layer 34. The insulating layer 34 can be formed of, for example, an oxide film or a nitride film formed by a CVD method. The metal thin film layer 36 can be formed of, for example, Al, Au, Pt, Ti, Mo, W, or a multilayer film thereof. The substrate 10 can be formed of, for example, a semi-insulating GaAs substrate. The gate terminal electrodes G1 and G2 can be made of, for example, Al. The structure in FIG. 5 is an effective structure when a conductive semiconductor substrate is applied as the substrate 10.

  In FIG. 5, the structure of the resistor 30 disposed between the gate terminal electrodes G1 and G2 has been described. However, the resistor 30 disposed between the gate terminal electrodes G2 and G3 and between the gate terminal electrodes G3 and G4 are described. The resistor 30 and the like disposed on the substrate can be formed in the same manner as in FIG.

(FET cell structure)
(Structural example 1)
As a schematic cross-sectional configuration taken along the line II-II in FIG. 1, a configuration example 1 of the FET cell includes a substrate 10, an epitaxial growth layer 12 disposed on the substrate 10, and a GaN epitaxial growth layer 12 as shown in FIG. 6. An electron supply layer 18 disposed above, and a source finger electrode 20, a gate finger electrode 24, and a drain finger electrode 22 disposed on the electron supply layer 18 are provided. A two-dimensional electron gas (2DEG) layer 16 is formed at the interface between the epitaxial growth layer 12 and the electron supply layer 18. In the configuration example 1 shown in FIG. 6, a high electron mobility transistor (HEMT) is shown.

Specifically, in the case of a GaAs HEMT, the substrate 10 is formed of a GaAs substrate, the epitaxial growth layer 12 is formed of a GaAs layer, and the electron supply layer 18 is formed of, for example, an aluminum gallium arsenide layer (Al _y Ga _{1 -y} As) (0.1 ≦ y ≦ 1). In the case of a GaN-based HEMT, the substrate 10 is formed of a GaN substrate or a SiC substrate, the epitaxial growth layer 12 is formed of a GaN layer, and the electron supply layer 18 is, for example, an aluminum gallium nitride layer (Al _x Ga _{1). -x} N) (formed by 0.1 ≦ x ≦ 1).

(Structural example 2)
As a schematic cross-sectional configuration along the line II-II in FIG. 1, the configuration example 2 of the FET cell includes a substrate 10, an epitaxial growth layer 12 disposed on the substrate 10, and an epitaxial growth layer 12 as shown in FIG. 7. Source region 26 and drain region 28 disposed on the source region 26, source finger electrode 20 disposed on the source region 26, gate finger electrode 24 disposed on the epitaxial growth layer 12 and drain finger electrode disposed on the drain region 28 22. A Schottky contact is formed at the interface between the epitaxial growth layer 12 and the gate finger electrode 24. In the configuration example 2 shown in FIG. 7, a metal-semiconductor field effect transistor (MESFET) is shown. For example, in the case of a GaAs MESFET, the substrate 10 is formed of a GaAs substrate, and the epitaxial growth layer 12 is formed of an epitaxially grown GaAs layer. The source region 26 and the drain region 28 can be formed by ion implantation of Si ions or the like.

(Structural example 3)
As a schematic cross-sectional configuration along the line II-II in FIG. 1, the configuration example 3 of the FET cell includes a substrate 10, an epitaxial growth layer 12 disposed on the substrate 10, and an epitaxial growth layer 12 as shown in FIG. , The source finger electrode 20 and the drain finger electrode 22 disposed on the electron supply layer 18, and the gate finger electrode 24 disposed in a recess portion on the electron supply layer 18. A 2DEG layer 16 is formed at the interface between the epitaxial growth layer 12 and the electron supply layer 18. In the configuration example 3 illustrated in FIG. 8, the HEMT is illustrated.

Specifically, in the case of a GaAs HEMT, the substrate 10 is formed of a GaAs substrate, the epitaxial growth layer 12 is formed of a GaAs layer, and the electron supply layer 18 is formed of, for example, an aluminum gallium arsenide layer (Al _y Ga _{1 -y} As) (0.1 ≦ y ≦ 1). In the case of a GaAs-based HEMT, an active layer may be formed in the electron supply layer 18 immediately below the gate finger electrode 24 by ion implantation of Si ions or the like.

In the case of a GaN-based HEMT, the substrate 10 is formed of a GaN substrate or a SiC substrate, the epitaxial growth layer 12 is formed of a GaN layer, and the electron supply layer 18 is, for example, an aluminum gallium nitride layer (Al _x Ga _{1). -x} N) (0.1 ≦ x ≦ 1).

(Structural example 4)
As a schematic cross-sectional configuration along the line II-II in FIG. 1, a configuration example 4 of the FET cell includes a substrate 10, an epitaxial growth layer 12 disposed on the substrate 10, and an epitaxial growth layer 12 as shown in FIG. 9. An electron supply layer 18 disposed on the electron supply layer 18, a source finger electrode 20 and a drain finger electrode 22 disposed on the electron supply layer 18, and a gate finger electrode 24 disposed in a two-stage recess on the electron supply layer 18. Prepare. A 2DEG layer 16 is formed at the interface between the epitaxial growth layer 12 and the electron supply layer 18. In the configuration example 4 illustrated in FIG. 9, the HEMT is illustrated.

As a specific material, in the case of GaAs-based HEMT, the substrate 10 is formed by a GaAs substrate, epitaxial layer 12 is formed of a GaAs layer, the electron supply layer 18 is, for example, aluminum gallium arsenide layer (Al _y Ga _{1 -y} As) (0.1 ≦ y ≦ 1). In the case of a GaAs-based HEMT, an active layer may be formed in the electron supply layer 18 immediately below the gate finger electrode 24 by ion implantation of Si ions or the like.

In the case of a GaN-based HEMT, the substrate 10 is formed of a GaN substrate or a SiC substrate, the epitaxial growth layer 12 is formed of a GaN layer, and the electron supply layer 18 is, for example, an aluminum gallium nitride layer (Al _x Ga _{1). -x} N) (formed by 0.1 ≦ x ≦ 1).

(Modification)
In the high frequency semiconductor device 25 according to the first embodiment, the gate terminal electrodes G1 to G4 have a trapezoidal shape, a convex shape, an hourglass shape, an elliptical shape, a triangular shape, a step shape, and a torch shape. Further, it may have a shape made of any one of the bee-shaped shapes or a combination thereof.

  A schematic planar pattern configuration of the high-frequency semiconductor device 25 according to the first modification of the first embodiment is expressed as shown in FIG. In Modification 1 shown in FIG. 10, an example is disclosed in which the gate terminal electrodes G1 to G4 have reverse convex shapes. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted. In the first modification shown in FIG. 10, the gate terminal electrodes G1 to G4 are formed in an inverted convex shape, thereby forming a plurality of distances between the gate terminal electrodes G1 and G2, G2 and G3, and G3 and G4. Therefore, the resistance value of the resistor 30 can be easily changed.

  A schematic planar pattern configuration of the gate terminal electrodes G1 to G4 and the resistor 30 portion of the high-frequency semiconductor device 25 according to the second modification of the first embodiment is expressed as shown in FIG. In Modification 2 shown in FIG. 11A, an example in which the gate terminal electrodes G1 to G4 have a trapezoidal shape is disclosed. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  A schematic planar pattern configuration of the gate terminal electrodes G1 to G4 and the resistor 30 portion of the high-frequency semiconductor device 25 according to the third modification of the first embodiment is expressed as shown in FIG. In Modification 3 shown in FIG. 11B, an example in which the gate terminal electrodes G1 to G4 have a drum shape is disclosed. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  A schematic planar pattern configuration of the gate terminal electrodes G1 to G4 and the resistor 30 portion of the high-frequency semiconductor device 25 according to Modification 4 of the first embodiment is expressed as shown in FIG. In Modification 4 shown in FIG. 12A, an example in which the gate terminal electrodes G1 to G4 have a convex shape is disclosed. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  A schematic planar pattern configuration of the gate terminal electrodes G1 to G4 and the resistor 30 portion of the high-frequency semiconductor device 25 according to the fifth modification of the first embodiment is expressed as shown in FIG. In Modification 5 shown in FIG. 12B, an example in which the gate terminal electrodes G1 to G4 have an elliptical shape is disclosed. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  A schematic planar pattern configuration of the gate terminal electrodes G1 to G4 and the resistor 30 portion of the high-frequency semiconductor device 25 according to Modification 6 of the first embodiment is expressed as shown in FIG. In the modification 6 shown to Fig.13 (a), the gate terminal electrodes G1-G4 have disclosed the example which has a torch type | mold shape. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  A schematic planar pattern configuration of the gate terminal electrodes G1 to G4 and the resistor 30 portion of the high-frequency semiconductor device 25 according to Modification 7 of the first embodiment is expressed as shown in FIG. In Modification 7 shown in FIG. 13B, an example in which the gate terminal electrodes G1 to G4 have a bee-shaped shape is disclosed. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  A schematic planar pattern configuration of the gate terminal electrodes G1 to G4 and the resistor 30 portion of the high-frequency semiconductor device 25 according to Modification 8 of the first embodiment is expressed as shown in FIG. In Modification 8 shown in FIG. 14A, an example in which the gate terminal electrodes G1 to G4 have a triangular shape is disclosed. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  A schematic planar pattern configuration of the gate terminal electrodes G1 to G4 and the resistor 30 portion of the high-frequency semiconductor device 25 according to the modification 9 of the first embodiment is expressed as shown in FIG. In Modification 9 shown in FIG. 14B, an example in which the gate terminal electrodes G1 to G4 have a stepped shape is disclosed. The other configuration is the same as that of the first embodiment, and a duplicate description is omitted.

  According to the first embodiment of the present invention and the modifications 1 to 9 thereof, a resistor having an optimum resistance value is set between gate terminal electrodes for any operating frequency without changing the pattern size. A high-frequency semiconductor device that can be selectively arranged and suppresses loop oscillation and frequency division oscillation can be provided.

[Second Embodiment]
A schematic planar pattern configuration of the high-frequency semiconductor device 25a according to the second embodiment of the present invention is expressed as shown in FIG. A schematic circuit configuration corresponding to FIG. 15 is expressed as shown in FIG.

  As shown in FIG. 15, the high-frequency semiconductor device 25a according to the second embodiment includes resistors 50 arranged between the drain terminal electrodes D1 and D2, D2 and D3, and D3 and D4 of adjacent FET cells 40. And a plurality of distances between the drain terminal electrodes can be selected depending on a position where the resistor 50 is disposed. Since other configurations are the same as those of the first embodiment, a duplicate description is omitted.

  In the high-frequency semiconductor device 25a according to the second embodiment, the drain terminal electrodes D1 to D4 have an electrode pattern shape that allows a plurality of pattern sizes of the resistor 50 to be selected. That is, FIG. 15 discloses an example in which the drain terminal electrodes D1 to D4 have an inverted trapezoidal shape, and the distance between the side portions between the adjacent drain terminal electrodes D1 to D4 is the upper base of the trapezoid. And the bottom is very different. Therefore, by appropriately selecting the patterning position of the resistor 50, a plurality of values of the resistor 50 can be selected without changing the pattern size. That is, in FIG. 15, the pattern size of the resistor 50 is not changed by performing patterning of the resistor 50 on the vertical positions between the adjacent drain terminal electrodes D1 and D2, D2 and D3, and D3 and D4. In addition, the resistance value can be changed.

  In the high-frequency semiconductor device 25a according to the second embodiment, the resistor 30 and the resistor 50 necessary for stopping the loop oscillation of each mode such as the odd mode and the even mode, or the frequency oscillation of the operating frequency are provided. The value can be optimized. In addition, the necessary values of the resistor 30 and the resistor 50 can be optimized according to the operating frequency of the high-frequency semiconductor device 25a. In FIG. 2, the resistor 30 is represented by RG, the resistor 50 is represented by RD, and each FET constituting the FET cell 40 is represented by Q1 to Q4, and loop oscillation or frequency division oscillation of the operating frequency. Can be stopped by the resistor RG connected between the adjacent gate terminal electrodes G1 to G4 and the resistor RD connected between the adjacent drain terminal electrodes D1 to D4.

  Here, the value of the resistor 50 can be appropriately selected from several Ω to several hundred Ω depending on the operating frequency. In the high-frequency semiconductor device 25a according to the second embodiment, the value of the resistor 50 is, for example, about 50Ω to 100Ω with respect to the operating frequency of about 8 GHz to 14 GHz.

  In the configuration example of FIG. 15, for example, the cell width W1 is about 120 μm, W2 is about 80 μm, the cell length W3 is about 100 μm, W4 is about 120 μm, and the gate width is 100 μm × 6 pieces × 4 cells = 2.40 mm or so.

  Also in the high-frequency semiconductor device 25a according to the second embodiment, the VIA holes SC1 to SC5 respectively disposed below the source terminal electrodes S1 to S5, and the second surface opposite to the first surface of the substrate 10 And a ground electrode connected to the source terminal electrodes S1 to S5 via the VIA holes SC1 to SC5.

  On the other hand, there is a structure in which the VIA holes SC1 to SC5 are not particularly arranged below the source terminal electrodes S1 to S5. In this case, for example, a side electrode is disposed on the side surface of the substrate 10 to provide a ground potential to the source terminal electrodes S1 to S5, and the source terminal electrodes S1 to S5 and the second surface of the substrate 10 are provided. You may employ | adopt the structure which connects the arrange | positioned grounding conductor. Alternatively, the ground potential can be applied to the source terminal electrodes S1 to S5 by wire bonding.

  In the high-frequency semiconductor device according to the second embodiment, the substrate 10 is, for example, a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on a SiC substrate, or GaN / AlGaN on a SiC substrate. The heterojunction epitaxial layer can be formed of any one of a substrate, a sapphire substrate, and a diamond substrate.

  The configuration of the resistor 50 can be formed in the same manner as the resistor 30 in the first embodiment. That is, the resistor 50 may include the metal thin film layer 36 disposed on the substrate 10 as in FIG. The resistor 50 may include a diffusion layer 32 disposed on the substrate 10 as in FIG. Further, the resistor 50 may be formed by patterning the substrate 10 with the diffusion layer 32 disposed on the substrate 10. Further, the resistor 50 may include a metal thin film layer 36 disposed on the substrate 10 via the insulating layer 34 as in FIG.

(Modification)
A schematic circuit configuration of the high-frequency semiconductor device 25b according to the first modification of the second embodiment is expressed as shown in FIG. In the high-frequency semiconductor device 25b according to the first modification of the second embodiment, as shown in FIG. 17, it is disposed between the drain terminal electrodes D1 and D2, D2 and D3, and D3 and D4 of adjacent FET cells 40. The resistor 50 is provided, and no resistor is disposed between the gate terminal electrodes G1 and G2, G2 and G3, and G3 and G4 of the adjacent FET cells 40. A plurality of distances between the drain terminal electrodes can be selected depending on a position where the resistor 50 is disposed.

  In the high-frequency semiconductor device 25b according to the first modification of the second embodiment, the resistor 50 necessary for stopping the loop oscillation in each mode such as the odd mode and the even mode, or the frequency division oscillation of the operating frequency is provided. The value can be optimized. In addition, the required value of the resistor 50 can be optimized according to the operating frequency of the high-frequency semiconductor device 25b. In FIG. 17, the resistor 50 is represented by RD, and the FETs constituting the FET cell 40 are represented by Q1 to Q4, and the loop oscillation or the divided oscillation of the operating frequency is applied to the adjacent drain terminal electrodes D1 to D1. It can be stopped by a resistor RD connected between D4.

  Here, the value of the resistor 50 can be appropriately selected from several Ω to several hundred Ω depending on the operating frequency. In the high-frequency semiconductor device 25b according to the first modification of the second embodiment, the value of the resistor 50 is, for example, about 50Ω to 100Ω with respect to an operating frequency of about 8 GHz to 14 GHz.

  In the high-frequency semiconductor device 25a according to the second embodiment, the gate terminal electrodes G1 to G4 have a trapezoidal shape, a convex shape, a drum shape, an elliptical shape, a triangular shape, a step shape, and a torch shape. Further, it may have a shape made of any one of the bee-shaped shapes or a combination thereof.

  A schematic planar pattern configuration of the high-frequency semiconductor device 25a according to the second modification of the second embodiment is expressed as shown in FIG. In Modification 2 shown in FIG. 18, an example is disclosed in which the gate terminal electrodes G1 to G4 have an inverted convex shape. The other configuration is the same as that of the second embodiment, and a duplicate description is omitted.

  A schematic planar pattern configuration of the drain terminal electrodes D1 to D4 and the resistor 50 portion of the high-frequency semiconductor device 25a according to the third modification of the second embodiment is expressed as shown in FIG. In Modified Example 3 shown in FIG. 19A, an example in which the drain terminal electrodes D1 to D4 have a trapezoidal shape is disclosed. Other configurations are the same as those of the first embodiment and its modifications 1 to 9, and thus redundant description is omitted.

  A schematic planar pattern configuration of the drain terminal electrodes D1 to D4 and the resistor 50 portion of the high-frequency semiconductor device 25a according to the fourth modification of the second embodiment is expressed as shown in FIG. In Modified Example 4 shown in FIG. 19B, an example is disclosed in which the drain terminal electrodes D1 to D4 have an hourglass shape. Other configurations are the same as those of the first embodiment and its modifications 1 to 9, and thus redundant description is omitted.

  A schematic planar pattern configuration of the drain terminal electrodes D1 to D4 and the resistor 50 portion of the high-frequency semiconductor device 25a according to the modification 5 of the second embodiment is expressed as shown in FIG. In Modification 5 shown in FIG. 20A, an example in which the drain terminal electrodes D1 to D4 have a convex shape is disclosed. Other configurations are the same as those of the first embodiment and its modifications 1 to 9, and thus redundant description is omitted.

  A schematic planar pattern configuration of the drain terminal electrodes D1 to D4 and the resistor 50 portion of the high-frequency semiconductor device 25a according to the modification 6 of the second embodiment is expressed as shown in FIG. In Modification 6 shown in FIG. 20B, an example in which the drain terminal electrodes D1 to D4 have an elliptical shape is disclosed. Other configurations are the same as those of the first embodiment and its modifications 1 to 9, and thus redundant description is omitted.

  A schematic planar pattern configuration of the drain terminal electrodes D1 to D4 and the resistor 50 portion of the high-frequency semiconductor device 25a according to Modification 7 of the second embodiment is expressed as shown in FIG. In Modification 7 shown in FIG. 20A, an example in which the drain terminal electrodes D1 to D4 have a torch shape is disclosed. Other configurations are the same as those of the first embodiment and its modifications 1 to 9, and thus redundant description is omitted.

  A schematic planar pattern configuration of the drain terminal electrodes D1 to D4 and the resistor 50 portion of the high-frequency semiconductor device 25a according to Modification 8 of the second embodiment is expressed as shown in FIG. In Modification 8 shown in FIG. 21B, an example in which the drain terminal electrodes D1 to D4 have a bee-shaped shape is disclosed. Other configurations are the same as those of the first embodiment and its modifications 1 to 9, and thus redundant description is omitted.

  A schematic planar pattern configuration of the drain terminal electrodes D1 to D4 and the resistor 50 portion of the high-frequency semiconductor device 25a according to the modification 9 of the second embodiment is expressed as shown in FIG. In Modification 9 shown in FIG. 22A, an example in which the drain terminal electrodes D1 to D4 have a stepped shape is disclosed. Other configurations are the same as those of the first embodiment and its modifications 1 to 9, and thus redundant description is omitted.

  A schematic planar pattern configuration of the drain terminal electrodes D1 to D4 and the resistor 50 portion of the high-frequency semiconductor device 25a according to Modification 10 of the second embodiment is expressed as shown in FIG. In Modification 10 shown in FIG. 22B, an example in which the drain terminal electrodes D1 to D4 have a triangular shape is disclosed. Other configurations are the same as those of the first embodiment and its modifications 1 to 9, and thus redundant description is omitted.

  According to the second embodiment of the present invention and modifications 1 to 10 thereof, a resistor having an optimum resistance value is connected between the gate terminal electrodes and / or between the drain terminal electrodes with respect to an arbitrary operating frequency. It is possible to provide a high-frequency semiconductor device that can be selectively arranged without changing the pattern size and suppresses loop oscillation and frequency division oscillation.

[Other embodiments]
As described above, the present invention has been described with reference to the first and second embodiments and the modifications thereof. However, the description and the drawings that constitute a part of this disclosure are exemplary and limit the present invention. Should not be understood. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the high-frequency semiconductor device according to the first to second embodiments, it is possible to adopt a configuration in which the drain terminal electrode is integrated.

  The elements applied to the high-frequency semiconductor device of the present invention are not limited to FETs, but include high electron mobility transistors (HEMTs), LDMOS (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistors), and heterojunctions. Needless to say, an amplifying element such as a bipolar transistor (HBT) or a micro electro mechanical systems (MEMS) element can also be applied.

  As described above, the present invention includes various embodiments that are not described herein.

  The high-frequency semiconductor device of the present invention can be applied to a wide range of fields such as an internal matching power amplification element, a power MMIC, a microwave power amplifier, a millimeter-wave power amplifier, and a high-frequency MEMS element.

10 ... Substrate 12 ... Epitaxial growth layer
16 ... Two-dimensional electron gas (2DEG) layer 18 ... Electron supply layer 20 ... Source finger electrode 22 ... Drain finger electrode 24 ... Gate finger electrodes 24a, 24b ... Gate bus lines 25, 25a, 25b ... High frequency semiconductor device 26 ... Source region 28 ... Drain region 30, 50 ... Resistor 32 ... Diffusion layer 34 ... Insulating layer 36 ... Metal thin film layer 40 ... FET cells G1, G2, ..., G4 ... Gate terminal electrodes S1, S2, ..., S5 ... Source terminal electrode D , D1, D2, ..., D4 ... drain terminal electrodes SC1 to SC5 ... VIA holes

Claims (18)

A substrate, a gate finger electrode having a plurality of fingers, a source finger electrode and a drain finger electrode disposed on a first surface of the substrate; and a gate finger electrode and the source finger disposed on the first surface of the substrate. A plurality of FET cells each having a gate terminal electrode, a source terminal electrode and a drain terminal electrode formed by bundling a plurality of fingers for each electrode and the drain finger electrode;
A first resistor disposed between the gate terminal electrodes of the adjacent FET cells, and a plurality of distances between the gate terminal electrodes of the adjacent FET cells are selected depending on a position where the first resistor is disposed A high-frequency semiconductor device, which is possible.   2. The high-frequency semiconductor device according to claim 1, wherein the gate terminal electrode has an electrode pattern shape in which a plurality of values of the first resistor can be selected without changing a pattern size.   The gate terminal electrode has a trapezoidal shape, a convex shape, a drum shape, an elliptical shape, a triangular shape, a step shape, a torch shape, a bee shape, or a combination thereof. The high-frequency semiconductor device according to claim 1.   The high-frequency semiconductor device according to claim 1, wherein the first resistor includes a metal thin film layer disposed on the substrate.   The high-frequency semiconductor device according to claim 1, wherein the first resistor includes a diffusion layer disposed on the substrate.   The high-frequency semiconductor device according to claim 1, wherein the first resistor is formed by patterning the substrate with a diffusion layer disposed on the substrate.   The high-frequency semiconductor device according to claim 1, wherein the first resistor includes a metal thin film layer disposed on the substrate via an insulating layer.   A VIA hole disposed under the source terminal electrode, and a ground electrode disposed on the second surface opposite to the first surface of the substrate and connected to the source terminal electrode via the VIA hole; The high-frequency semiconductor device according to claim 1, comprising:   A second resistor disposed between the drain terminal electrodes of the adjacent FET cells is provided, and a plurality of distances between the drain terminal electrodes can be selected depending on a position where the second resistor is disposed. The high-frequency semiconductor device according to claim 1.   10. The high-frequency semiconductor device according to claim 9, wherein the drain terminal electrode has an electrode pattern shape in which a plurality of values of the second resistor can be selected without changing a pattern size.   The drain terminal electrode has a trapezoidal shape, a convex shape, a drum shape, an elliptical shape, a triangular shape, a stepped shape, a torch shape, a bee shape, or a combination thereof. The high-frequency semiconductor device according to claim 9.   The high-frequency semiconductor device according to claim 9, wherein the second resistor includes a metal thin film layer disposed on the substrate.   The high-frequency semiconductor device according to claim 9, wherein the second resistor includes a diffusion layer disposed on the substrate.   The high-frequency semiconductor device according to claim 9, wherein the second resistor is formed by patterning the substrate with a diffusion layer disposed on the substrate.   The high frequency semiconductor device according to any one of claims 9 to 11, wherein the second resistor includes a metal thin film layer disposed on the substrate via an insulating layer.   A VIA hole disposed under the source terminal electrode, and a ground electrode disposed on the second surface opposite to the first surface of the substrate and connected to the source terminal electrode via the VIA hole; The high-frequency semiconductor device according to claim 9, comprising:   The substrate is a GaAs substrate, a SiC substrate, a GaN substrate, a substrate in which a GaN epitaxial layer is formed on the SiC substrate, a substrate in which a heterojunction epitaxial layer made of GaN / AlGaN is formed on the SiC substrate, and a GaAs / AlGaAs on the GaAs substrate. 17. The high-frequency semiconductor device according to claim 1, wherein the high-frequency semiconductor device is any one of a substrate, a sapphire substrate, and a diamond substrate on which a heterojunction epitaxial layer made of is formed.   The high-frequency semiconductor device according to claim 1, wherein the FET cell includes any one of a GaAs-based HEMT, a GaAs MESFET, and a GaN-based HEMT.

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