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JP2009021499A - 積層型半導体装置 - Google Patents

積層型半導体装置 Download PDF

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Publication number
JP2009021499A
JP2009021499A JP2007184467A JP2007184467A JP2009021499A JP 2009021499 A JP2009021499 A JP 2009021499A JP 2007184467 A JP2007184467 A JP 2007184467A JP 2007184467 A JP2007184467 A JP 2007184467A JP 2009021499 A JP2009021499 A JP 2009021499A
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JP
Japan
Prior art keywords
semiconductor element
metal wire
stacked
semiconductor device
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007184467A
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English (en)
Inventor
Katsuhiro Ishida
勝広 石田
Ryoji Matsushima
良二 松嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2007184467A priority Critical patent/JP2009021499A/ja
Priority to US12/170,062 priority patent/US7968993B2/en
Publication of JP2009021499A publication Critical patent/JP2009021499A/ja
Pending legal-status Critical Current

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Abstract

【課題】複数の半導体素子を積層して樹脂封止するにあたって、上段側半導体素子に接続された金属ワイヤの樹脂封止時におけるワイヤ流れを抑制する。
【解決手段】積層型半導体装置１は、回路基板２上に搭載された第１の半導体素子５と、その上に積層された第２の半導体素子１０とを具備する。第１および第２の半導体素子５、１０の電極パッドは、第１および第２の金属ワイヤ９、１４を介して回路基板２の接続パッド４と電気的に接続されている。第２の金属ワイヤ１４はその一部が第１の半導体素子５の表面を覆う絶縁性保護膜８と接触するように配置されている。
【選択図】図３

Description

本発明は複数の半導体素子を積層した積層型半導体装置に関する。
半導体装置の小型化や高密度実装化等を実現するために、１つのパッケージ内に複数の半導体素子を積層して封止した積層型半導体装置が実用化されている。積層型半導体装置において、複数の半導体素子は配線基板やリードフレーム等の回路基材上に接着剤層を介して順に積層される。各半導体素子の電極パッドは、回路基材の接続部とボンディングワイヤを介して電気的に接続される。このような積層体を樹脂封止することによって、スタック型マルチチップパッケージ等の積層型半導体装置が構成される。
例えば、半導体メモリ装置は１個もしくは複数個のメモリ素子とコントローラ素子とから構成される。半導体メモリ装置に積層構造を適用する場合、１個もしくは多段に積層されたメモリ素子上に、それより小型のコントローラ素子が積層される。このため、大型のメモリ素子（下段側半導体素子）上に積層された小型のコントローラ素子（上段側半導体素子）に対するボンディング長さが必然的に長くなる。上段側半導体素子に接続されたボンディングワイヤは素子形状が異なるほど長ループ化する傾向にある。さらに、ボンディングワイヤ自体は半導体素子のパッド面積の微小化等に伴って細線化する傾向にある。
複数の半導体素子の積層体を樹脂封止する場合、上段側半導体素子に接続されたボンディングワイヤが偏移（ワイヤ流れ）を起こしやすく、隣接する異電位ワイヤ間の接触によるショート不良等を引起す要因となっている。ワイヤ流れはボンディングワイヤが長ループ化するほど、さらにボンディングワイヤが細線化するほど生じやすくなっている。特に、ワイヤ流れはボンディングワイヤの水平面に平衡に張られた平坦部の偏移よりも、回路基材からの立ち上り部や平坦部との屈曲点が倒れる現象が問題となる。
なお、特許文献１には半導体素子の中央付近に設けられた電極パッドに金属ワイヤを接続するにあたって、半導体素子の電極パッドに金属ワイヤの一端をボール接続した後、金属ワイヤをそれが接続された半導体素子の表面絶縁膜と接触させつつ繰り出し、金属ワイヤの他端を外部端子に圧着して接続することが開示されている。ここでは金属ワイヤが素子端部（角部）と接触することを防止するために、金属ワイヤをそれが接続された素子表面自体に接触させているだけであり、金属ワイヤの樹脂封止時におけるワイヤ流れ、さらには積層型半導体装置における上段側半導体素子に接続された金属ワイヤのワイヤ流れを防止することについては考慮されていない。
特開２００５−１１６９１５号公報
本発明の目的は、複数の半導体素子を積層して樹脂封止するにあたって、上段側半導体素子に接続された金属ワイヤの樹脂封止時におけるワイヤ流れを抑制することによって、製造歩留りや信頼性等を向上させた積層型半導体装置を提供することにある。
本発明の態様に係る積層型半導体装置は、素子搭載部と接続部とを有する回路基材と、半導体素子本体と、前記半導体素子本体の表面に配置された電極パッドと、前記電極パッドを露出させつつ前記表面を覆う絶縁性保護膜とを有し、前記回路基材の素子搭載部上に搭載された第１の半導体素子と、半導体素子本体と、前記半導体素子本体の表面に配置された電極パッドとを有し、前記第１の半導体素子上に積層された第２の半導体素子と、前記回路基材の前記接続部と前記第１の半導体素子の前記電極パッドとを電気的に接続する第１の金属ワイヤと、前記回路基材の前記接続部と前記第２の半導体素子の前記電極パッドとを電気的に接続する第２の金属ワイヤであって、その一部が前記第１の半導体素子の前記絶縁性保護膜と接触するように配置された第２の金属ワイヤと、前記第１および第２の半導体素子を前記第１および第２の金属ワイヤと共に封止する樹脂封止部とを具備することを特徴としている。
本発明の態様に係る積層型半導体装置によれば、上段側の半導体素子に接続された金属ワイヤの樹脂封止時におけるワイヤ流れを抑制することができる。これによって、隣接する異電位ワイヤ間の接触によるショート不良の発生等が抑制されるため、製造歩留りや信頼性に優れる積層型半導体装置を提供することが可能となる。
以下、本発明を実施するための形態について、図面を参照して説明する。図１は本発明の実施形態による積層型半導体装置の構成を示す平面図、図２はその断面図、図３はその一部を拡大して示す断面図である。これらの図に示す積層型半導体装置１は、素子搭載用の回路基材として回路基板２を有している。回路基板２は半導体素子を搭載することが可能で、かつ表面や内部に設けられた配線網を有するものであればよい。回路基材はリードフレームのような素子搭載部と回路部とを一体化したものであってもよい。
回路基板２を構成する基板には、樹脂基板、セラミックス基板、ガラス基板等の絶縁基板、あるいは半導体基板を適用することができる。回路基板２の具体例としては、ガラス−エポキシ樹脂やＢＴ樹脂（ビスマレイミド・トリアジン樹脂）等を使用したプリント配線基板が挙げられる。回路基板２の下面側には外部接続端子３が設けられている。ここではＢＧＡパッケージに適用する積層型半導体装置１を示しているため、回路基板２の下面に外部接続端子３として半田バンプを設けている。積層型半導体装置１はＬＧＡパッケージ等にも適用可能であり、この場合には外部接続端子３として金属ランドが適用される。
回路基板２の上面には素子搭載部が設けられており、その周囲には外部接続端子３と配線網を介して電気的に接続された接続パッド４が設けられている。接続パッド４はワイヤボンディング時の接続部となる。回路基板２の素子搭載面には第１の半導体素子５が第１の接着層６を介して接着されている。第１の半導体素子５はトランジスタを含む回路が形成された素子本体の表面（上面）に配置された第１の電極パッド７を有している。第１の半導体素子５の上面は第１の電極パッド７を露出させるように設けられた第１の絶縁性保護膜８で覆われている。絶縁性保護膜８にはＳｉＯx膜やＳｉＮx膜等のパッシベーション膜、さらにその上に形成されたポリイミド樹脂層等の絶縁樹脂層が適用される。
第１の電極パッド７はＡｕワイヤ等の第１の金属ワイヤ９を介して回路基板２の接続パッド４と電気的に接続されている。第１の電極パッド７は、第１の半導体素子５の外形を構成する一辺、具体的には一方の長辺に沿って配列されている。第１の半導体素子５は長辺片側パッド構造を有している。回路基板２の接続パッド４の一部は第１の電極パッド７と対応するように配置されている。第１の金属ワイヤ９は接続パッド４から第１の電極パッド７に向けてワイヤリングされており、第１の金属ワイヤ９の各端部は接続パッド４と第１の電極パッド７に接続されている。
第１の半導体素子５上には第２の半導体素子１０が第２の接着層１１を介して接着されている。第２の半導体素子１０はトランジスタを含む回路が形成された素子本体の表面（上面）に配置された第２の電極パッド１２を有している。第２の半導体素子１０の上面は第２の電極パッド１２を露出させるように設けられた第２の絶縁性保護膜１３で覆われている。絶縁性保護膜１３にはＳｉＯx膜やＳｉＮx膜等のパッシベーション膜、さらにその上に形成されたポリイミド樹脂層等の絶縁樹脂層が適用される。第２の電極パッド１２は第２の半導体素子１０の外形を構成する辺のうち、隣接する二辺に沿って配列されている。第２の半導体素子１０はＬ型パッド構造を有している。
第２の電極パッド１２はＡｕワイヤ等の第２の金属ワイヤ１４を介して回路基板２の接続パッド４と電気的に接続されている。回路基板２の接続パッド４の一部は第２の電極パッド１２と対応するように配置されている。第２の金属ワイヤ１４は接続パッド４から第２の電極パッド１２に向けてワイヤリングされている。具体的には、第２の金属ワイヤ１４の一端は接続パッド４にボール接続されており、他端は第２の電極パッド１２上に予め形成された金属バンプ（Ａｕバンプ等）１５に接続されている。第２の金属ワイヤ１４はリバースボンディングを適用したものであり、第１の金属ワイヤ９も同様である。
第１の半導体素子５の具体例としては、ＮＡＮＤ型フラッシュメモリのような半導体メモリ素子が挙げられる。第２の半導体素子１０の具体例としては、半導体メモリ素子より小さい外形形状を有するコントローラ素子が挙げられる。第２の半導体素子１０はこれに限られるものではなく、コントローラ素子と同様にＮＡＮＤ型フラッシュメモリ等に比べて小形なＰＳＲＡＭ（Ｐｓｅｕｄｏ Ｓｔａｔｉｃ ＲＡＭ）等であってもよい。第１の半導体素子５は１個に限られるものではなく、複数個を積層して配置してもよい。
図４および図５は２個の半導体素子５Ａ、５Ｂを積層して回路基板２上に配置し、さらにその上に第２の半導体素子１０を積層した状態を示している。２個の半導体素子５Ａ、５Ｂは各電極パッド７Ａ、７Ｂが露出するように階段状に積層されている。すなわち、２個の半導体素子５Ａ、５Ｂの短辺を揃え、かつ長辺を電極パッド７Ａが露出するようにずらして積層されている。電極パッド７Ａ、７Ｂは接続パッド４と金属ワイヤ９を介して電気的に接続されている。これら電極パッド７Ａ、７Ｂの電気特性や信号特性等が等しい場合には、電極パッド７Ｂに接続された金属ワイヤ９を電極パッド７Ａに接続し、この電極パッド７Ａを介して接続パッド４と電気的に接続することができる。
そして、回路基板２上に積層された第１および第２の半導体素子５、１０を第１および第２の金属ワイヤ９、１４と共に、エポキシ樹脂のような封止樹脂で封止して樹脂封止部１６を形成することによって、スタック型マルチチップパッケージ構造を有する積層型半導体装置１が構成されている。図１では樹脂封止部１６の図示を省略している。図３では外部接続端子３および樹脂封止部１６の図示を省略している。後述する図６ないし図８も同様である。積層型半導体装置１は半導体メモリ装置等に適用されるスタック型マルチチップパッケージに限らず、メモリ素子とロジック素子とを組合せたＳＩＰ（Ｓｙｓｔｅｍ ｉｎ Ｐａｃｋａｇｅ）等であってもよい。
ここで、上段側の第２の半導体素子１０は下段側の第１の半導体素子４に比べて外形が小さいため、第２の金属ワイヤ１４のワイヤ長さは必然的に長くなる。このため、トランスファー成形等を適用した樹脂封止部１６を作製した際に、ワイヤ長さが長い第２の金属ワイヤ１４は樹脂流で偏移しやすく、これにより隣接する異電位ワイヤ間の接触によるショート不良等が発生するおそれがある。樹脂封止時におけるワイヤ流れは、第２の金属ワイヤ１４のワイヤリング方向に沿った第２の半導体素子１０の外形辺から第１の半導体素子５の外形辺までの距離Ｌが３ｍｍ以上の場合に生じやすい。さらに、第２の金属ワイヤ１４のワイヤ径が２５μｍ以下の場合にもワイヤ流れが生じやすい。
そこで、この実施形態では第２の金属ワイヤ１０の一部を第１の半導体素子５の絶縁性保護膜８と接触させている。図３に示す第２の金属ワイヤ１４には、まず接続パッド４からの立ち上り部の端部に第１の屈曲部１７が設けられている。第１の屈曲部１７は第２の金属ワイヤ１４の立ち上り部を第２の電極パッド１２の方向に向けるものであるが、通常のリバースボンディングより若干大きく屈曲させることによって、第１の半導体素子５の絶縁性保護膜８の方向に向けている。そして、第２の金属ワイヤ１４の中間部分に第１の半導体素子５から離れる方向に屈曲させた第２の屈曲部１８を設けることによって、第２の金属ワイヤ１４の中間部分を絶縁性保護膜８上に着地させている。
絶縁性保護膜８上に着地させた第２の金属ワイヤ１４には、さらに第２の電極パッド１２との接続部分の近傍に第２の屈曲部１８とは反対方向に屈曲させた第３の屈曲部１９が設けられている。これによって、第２の金属ワイヤ１４の素子側端部を第２の電極パッド１２上に設けられた金属バンプ１５に接続している。図３では第２の金属ワイヤ１４が第１の半導体素子５の外周部側に着地するように第２の屈曲部１８を設けているが、第２の屈曲部１８は図６に示すように第２の半導体素子１０に寄せた位置に設けてもよい。第２の金属ワイヤ１４は絶縁性保護膜８上であれば任意の位置に着地させることができる。
さらに、図３や図６では第２の金属ワイヤ１４の絶縁性保護膜８に対する着地箇所を１箇所とした状態を示しているが、第２の金属ワイヤ１４は絶縁性保護膜８に対して複数箇所で着地させてもよい。図７に示す第２の金属ワイヤ１４は、絶縁性保護膜８に対する第１の着地点である第２の屈曲部１８の近傍に第３の屈曲部１９と第４の屈曲部２０を設けている。第３の屈曲部１９は第２の屈曲部１８とは反対方向（第１の半導体素子５に向かう方向）に屈曲させており、第４の屈曲部２０は第３の屈曲部１９とは反対方向（第１の半導体素子５から離れる方向）に屈曲させている。
第３および第４の屈曲部１９、２０は絶縁性保護膜８上に位置している。これらによって、第２の金属ワイヤ１４は第４の屈曲部２０が絶縁性保護膜８上に着地している。すなわち、第２の金属ワイヤ１４は第２の屈曲部１８と第４の屈曲部２０の２箇所で絶縁性保護膜８上に着地している。そして、第２の電極パッド１２との接続部分の近傍に第５の屈曲部２１を設けることによって、第２の金属ワイヤ１４の素子側端部を第２の電極パッド１２上に設けられた金属バンプ１５に接続している。
第２の金属ワイヤ１４の絶縁性保護膜８に対する接触形状は、屈曲部を絶縁性保護膜８上に着地させた形態に限られるものではない。第２の金属ワイヤ１４は図８に示すように、その一部を絶縁性保護膜８上に這わせるようにしてもよい。図８に示す第２の金属ワイヤ１４は絶縁性保護膜８上に第２の屈曲部１８と第３の屈曲部１９が設けられている。第２の屈曲部１８と第３の屈曲部１９との間の形状は絶縁性保護膜８と平行とされており、これによって第２の金属ワイヤ１４の中間部分を絶縁性保護膜８上に這わせている。そして、第２の金属ワイヤ１４の素子側端部に第４の屈曲部２０を設けることによって、第２の金属ワイヤ１４を第２の電極パッド１２に接続している。
第２の金属ワイヤ１４に対する屈曲部の形成は、ワイヤルーピング時に実施することができる。第２の金属ワイヤ１４はリバースボンディンクを適用して接続されるため、まず第２の電極パッド１２上に金属バンプ１５を形成する。次いで、ボンディングツールに保持された金属ワイヤの先端に金属ボールを形成し、この金属ボールを回路基板２の接続パッド４に対して接続（ボール接続）する。続いて、ボンディングツールから金属ワイヤを繰り出してワイヤリングループを形成しつつ、ボンディングツールを第２の電極パッド１２上に形成された金属バンプ１５の上方に移動させる。
この際、ボンディングツールの移動方向を制御することによって、金属ワイヤに屈曲部（ワイヤのくせ）を形成する。金属ワイヤには必要に応じた個数の屈曲部が設けられる。例えば、図３に示したワイヤ形状の場合、金属ワイヤに３箇所の屈曲部が形成される。このように、ボンディングツールの動作に基づいて屈曲部を形成した金属ワイヤを、通常のリバースボンディングと同様に、第２の電極パッド１２上の金属バンプ１５に接続（ステッチ接続）することによって、金属ワイヤの中間部分が屈曲部の形状に基づいて絶縁性保護膜８上に着地する。また、屈曲部の個数や形状によっては、第２の金属ワイヤ１４の中間部分を絶縁性保護膜８上に這わせることができる。
リバースボンディングは第２の金属ワイヤ１４のループ高さを低くできることに加えて、屈曲部の形成が容易であるという利点がある。すなわち、第２の半導体素子１０の電極パッド１２にボール接続する通常のボンディング（正ボンディング）を適用した場合、金属ワイヤに屈曲部を形成するためにはボンディングツールをリバース動作させる必要がある。このため、正ボンディングでは屈曲部の形成が難しい。これに対して、リバースボンディングの場合には通常の動作の延長線上で屈曲部を形成することができる。従って、第２の金属ワイヤ１４の絶縁性保護膜８に対する接触性を高めることが可能となる。
上述したように、第２の金属ワイヤ１４の中間部分を絶縁性保護膜８に接触させる（着地もしくは這わせる）ことによって、トランスファー成形等を適用して樹脂封止部１６を作製する際の樹脂流によるワイヤ流れを防止することができる。これは第２の金属ワイヤ１４が絶縁性保護膜８と接触していることに加えて、第２の金属ワイヤ１４を絶縁性保護膜８に接触させるように屈曲させた形状に基づくものである。すなわち、第２の金属ワイヤ１４を絶縁性保護膜８に接触させることでループ高さを低くすることができる。さらに、第２の金属ワイヤ１４の屈曲部が多くなることでワイヤ剛性が向上する。これらによって、樹脂封止時におけるワイヤ流れを防止することが可能となる。
さらに、第２の金属ワイヤ１４は第２の電極パッド１２からの距離が長くなる立ち上り部が樹脂流で転倒しやすい。このような点に対して、第２の金属ワイヤ１４を絶縁性保護膜８と接触させることで、立ち上り部および第１の屈曲部１７から支点となる位置（ここでは絶縁性保護膜８に対する接触部分）までの距離が短くなるため、第２の金属ワイヤ１４の立ち上り部の転倒を抑制することができる。第２の金属ワイヤ１４の絶縁性保護膜８との接触によるワイヤ流れの抑制効果は、特にワイヤリング方向に沿った第２の半導体素子１０の外形辺から第１の半導体素子５の外形辺までの距離Ｌが３ｍｍ以上で、かつ第２の金属ワイヤ１４のワイヤ径が２５μｍ以下の場合に有効である。
そして、第２の金属ワイヤ１４のワイヤ流れを防ぐことによって、異電位ワイヤ間の接触によるショート不良の発生等を抑制することができる。従って、積層型半導体装置１の製造歩留りや信頼性を高めることが可能となる。さらに、封止樹脂を選定する際にワイヤ流れの防止を考慮する必要がなくなるため、他の不具合（例えば充填性や反り等）に特化した樹脂を選定することができ、これによって積層型半導体装置１の製造歩留りをさらに高めることができる。このように、この実施形態によれば信頼性に優れる積層型半導体装置１を高歩留りで提供することが可能となる。
なお、本発明は上記した各実施形態に限定されるものではなく、複数の半導体素子を積層して回路基材上に搭載すると共に、各半導体素子の接続にワイヤボンディングを適用した各種の積層型半導体装置に適用することができる。そのような積層型半導体装置も本発明に含まれるものである。また、本発明の実施形態は本発明の技術的思想の範囲内で拡張もしくは変更することができ、この拡張、変更した実施形態も本発明の技術的範囲に含まれるものである。
本発明の実施形態による積層型半導体装置を示す平面図である。 図１に示す積層型半導体装置の断面図である。 図１に示す積層型半導体装置の一部を拡大して示す断面図である。 図１に示す積層型半導体装置の変形例を示す平面図である。 図４に示す積層型半導体装置の断面図である。 図３に示す積層型半導体装置の変形例を示す断面図である。 図３に示す積層型半導体装置の他の変形例を示す断面図である。 図３に示す積層型半導体装置のさらに他の変形例を示す断面図である。
符号の説明
１…積層型半導体装置、２…回路基板、３…外部接続端子、４…接続パッド、５…第１の半導体素子、７…第１の電極パッド、８，１３…絶縁性保護膜、９…第１の金属ワイヤ、１０…第２の半導体素子、１２…第２の電極パッド、１４…第２の金属ワイヤ、１５…金属バンプ、１６…樹脂封止部、１７，１８，１９，２０，２１…屈曲部。

Claims (5)

  1. 素子搭載部と接続部とを有する回路基材と、
    半導体素子本体と、前記半導体素子本体の表面に配置された電極パッドと、前記電極パッドを露出させつつ前記表面を覆う絶縁性保護膜とを有し、前記回路基材の素子搭載部上に搭載された第１の半導体素子と、
    半導体素子本体と、前記半導体素子本体の表面に配置された電極パッドとを有し、前記第１の半導体素子上に積層された第２の半導体素子と、
    前記回路基材の前記接続部と前記第１の半導体素子の前記電極パッドとを電気的に接続する第１の金属ワイヤと、
    前記回路基材の前記接続部と前記第２の半導体素子の前記電極パッドとを電気的に接続する第２の金属ワイヤであって、その一部が前記第１の半導体素子の前記絶縁性保護膜と接触するように配置された第２の金属ワイヤと、
    前記第１および第２の半導体素子を前記第１および第２の金属ワイヤと共に封止する樹脂封止部と
    を具備することを特徴とする積層型半導体装置。
  2. 請求項１記載の積層型半導体装置において、
    前記第２の金属ワイヤはその中間部分を１箇所または複数箇所で前記絶縁性保護膜上に着地させているか、もしくは前記絶縁性保護膜上に這わせていることを特徴とする積層型半導体装置。
  3. 請求項１または請求項２記載の積層型半導体装置において、
    前記第２の金属ワイヤの一端は前記回路基材の前記接続部にボール接続されており、かつ他端は前記第１の半導体素子の前記電極パッド上に形成された金属バンプに接続されていることを特徴とする積層型半導体装置。
  4. 請求項１ないし請求項３のいずれか１項記載の積層型半導体装置において、
    前記第２の金属ワイヤは、前記接続部からの立ち上り部の端部に設けられた第１の屈曲部と、前記絶縁性保護膜との接触部分の近傍に設けられ、前記第１の半導体素子から離れる方向に屈曲させた第２の屈曲部と、前記第２の電極パッドとの接続部分の近傍に設けられ、第２の屈曲部とは反対方向に屈曲させた第３の屈曲部とを有することを特徴とする積層型半導体装置。
  5. 請求項１ないし請求項４のいずれか１項記載の積層型半導体装置において、
    前記第２の半導体素子は前記第１の半導体素子より小さい外形を有し、かつ積層時における前記第２の半導体素子の外形辺から前記第１の半導体素子の外形辺までの距離が３ｍｍ以上であることを特徴とする積層型半導体装置。
JP2007184467A 2007-07-13 2007-07-13 積層型半導体装置 Pending JP2009021499A (ja)

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